dma.h 2.9 KB

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  1. /* SPDX-License-Identifier: ISC */
  2. /*
  3. * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
  4. */
  5. #ifndef __MT76_DMA_H
  6. #define __MT76_DMA_H
  7. #define DMA_DUMMY_DATA ((void *)~0)
  8. #define MT_RING_SIZE 0x10
  9. #define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0)
  10. #define MT_DMA_CTL_LAST_SEC1 BIT(14)
  11. #define MT_DMA_CTL_BURST BIT(15)
  12. #define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16)
  13. #define MT_DMA_CTL_LAST_SEC0 BIT(30)
  14. #define MT_DMA_CTL_DMA_DONE BIT(31)
  15. #define MT_DMA_CTL_TO_HOST BIT(8)
  16. #define MT_DMA_CTL_TO_HOST_A BIT(12)
  17. #define MT_DMA_CTL_DROP BIT(14)
  18. #define MT_DMA_CTL_TOKEN GENMASK(31, 16)
  19. #define MT_DMA_CTL_SDP1_H GENMASK(19, 16)
  20. #define MT_DMA_CTL_SDP0_H GENMASK(3, 0)
  21. #define MT_DMA_CTL_WO_DROP BIT(8)
  22. #define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
  23. #define MT_DMA_PPE_ENTRY GENMASK(30, 16)
  24. #define MT_DMA_INFO_DMA_FRAG BIT(9)
  25. #define MT_DMA_INFO_PPE_VLD BIT(31)
  26. #define MT_DMA_CTL_PN_CHK_FAIL BIT(13)
  27. #define MT_DMA_CTL_VER_MASK BIT(7)
  28. #define MT_DMA_RRO_EN BIT(13)
  29. #define MT_DMA_WED_IND_CMD_CNT 8
  30. #define MT_DMA_WED_IND_REASON GENMASK(15, 12)
  31. #define MT_DMA_HDR_LEN 4
  32. #define MT_RX_INFO_LEN 4
  33. #define MT_FCE_INFO_LEN 4
  34. #define MT_RX_RXWI_LEN 32
  35. struct mt76_desc {
  36. __le32 buf0;
  37. __le32 ctrl;
  38. __le32 buf1;
  39. __le32 info;
  40. } __packed __aligned(4);
  41. struct mt76_wed_rro_desc {
  42. __le32 buf0;
  43. __le32 buf1;
  44. } __packed __aligned(4);
  45. enum mt76_qsel {
  46. MT_QSEL_MGMT,
  47. MT_QSEL_HCCA,
  48. MT_QSEL_EDCA,
  49. MT_QSEL_EDCA_2,
  50. };
  51. enum mt76_mcu_evt_type {
  52. EVT_CMD_DONE,
  53. EVT_CMD_ERROR,
  54. EVT_CMD_RETRY,
  55. EVT_EVENT_PWR_RSP,
  56. EVT_EVENT_WOW_RSP,
  57. EVT_EVENT_CARRIER_DETECT_RSP,
  58. EVT_EVENT_DFS_DETECT_RSP,
  59. };
  60. enum mt76_dma_wed_ind_reason {
  61. MT_DMA_WED_IND_REASON_NORMAL,
  62. MT_DMA_WED_IND_REASON_REPEAT,
  63. MT_DMA_WED_IND_REASON_OLDPKT,
  64. };
  65. int mt76_dma_rx_poll(struct napi_struct *napi, int budget);
  66. void mt76_dma_attach(struct mt76_dev *dev);
  67. void mt76_dma_cleanup(struct mt76_dev *dev);
  68. int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q,
  69. bool allow_direct);
  70. void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q,
  71. bool reset_idx);
  72. void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q);
  73. static inline void
  74. mt76_dma_reset_tx_queue(struct mt76_dev *dev, struct mt76_queue *q)
  75. {
  76. dev->queue_ops->reset_q(dev, q);
  77. if (mtk_wed_device_active(&dev->mmio.wed))
  78. mt76_wed_dma_setup(dev, q, true);
  79. }
  80. static inline void
  81. mt76_dma_should_drop_buf(bool *drop, u32 ctrl, u32 buf1, u32 info)
  82. {
  83. if (!drop)
  84. return;
  85. *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP));
  86. if (!(ctrl & MT_DMA_CTL_VER_MASK))
  87. return;
  88. switch (FIELD_GET(MT_DMA_WED_IND_REASON, buf1)) {
  89. case MT_DMA_WED_IND_REASON_REPEAT:
  90. *drop = true;
  91. break;
  92. case MT_DMA_WED_IND_REASON_OLDPKT:
  93. *drop = !(info & MT_DMA_INFO_DMA_FRAG);
  94. break;
  95. default:
  96. *drop = !!(ctrl & MT_DMA_CTL_PN_CHK_FAIL);
  97. break;
  98. }
  99. }
  100. static inline void *mt76_priv(struct net_device *dev)
  101. {
  102. struct mt76_dev **priv;
  103. priv = netdev_priv(dev);
  104. return *priv;
  105. }
  106. #endif