rdma.c 63 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVMe over Fabrics RDMA host code.
  4. * Copyright (c) 2015-2016 HGST, a Western Digital Company.
  5. */
  6. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  7. #include <linux/module.h>
  8. #include <linux/init.h>
  9. #include <linux/slab.h>
  10. #include <rdma/mr_pool.h>
  11. #include <linux/err.h>
  12. #include <linux/string.h>
  13. #include <linux/atomic.h>
  14. #include <linux/blk-mq.h>
  15. #include <linux/blk-integrity.h>
  16. #include <linux/types.h>
  17. #include <linux/list.h>
  18. #include <linux/mutex.h>
  19. #include <linux/scatterlist.h>
  20. #include <linux/nvme.h>
  21. #include <linux/unaligned.h>
  22. #include <rdma/ib_verbs.h>
  23. #include <rdma/rdma_cm.h>
  24. #include <linux/nvme-rdma.h>
  25. #include "nvme.h"
  26. #include "fabrics.h"
  27. #define NVME_RDMA_CM_TIMEOUT_MS 3000 /* 3 second */
  28. #define NVME_RDMA_MAX_SEGMENTS 256
  29. #define NVME_RDMA_MAX_INLINE_SEGMENTS 4
  30. #define NVME_RDMA_DATA_SGL_SIZE \
  31. (sizeof(struct scatterlist) * NVME_INLINE_SG_CNT)
  32. #define NVME_RDMA_METADATA_SGL_SIZE \
  33. (sizeof(struct scatterlist) * NVME_INLINE_METADATA_SG_CNT)
  34. struct nvme_rdma_device {
  35. struct ib_device *dev;
  36. struct ib_pd *pd;
  37. struct kref ref;
  38. struct list_head entry;
  39. unsigned int num_inline_segments;
  40. };
  41. struct nvme_rdma_qe {
  42. struct ib_cqe cqe;
  43. void *data;
  44. u64 dma;
  45. };
  46. struct nvme_rdma_sgl {
  47. int nents;
  48. struct sg_table sg_table;
  49. };
  50. struct nvme_rdma_queue;
  51. struct nvme_rdma_request {
  52. struct nvme_request req;
  53. struct ib_mr *mr;
  54. struct nvme_rdma_qe sqe;
  55. union nvme_result result;
  56. __le16 status;
  57. refcount_t ref;
  58. struct ib_sge sge[1 + NVME_RDMA_MAX_INLINE_SEGMENTS];
  59. u32 num_sge;
  60. struct ib_reg_wr reg_wr;
  61. struct ib_cqe reg_cqe;
  62. struct nvme_rdma_queue *queue;
  63. struct nvme_rdma_sgl data_sgl;
  64. struct nvme_rdma_sgl *metadata_sgl;
  65. bool use_sig_mr;
  66. };
  67. enum nvme_rdma_queue_flags {
  68. NVME_RDMA_Q_ALLOCATED = 0,
  69. NVME_RDMA_Q_LIVE = 1,
  70. NVME_RDMA_Q_TR_READY = 2,
  71. };
  72. struct nvme_rdma_queue {
  73. struct nvme_rdma_qe *rsp_ring;
  74. int queue_size;
  75. size_t cmnd_capsule_len;
  76. struct nvme_rdma_ctrl *ctrl;
  77. struct nvme_rdma_device *device;
  78. struct ib_cq *ib_cq;
  79. struct ib_qp *qp;
  80. unsigned long flags;
  81. struct rdma_cm_id *cm_id;
  82. int cm_error;
  83. struct completion cm_done;
  84. bool pi_support;
  85. int cq_size;
  86. struct mutex queue_lock;
  87. };
  88. struct nvme_rdma_ctrl {
  89. /* read only in the hot path */
  90. struct nvme_rdma_queue *queues;
  91. /* other member variables */
  92. struct blk_mq_tag_set tag_set;
  93. struct work_struct err_work;
  94. struct nvme_rdma_qe async_event_sqe;
  95. struct delayed_work reconnect_work;
  96. struct list_head list;
  97. struct blk_mq_tag_set admin_tag_set;
  98. struct nvme_rdma_device *device;
  99. u32 max_fr_pages;
  100. struct sockaddr_storage addr;
  101. struct sockaddr_storage src_addr;
  102. struct nvme_ctrl ctrl;
  103. bool use_inline_data;
  104. u32 io_queues[HCTX_MAX_TYPES];
  105. };
  106. static inline struct nvme_rdma_ctrl *to_rdma_ctrl(struct nvme_ctrl *ctrl)
  107. {
  108. return container_of(ctrl, struct nvme_rdma_ctrl, ctrl);
  109. }
  110. static LIST_HEAD(device_list);
  111. static DEFINE_MUTEX(device_list_mutex);
  112. static LIST_HEAD(nvme_rdma_ctrl_list);
  113. static DEFINE_MUTEX(nvme_rdma_ctrl_mutex);
  114. /*
  115. * Disabling this option makes small I/O goes faster, but is fundamentally
  116. * unsafe. With it turned off we will have to register a global rkey that
  117. * allows read and write access to all physical memory.
  118. */
  119. static bool register_always = true;
  120. module_param(register_always, bool, 0444);
  121. MODULE_PARM_DESC(register_always,
  122. "Use memory registration even for contiguous memory regions");
  123. static int nvme_rdma_cm_handler(struct rdma_cm_id *cm_id,
  124. struct rdma_cm_event *event);
  125. static void nvme_rdma_recv_done(struct ib_cq *cq, struct ib_wc *wc);
  126. static void nvme_rdma_complete_rq(struct request *rq);
  127. static const struct blk_mq_ops nvme_rdma_mq_ops;
  128. static const struct blk_mq_ops nvme_rdma_admin_mq_ops;
  129. static inline int nvme_rdma_queue_idx(struct nvme_rdma_queue *queue)
  130. {
  131. return queue - queue->ctrl->queues;
  132. }
  133. static bool nvme_rdma_poll_queue(struct nvme_rdma_queue *queue)
  134. {
  135. return nvme_rdma_queue_idx(queue) >
  136. queue->ctrl->io_queues[HCTX_TYPE_DEFAULT] +
  137. queue->ctrl->io_queues[HCTX_TYPE_READ];
  138. }
  139. static inline size_t nvme_rdma_inline_data_size(struct nvme_rdma_queue *queue)
  140. {
  141. return queue->cmnd_capsule_len - sizeof(struct nvme_command);
  142. }
  143. static void nvme_rdma_free_qe(struct ib_device *ibdev, struct nvme_rdma_qe *qe,
  144. size_t capsule_size, enum dma_data_direction dir)
  145. {
  146. ib_dma_unmap_single(ibdev, qe->dma, capsule_size, dir);
  147. kfree(qe->data);
  148. }
  149. static int nvme_rdma_alloc_qe(struct ib_device *ibdev, struct nvme_rdma_qe *qe,
  150. size_t capsule_size, enum dma_data_direction dir)
  151. {
  152. qe->data = kzalloc(capsule_size, GFP_KERNEL);
  153. if (!qe->data)
  154. return -ENOMEM;
  155. qe->dma = ib_dma_map_single(ibdev, qe->data, capsule_size, dir);
  156. if (ib_dma_mapping_error(ibdev, qe->dma)) {
  157. kfree(qe->data);
  158. qe->data = NULL;
  159. return -ENOMEM;
  160. }
  161. return 0;
  162. }
  163. static void nvme_rdma_free_ring(struct ib_device *ibdev,
  164. struct nvme_rdma_qe *ring, size_t ib_queue_size,
  165. size_t capsule_size, enum dma_data_direction dir)
  166. {
  167. int i;
  168. for (i = 0; i < ib_queue_size; i++)
  169. nvme_rdma_free_qe(ibdev, &ring[i], capsule_size, dir);
  170. kfree(ring);
  171. }
  172. static struct nvme_rdma_qe *nvme_rdma_alloc_ring(struct ib_device *ibdev,
  173. size_t ib_queue_size, size_t capsule_size,
  174. enum dma_data_direction dir)
  175. {
  176. struct nvme_rdma_qe *ring;
  177. int i;
  178. ring = kcalloc(ib_queue_size, sizeof(struct nvme_rdma_qe), GFP_KERNEL);
  179. if (!ring)
  180. return NULL;
  181. /*
  182. * Bind the CQEs (post recv buffers) DMA mapping to the RDMA queue
  183. * lifetime. It's safe, since any chage in the underlying RDMA device
  184. * will issue error recovery and queue re-creation.
  185. */
  186. for (i = 0; i < ib_queue_size; i++) {
  187. if (nvme_rdma_alloc_qe(ibdev, &ring[i], capsule_size, dir))
  188. goto out_free_ring;
  189. }
  190. return ring;
  191. out_free_ring:
  192. nvme_rdma_free_ring(ibdev, ring, i, capsule_size, dir);
  193. return NULL;
  194. }
  195. static void nvme_rdma_qp_event(struct ib_event *event, void *context)
  196. {
  197. pr_debug("QP event %s (%d)\n",
  198. ib_event_msg(event->event), event->event);
  199. }
  200. static int nvme_rdma_wait_for_cm(struct nvme_rdma_queue *queue)
  201. {
  202. int ret;
  203. ret = wait_for_completion_interruptible(&queue->cm_done);
  204. if (ret)
  205. return ret;
  206. WARN_ON_ONCE(queue->cm_error > 0);
  207. return queue->cm_error;
  208. }
  209. static int nvme_rdma_create_qp(struct nvme_rdma_queue *queue, const int factor)
  210. {
  211. struct nvme_rdma_device *dev = queue->device;
  212. struct ib_qp_init_attr init_attr;
  213. int ret;
  214. memset(&init_attr, 0, sizeof(init_attr));
  215. init_attr.event_handler = nvme_rdma_qp_event;
  216. /* +1 for drain */
  217. init_attr.cap.max_send_wr = factor * queue->queue_size + 1;
  218. /* +1 for drain */
  219. init_attr.cap.max_recv_wr = queue->queue_size + 1;
  220. init_attr.cap.max_recv_sge = 1;
  221. init_attr.cap.max_send_sge = 1 + dev->num_inline_segments;
  222. init_attr.sq_sig_type = IB_SIGNAL_REQ_WR;
  223. init_attr.qp_type = IB_QPT_RC;
  224. init_attr.send_cq = queue->ib_cq;
  225. init_attr.recv_cq = queue->ib_cq;
  226. if (queue->pi_support)
  227. init_attr.create_flags |= IB_QP_CREATE_INTEGRITY_EN;
  228. init_attr.qp_context = queue;
  229. ret = rdma_create_qp(queue->cm_id, dev->pd, &init_attr);
  230. queue->qp = queue->cm_id->qp;
  231. return ret;
  232. }
  233. static void nvme_rdma_exit_request(struct blk_mq_tag_set *set,
  234. struct request *rq, unsigned int hctx_idx)
  235. {
  236. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  237. kfree(req->sqe.data);
  238. }
  239. static int nvme_rdma_init_request(struct blk_mq_tag_set *set,
  240. struct request *rq, unsigned int hctx_idx,
  241. unsigned int numa_node)
  242. {
  243. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(set->driver_data);
  244. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  245. int queue_idx = (set == &ctrl->tag_set) ? hctx_idx + 1 : 0;
  246. struct nvme_rdma_queue *queue = &ctrl->queues[queue_idx];
  247. nvme_req(rq)->ctrl = &ctrl->ctrl;
  248. req->sqe.data = kzalloc(sizeof(struct nvme_command), GFP_KERNEL);
  249. if (!req->sqe.data)
  250. return -ENOMEM;
  251. /* metadata nvme_rdma_sgl struct is located after command's data SGL */
  252. if (queue->pi_support)
  253. req->metadata_sgl = (void *)nvme_req(rq) +
  254. sizeof(struct nvme_rdma_request) +
  255. NVME_RDMA_DATA_SGL_SIZE;
  256. req->queue = queue;
  257. nvme_req(rq)->cmd = req->sqe.data;
  258. return 0;
  259. }
  260. static int nvme_rdma_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  261. unsigned int hctx_idx)
  262. {
  263. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(data);
  264. struct nvme_rdma_queue *queue = &ctrl->queues[hctx_idx + 1];
  265. BUG_ON(hctx_idx >= ctrl->ctrl.queue_count);
  266. hctx->driver_data = queue;
  267. return 0;
  268. }
  269. static int nvme_rdma_init_admin_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  270. unsigned int hctx_idx)
  271. {
  272. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(data);
  273. struct nvme_rdma_queue *queue = &ctrl->queues[0];
  274. BUG_ON(hctx_idx != 0);
  275. hctx->driver_data = queue;
  276. return 0;
  277. }
  278. static void nvme_rdma_free_dev(struct kref *ref)
  279. {
  280. struct nvme_rdma_device *ndev =
  281. container_of(ref, struct nvme_rdma_device, ref);
  282. mutex_lock(&device_list_mutex);
  283. list_del(&ndev->entry);
  284. mutex_unlock(&device_list_mutex);
  285. ib_dealloc_pd(ndev->pd);
  286. kfree(ndev);
  287. }
  288. static void nvme_rdma_dev_put(struct nvme_rdma_device *dev)
  289. {
  290. kref_put(&dev->ref, nvme_rdma_free_dev);
  291. }
  292. static int nvme_rdma_dev_get(struct nvme_rdma_device *dev)
  293. {
  294. return kref_get_unless_zero(&dev->ref);
  295. }
  296. static struct nvme_rdma_device *
  297. nvme_rdma_find_get_device(struct rdma_cm_id *cm_id)
  298. {
  299. struct nvme_rdma_device *ndev;
  300. mutex_lock(&device_list_mutex);
  301. list_for_each_entry(ndev, &device_list, entry) {
  302. if (ndev->dev->node_guid == cm_id->device->node_guid &&
  303. nvme_rdma_dev_get(ndev))
  304. goto out_unlock;
  305. }
  306. ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
  307. if (!ndev)
  308. goto out_err;
  309. ndev->dev = cm_id->device;
  310. kref_init(&ndev->ref);
  311. ndev->pd = ib_alloc_pd(ndev->dev,
  312. register_always ? 0 : IB_PD_UNSAFE_GLOBAL_RKEY);
  313. if (IS_ERR(ndev->pd))
  314. goto out_free_dev;
  315. if (!(ndev->dev->attrs.device_cap_flags &
  316. IB_DEVICE_MEM_MGT_EXTENSIONS)) {
  317. dev_err(&ndev->dev->dev,
  318. "Memory registrations not supported.\n");
  319. goto out_free_pd;
  320. }
  321. ndev->num_inline_segments = min(NVME_RDMA_MAX_INLINE_SEGMENTS,
  322. ndev->dev->attrs.max_send_sge - 1);
  323. list_add(&ndev->entry, &device_list);
  324. out_unlock:
  325. mutex_unlock(&device_list_mutex);
  326. return ndev;
  327. out_free_pd:
  328. ib_dealloc_pd(ndev->pd);
  329. out_free_dev:
  330. kfree(ndev);
  331. out_err:
  332. mutex_unlock(&device_list_mutex);
  333. return NULL;
  334. }
  335. static void nvme_rdma_free_cq(struct nvme_rdma_queue *queue)
  336. {
  337. if (nvme_rdma_poll_queue(queue))
  338. ib_free_cq(queue->ib_cq);
  339. else
  340. ib_cq_pool_put(queue->ib_cq, queue->cq_size);
  341. }
  342. static void nvme_rdma_destroy_queue_ib(struct nvme_rdma_queue *queue)
  343. {
  344. struct nvme_rdma_device *dev;
  345. struct ib_device *ibdev;
  346. if (!test_and_clear_bit(NVME_RDMA_Q_TR_READY, &queue->flags))
  347. return;
  348. dev = queue->device;
  349. ibdev = dev->dev;
  350. if (queue->pi_support)
  351. ib_mr_pool_destroy(queue->qp, &queue->qp->sig_mrs);
  352. ib_mr_pool_destroy(queue->qp, &queue->qp->rdma_mrs);
  353. /*
  354. * The cm_id object might have been destroyed during RDMA connection
  355. * establishment error flow to avoid getting other cma events, thus
  356. * the destruction of the QP shouldn't use rdma_cm API.
  357. */
  358. ib_destroy_qp(queue->qp);
  359. nvme_rdma_free_cq(queue);
  360. nvme_rdma_free_ring(ibdev, queue->rsp_ring, queue->queue_size,
  361. sizeof(struct nvme_completion), DMA_FROM_DEVICE);
  362. nvme_rdma_dev_put(dev);
  363. }
  364. static int nvme_rdma_get_max_fr_pages(struct ib_device *ibdev, bool pi_support)
  365. {
  366. u32 max_page_list_len;
  367. if (pi_support)
  368. max_page_list_len = ibdev->attrs.max_pi_fast_reg_page_list_len;
  369. else
  370. max_page_list_len = ibdev->attrs.max_fast_reg_page_list_len;
  371. return min_t(u32, NVME_RDMA_MAX_SEGMENTS, max_page_list_len - 1);
  372. }
  373. static int nvme_rdma_create_cq(struct ib_device *ibdev,
  374. struct nvme_rdma_queue *queue)
  375. {
  376. int ret, comp_vector, idx = nvme_rdma_queue_idx(queue);
  377. /*
  378. * Spread I/O queues completion vectors according their queue index.
  379. * Admin queues can always go on completion vector 0.
  380. */
  381. comp_vector = (idx == 0 ? idx : idx - 1) % ibdev->num_comp_vectors;
  382. /* Polling queues need direct cq polling context */
  383. if (nvme_rdma_poll_queue(queue))
  384. queue->ib_cq = ib_alloc_cq(ibdev, queue, queue->cq_size,
  385. comp_vector, IB_POLL_DIRECT);
  386. else
  387. queue->ib_cq = ib_cq_pool_get(ibdev, queue->cq_size,
  388. comp_vector, IB_POLL_SOFTIRQ);
  389. if (IS_ERR(queue->ib_cq)) {
  390. ret = PTR_ERR(queue->ib_cq);
  391. return ret;
  392. }
  393. return 0;
  394. }
  395. static int nvme_rdma_create_queue_ib(struct nvme_rdma_queue *queue)
  396. {
  397. struct ib_device *ibdev;
  398. const int send_wr_factor = 3; /* MR, SEND, INV */
  399. const int cq_factor = send_wr_factor + 1; /* + RECV */
  400. int ret, pages_per_mr;
  401. queue->device = nvme_rdma_find_get_device(queue->cm_id);
  402. if (!queue->device) {
  403. dev_err(queue->cm_id->device->dev.parent,
  404. "no client data found!\n");
  405. return -ECONNREFUSED;
  406. }
  407. ibdev = queue->device->dev;
  408. /* +1 for ib_drain_qp */
  409. queue->cq_size = cq_factor * queue->queue_size + 1;
  410. ret = nvme_rdma_create_cq(ibdev, queue);
  411. if (ret)
  412. goto out_put_dev;
  413. ret = nvme_rdma_create_qp(queue, send_wr_factor);
  414. if (ret)
  415. goto out_destroy_ib_cq;
  416. queue->rsp_ring = nvme_rdma_alloc_ring(ibdev, queue->queue_size,
  417. sizeof(struct nvme_completion), DMA_FROM_DEVICE);
  418. if (!queue->rsp_ring) {
  419. ret = -ENOMEM;
  420. goto out_destroy_qp;
  421. }
  422. /*
  423. * Currently we don't use SG_GAPS MR's so if the first entry is
  424. * misaligned we'll end up using two entries for a single data page,
  425. * so one additional entry is required.
  426. */
  427. pages_per_mr = nvme_rdma_get_max_fr_pages(ibdev, queue->pi_support) + 1;
  428. ret = ib_mr_pool_init(queue->qp, &queue->qp->rdma_mrs,
  429. queue->queue_size,
  430. IB_MR_TYPE_MEM_REG,
  431. pages_per_mr, 0);
  432. if (ret) {
  433. dev_err(queue->ctrl->ctrl.device,
  434. "failed to initialize MR pool sized %d for QID %d\n",
  435. queue->queue_size, nvme_rdma_queue_idx(queue));
  436. goto out_destroy_ring;
  437. }
  438. if (queue->pi_support) {
  439. ret = ib_mr_pool_init(queue->qp, &queue->qp->sig_mrs,
  440. queue->queue_size, IB_MR_TYPE_INTEGRITY,
  441. pages_per_mr, pages_per_mr);
  442. if (ret) {
  443. dev_err(queue->ctrl->ctrl.device,
  444. "failed to initialize PI MR pool sized %d for QID %d\n",
  445. queue->queue_size, nvme_rdma_queue_idx(queue));
  446. goto out_destroy_mr_pool;
  447. }
  448. }
  449. set_bit(NVME_RDMA_Q_TR_READY, &queue->flags);
  450. return 0;
  451. out_destroy_mr_pool:
  452. ib_mr_pool_destroy(queue->qp, &queue->qp->rdma_mrs);
  453. out_destroy_ring:
  454. nvme_rdma_free_ring(ibdev, queue->rsp_ring, queue->queue_size,
  455. sizeof(struct nvme_completion), DMA_FROM_DEVICE);
  456. out_destroy_qp:
  457. rdma_destroy_qp(queue->cm_id);
  458. out_destroy_ib_cq:
  459. nvme_rdma_free_cq(queue);
  460. out_put_dev:
  461. nvme_rdma_dev_put(queue->device);
  462. return ret;
  463. }
  464. static int nvme_rdma_alloc_queue(struct nvme_rdma_ctrl *ctrl,
  465. int idx, size_t queue_size)
  466. {
  467. struct nvme_rdma_queue *queue;
  468. struct sockaddr *src_addr = NULL;
  469. int ret;
  470. queue = &ctrl->queues[idx];
  471. mutex_init(&queue->queue_lock);
  472. queue->ctrl = ctrl;
  473. if (idx && ctrl->ctrl.max_integrity_segments)
  474. queue->pi_support = true;
  475. else
  476. queue->pi_support = false;
  477. init_completion(&queue->cm_done);
  478. if (idx > 0)
  479. queue->cmnd_capsule_len = ctrl->ctrl.ioccsz * 16;
  480. else
  481. queue->cmnd_capsule_len = sizeof(struct nvme_command);
  482. queue->queue_size = queue_size;
  483. queue->cm_id = rdma_create_id(&init_net, nvme_rdma_cm_handler, queue,
  484. RDMA_PS_TCP, IB_QPT_RC);
  485. if (IS_ERR(queue->cm_id)) {
  486. dev_info(ctrl->ctrl.device,
  487. "failed to create CM ID: %ld\n", PTR_ERR(queue->cm_id));
  488. ret = PTR_ERR(queue->cm_id);
  489. goto out_destroy_mutex;
  490. }
  491. if (ctrl->ctrl.opts->mask & NVMF_OPT_HOST_TRADDR)
  492. src_addr = (struct sockaddr *)&ctrl->src_addr;
  493. queue->cm_error = -ETIMEDOUT;
  494. ret = rdma_resolve_addr(queue->cm_id, src_addr,
  495. (struct sockaddr *)&ctrl->addr,
  496. NVME_RDMA_CM_TIMEOUT_MS);
  497. if (ret) {
  498. dev_info(ctrl->ctrl.device,
  499. "rdma_resolve_addr failed (%d).\n", ret);
  500. goto out_destroy_cm_id;
  501. }
  502. ret = nvme_rdma_wait_for_cm(queue);
  503. if (ret) {
  504. dev_info(ctrl->ctrl.device,
  505. "rdma connection establishment failed (%d)\n", ret);
  506. goto out_destroy_cm_id;
  507. }
  508. set_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags);
  509. return 0;
  510. out_destroy_cm_id:
  511. rdma_destroy_id(queue->cm_id);
  512. nvme_rdma_destroy_queue_ib(queue);
  513. out_destroy_mutex:
  514. mutex_destroy(&queue->queue_lock);
  515. return ret;
  516. }
  517. static void __nvme_rdma_stop_queue(struct nvme_rdma_queue *queue)
  518. {
  519. rdma_disconnect(queue->cm_id);
  520. ib_drain_qp(queue->qp);
  521. }
  522. static void nvme_rdma_stop_queue(struct nvme_rdma_queue *queue)
  523. {
  524. if (!test_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
  525. return;
  526. mutex_lock(&queue->queue_lock);
  527. if (test_and_clear_bit(NVME_RDMA_Q_LIVE, &queue->flags))
  528. __nvme_rdma_stop_queue(queue);
  529. mutex_unlock(&queue->queue_lock);
  530. }
  531. static void nvme_rdma_free_queue(struct nvme_rdma_queue *queue)
  532. {
  533. if (!test_and_clear_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
  534. return;
  535. rdma_destroy_id(queue->cm_id);
  536. nvme_rdma_destroy_queue_ib(queue);
  537. mutex_destroy(&queue->queue_lock);
  538. }
  539. static void nvme_rdma_free_io_queues(struct nvme_rdma_ctrl *ctrl)
  540. {
  541. int i;
  542. for (i = 1; i < ctrl->ctrl.queue_count; i++)
  543. nvme_rdma_free_queue(&ctrl->queues[i]);
  544. }
  545. static void nvme_rdma_stop_io_queues(struct nvme_rdma_ctrl *ctrl)
  546. {
  547. int i;
  548. for (i = 1; i < ctrl->ctrl.queue_count; i++)
  549. nvme_rdma_stop_queue(&ctrl->queues[i]);
  550. }
  551. static int nvme_rdma_start_queue(struct nvme_rdma_ctrl *ctrl, int idx)
  552. {
  553. struct nvme_rdma_queue *queue = &ctrl->queues[idx];
  554. int ret;
  555. if (idx)
  556. ret = nvmf_connect_io_queue(&ctrl->ctrl, idx);
  557. else
  558. ret = nvmf_connect_admin_queue(&ctrl->ctrl);
  559. if (!ret) {
  560. set_bit(NVME_RDMA_Q_LIVE, &queue->flags);
  561. } else {
  562. if (test_bit(NVME_RDMA_Q_ALLOCATED, &queue->flags))
  563. __nvme_rdma_stop_queue(queue);
  564. dev_info(ctrl->ctrl.device,
  565. "failed to connect queue: %d ret=%d\n", idx, ret);
  566. }
  567. return ret;
  568. }
  569. static int nvme_rdma_start_io_queues(struct nvme_rdma_ctrl *ctrl,
  570. int first, int last)
  571. {
  572. int i, ret = 0;
  573. for (i = first; i < last; i++) {
  574. ret = nvme_rdma_start_queue(ctrl, i);
  575. if (ret)
  576. goto out_stop_queues;
  577. }
  578. return 0;
  579. out_stop_queues:
  580. for (i--; i >= first; i--)
  581. nvme_rdma_stop_queue(&ctrl->queues[i]);
  582. return ret;
  583. }
  584. static int nvme_rdma_alloc_io_queues(struct nvme_rdma_ctrl *ctrl)
  585. {
  586. struct nvmf_ctrl_options *opts = ctrl->ctrl.opts;
  587. unsigned int nr_io_queues;
  588. int i, ret;
  589. nr_io_queues = nvmf_nr_io_queues(opts);
  590. ret = nvme_set_queue_count(&ctrl->ctrl, &nr_io_queues);
  591. if (ret)
  592. return ret;
  593. if (nr_io_queues == 0) {
  594. dev_err(ctrl->ctrl.device,
  595. "unable to set any I/O queues\n");
  596. return -ENOMEM;
  597. }
  598. ctrl->ctrl.queue_count = nr_io_queues + 1;
  599. dev_info(ctrl->ctrl.device,
  600. "creating %d I/O queues.\n", nr_io_queues);
  601. nvmf_set_io_queues(opts, nr_io_queues, ctrl->io_queues);
  602. for (i = 1; i < ctrl->ctrl.queue_count; i++) {
  603. ret = nvme_rdma_alloc_queue(ctrl, i,
  604. ctrl->ctrl.sqsize + 1);
  605. if (ret)
  606. goto out_free_queues;
  607. }
  608. return 0;
  609. out_free_queues:
  610. for (i--; i >= 1; i--)
  611. nvme_rdma_free_queue(&ctrl->queues[i]);
  612. return ret;
  613. }
  614. static int nvme_rdma_alloc_tag_set(struct nvme_ctrl *ctrl)
  615. {
  616. unsigned int cmd_size = sizeof(struct nvme_rdma_request) +
  617. NVME_RDMA_DATA_SGL_SIZE;
  618. if (ctrl->max_integrity_segments)
  619. cmd_size += sizeof(struct nvme_rdma_sgl) +
  620. NVME_RDMA_METADATA_SGL_SIZE;
  621. return nvme_alloc_io_tag_set(ctrl, &to_rdma_ctrl(ctrl)->tag_set,
  622. &nvme_rdma_mq_ops,
  623. ctrl->opts->nr_poll_queues ? HCTX_MAX_TYPES : 2,
  624. cmd_size);
  625. }
  626. static void nvme_rdma_destroy_admin_queue(struct nvme_rdma_ctrl *ctrl)
  627. {
  628. if (ctrl->async_event_sqe.data) {
  629. cancel_work_sync(&ctrl->ctrl.async_event_work);
  630. nvme_rdma_free_qe(ctrl->device->dev, &ctrl->async_event_sqe,
  631. sizeof(struct nvme_command), DMA_TO_DEVICE);
  632. ctrl->async_event_sqe.data = NULL;
  633. }
  634. nvme_rdma_free_queue(&ctrl->queues[0]);
  635. }
  636. static int nvme_rdma_configure_admin_queue(struct nvme_rdma_ctrl *ctrl,
  637. bool new)
  638. {
  639. bool pi_capable = false;
  640. int error;
  641. error = nvme_rdma_alloc_queue(ctrl, 0, NVME_AQ_DEPTH);
  642. if (error)
  643. return error;
  644. ctrl->device = ctrl->queues[0].device;
  645. ctrl->ctrl.numa_node = ibdev_to_node(ctrl->device->dev);
  646. /* T10-PI support */
  647. if (ctrl->device->dev->attrs.kernel_cap_flags &
  648. IBK_INTEGRITY_HANDOVER)
  649. pi_capable = true;
  650. ctrl->max_fr_pages = nvme_rdma_get_max_fr_pages(ctrl->device->dev,
  651. pi_capable);
  652. /*
  653. * Bind the async event SQE DMA mapping to the admin queue lifetime.
  654. * It's safe, since any chage in the underlying RDMA device will issue
  655. * error recovery and queue re-creation.
  656. */
  657. error = nvme_rdma_alloc_qe(ctrl->device->dev, &ctrl->async_event_sqe,
  658. sizeof(struct nvme_command), DMA_TO_DEVICE);
  659. if (error)
  660. goto out_free_queue;
  661. if (new) {
  662. error = nvme_alloc_admin_tag_set(&ctrl->ctrl,
  663. &ctrl->admin_tag_set, &nvme_rdma_admin_mq_ops,
  664. sizeof(struct nvme_rdma_request) +
  665. NVME_RDMA_DATA_SGL_SIZE);
  666. if (error)
  667. goto out_free_async_qe;
  668. }
  669. error = nvme_rdma_start_queue(ctrl, 0);
  670. if (error)
  671. goto out_remove_admin_tag_set;
  672. error = nvme_enable_ctrl(&ctrl->ctrl);
  673. if (error)
  674. goto out_stop_queue;
  675. ctrl->ctrl.max_segments = ctrl->max_fr_pages;
  676. ctrl->ctrl.max_hw_sectors = ctrl->max_fr_pages << (ilog2(SZ_4K) - 9);
  677. if (pi_capable)
  678. ctrl->ctrl.max_integrity_segments = ctrl->max_fr_pages;
  679. else
  680. ctrl->ctrl.max_integrity_segments = 0;
  681. nvme_unquiesce_admin_queue(&ctrl->ctrl);
  682. error = nvme_init_ctrl_finish(&ctrl->ctrl, false);
  683. if (error)
  684. goto out_quiesce_queue;
  685. return 0;
  686. out_quiesce_queue:
  687. nvme_quiesce_admin_queue(&ctrl->ctrl);
  688. blk_sync_queue(ctrl->ctrl.admin_q);
  689. out_stop_queue:
  690. nvme_rdma_stop_queue(&ctrl->queues[0]);
  691. nvme_cancel_admin_tagset(&ctrl->ctrl);
  692. out_remove_admin_tag_set:
  693. if (new)
  694. nvme_remove_admin_tag_set(&ctrl->ctrl);
  695. out_free_async_qe:
  696. if (ctrl->async_event_sqe.data) {
  697. nvme_rdma_free_qe(ctrl->device->dev, &ctrl->async_event_sqe,
  698. sizeof(struct nvme_command), DMA_TO_DEVICE);
  699. ctrl->async_event_sqe.data = NULL;
  700. }
  701. out_free_queue:
  702. nvme_rdma_free_queue(&ctrl->queues[0]);
  703. return error;
  704. }
  705. static int nvme_rdma_configure_io_queues(struct nvme_rdma_ctrl *ctrl, bool new)
  706. {
  707. int ret, nr_queues;
  708. ret = nvme_rdma_alloc_io_queues(ctrl);
  709. if (ret)
  710. return ret;
  711. if (new) {
  712. ret = nvme_rdma_alloc_tag_set(&ctrl->ctrl);
  713. if (ret)
  714. goto out_free_io_queues;
  715. }
  716. /*
  717. * Only start IO queues for which we have allocated the tagset
  718. * and limitted it to the available queues. On reconnects, the
  719. * queue number might have changed.
  720. */
  721. nr_queues = min(ctrl->tag_set.nr_hw_queues + 1, ctrl->ctrl.queue_count);
  722. ret = nvme_rdma_start_io_queues(ctrl, 1, nr_queues);
  723. if (ret)
  724. goto out_cleanup_tagset;
  725. if (!new) {
  726. nvme_start_freeze(&ctrl->ctrl);
  727. nvme_unquiesce_io_queues(&ctrl->ctrl);
  728. if (!nvme_wait_freeze_timeout(&ctrl->ctrl, NVME_IO_TIMEOUT)) {
  729. /*
  730. * If we timed out waiting for freeze we are likely to
  731. * be stuck. Fail the controller initialization just
  732. * to be safe.
  733. */
  734. ret = -ENODEV;
  735. nvme_unfreeze(&ctrl->ctrl);
  736. goto out_wait_freeze_timed_out;
  737. }
  738. blk_mq_update_nr_hw_queues(ctrl->ctrl.tagset,
  739. ctrl->ctrl.queue_count - 1);
  740. nvme_unfreeze(&ctrl->ctrl);
  741. }
  742. /*
  743. * If the number of queues has increased (reconnect case)
  744. * start all new queues now.
  745. */
  746. ret = nvme_rdma_start_io_queues(ctrl, nr_queues,
  747. ctrl->tag_set.nr_hw_queues + 1);
  748. if (ret)
  749. goto out_wait_freeze_timed_out;
  750. return 0;
  751. out_wait_freeze_timed_out:
  752. nvme_quiesce_io_queues(&ctrl->ctrl);
  753. nvme_sync_io_queues(&ctrl->ctrl);
  754. nvme_rdma_stop_io_queues(ctrl);
  755. out_cleanup_tagset:
  756. nvme_cancel_tagset(&ctrl->ctrl);
  757. if (new)
  758. nvme_remove_io_tag_set(&ctrl->ctrl);
  759. out_free_io_queues:
  760. nvme_rdma_free_io_queues(ctrl);
  761. return ret;
  762. }
  763. static void nvme_rdma_teardown_admin_queue(struct nvme_rdma_ctrl *ctrl,
  764. bool remove)
  765. {
  766. nvme_quiesce_admin_queue(&ctrl->ctrl);
  767. blk_sync_queue(ctrl->ctrl.admin_q);
  768. nvme_rdma_stop_queue(&ctrl->queues[0]);
  769. nvme_cancel_admin_tagset(&ctrl->ctrl);
  770. if (remove) {
  771. nvme_unquiesce_admin_queue(&ctrl->ctrl);
  772. nvme_remove_admin_tag_set(&ctrl->ctrl);
  773. }
  774. nvme_rdma_destroy_admin_queue(ctrl);
  775. }
  776. static void nvme_rdma_teardown_io_queues(struct nvme_rdma_ctrl *ctrl,
  777. bool remove)
  778. {
  779. if (ctrl->ctrl.queue_count > 1) {
  780. nvme_quiesce_io_queues(&ctrl->ctrl);
  781. nvme_sync_io_queues(&ctrl->ctrl);
  782. nvme_rdma_stop_io_queues(ctrl);
  783. nvme_cancel_tagset(&ctrl->ctrl);
  784. if (remove) {
  785. nvme_unquiesce_io_queues(&ctrl->ctrl);
  786. nvme_remove_io_tag_set(&ctrl->ctrl);
  787. }
  788. nvme_rdma_free_io_queues(ctrl);
  789. }
  790. }
  791. static void nvme_rdma_stop_ctrl(struct nvme_ctrl *nctrl)
  792. {
  793. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
  794. flush_work(&ctrl->err_work);
  795. cancel_delayed_work_sync(&ctrl->reconnect_work);
  796. }
  797. static void nvme_rdma_free_ctrl(struct nvme_ctrl *nctrl)
  798. {
  799. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(nctrl);
  800. if (list_empty(&ctrl->list))
  801. goto free_ctrl;
  802. mutex_lock(&nvme_rdma_ctrl_mutex);
  803. list_del(&ctrl->list);
  804. mutex_unlock(&nvme_rdma_ctrl_mutex);
  805. nvmf_free_options(nctrl->opts);
  806. free_ctrl:
  807. kfree(ctrl->queues);
  808. kfree(ctrl);
  809. }
  810. static void nvme_rdma_reconnect_or_remove(struct nvme_rdma_ctrl *ctrl,
  811. int status)
  812. {
  813. enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
  814. /* If we are resetting/deleting then do nothing */
  815. if (state != NVME_CTRL_CONNECTING) {
  816. WARN_ON_ONCE(state == NVME_CTRL_NEW || state == NVME_CTRL_LIVE);
  817. return;
  818. }
  819. if (nvmf_should_reconnect(&ctrl->ctrl, status)) {
  820. dev_info(ctrl->ctrl.device, "Reconnecting in %d seconds...\n",
  821. ctrl->ctrl.opts->reconnect_delay);
  822. queue_delayed_work(nvme_wq, &ctrl->reconnect_work,
  823. ctrl->ctrl.opts->reconnect_delay * HZ);
  824. } else {
  825. nvme_delete_ctrl(&ctrl->ctrl);
  826. }
  827. }
  828. static int nvme_rdma_setup_ctrl(struct nvme_rdma_ctrl *ctrl, bool new)
  829. {
  830. int ret;
  831. bool changed;
  832. u16 max_queue_size;
  833. ret = nvme_rdma_configure_admin_queue(ctrl, new);
  834. if (ret)
  835. return ret;
  836. if (ctrl->ctrl.icdoff) {
  837. ret = -EOPNOTSUPP;
  838. dev_err(ctrl->ctrl.device, "icdoff is not supported!\n");
  839. goto destroy_admin;
  840. }
  841. if (!(ctrl->ctrl.sgls & (1 << 2))) {
  842. ret = -EOPNOTSUPP;
  843. dev_err(ctrl->ctrl.device,
  844. "Mandatory keyed sgls are not supported!\n");
  845. goto destroy_admin;
  846. }
  847. if (ctrl->ctrl.opts->queue_size > ctrl->ctrl.sqsize + 1) {
  848. dev_warn(ctrl->ctrl.device,
  849. "queue_size %zu > ctrl sqsize %u, clamping down\n",
  850. ctrl->ctrl.opts->queue_size, ctrl->ctrl.sqsize + 1);
  851. }
  852. if (ctrl->ctrl.max_integrity_segments)
  853. max_queue_size = NVME_RDMA_MAX_METADATA_QUEUE_SIZE;
  854. else
  855. max_queue_size = NVME_RDMA_MAX_QUEUE_SIZE;
  856. if (ctrl->ctrl.sqsize + 1 > max_queue_size) {
  857. dev_warn(ctrl->ctrl.device,
  858. "ctrl sqsize %u > max queue size %u, clamping down\n",
  859. ctrl->ctrl.sqsize + 1, max_queue_size);
  860. ctrl->ctrl.sqsize = max_queue_size - 1;
  861. }
  862. if (ctrl->ctrl.sqsize + 1 > ctrl->ctrl.maxcmd) {
  863. dev_warn(ctrl->ctrl.device,
  864. "sqsize %u > ctrl maxcmd %u, clamping down\n",
  865. ctrl->ctrl.sqsize + 1, ctrl->ctrl.maxcmd);
  866. ctrl->ctrl.sqsize = ctrl->ctrl.maxcmd - 1;
  867. }
  868. if (ctrl->ctrl.sgls & (1 << 20))
  869. ctrl->use_inline_data = true;
  870. if (ctrl->ctrl.queue_count > 1) {
  871. ret = nvme_rdma_configure_io_queues(ctrl, new);
  872. if (ret)
  873. goto destroy_admin;
  874. }
  875. changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_LIVE);
  876. if (!changed) {
  877. /*
  878. * state change failure is ok if we started ctrl delete,
  879. * unless we're during creation of a new controller to
  880. * avoid races with teardown flow.
  881. */
  882. enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
  883. WARN_ON_ONCE(state != NVME_CTRL_DELETING &&
  884. state != NVME_CTRL_DELETING_NOIO);
  885. WARN_ON_ONCE(new);
  886. ret = -EINVAL;
  887. goto destroy_io;
  888. }
  889. nvme_start_ctrl(&ctrl->ctrl);
  890. return 0;
  891. destroy_io:
  892. if (ctrl->ctrl.queue_count > 1) {
  893. nvme_quiesce_io_queues(&ctrl->ctrl);
  894. nvme_sync_io_queues(&ctrl->ctrl);
  895. nvme_rdma_stop_io_queues(ctrl);
  896. nvme_cancel_tagset(&ctrl->ctrl);
  897. if (new)
  898. nvme_remove_io_tag_set(&ctrl->ctrl);
  899. nvme_rdma_free_io_queues(ctrl);
  900. }
  901. destroy_admin:
  902. nvme_stop_keep_alive(&ctrl->ctrl);
  903. nvme_rdma_teardown_admin_queue(ctrl, new);
  904. return ret;
  905. }
  906. static void nvme_rdma_reconnect_ctrl_work(struct work_struct *work)
  907. {
  908. struct nvme_rdma_ctrl *ctrl = container_of(to_delayed_work(work),
  909. struct nvme_rdma_ctrl, reconnect_work);
  910. int ret;
  911. ++ctrl->ctrl.nr_reconnects;
  912. ret = nvme_rdma_setup_ctrl(ctrl, false);
  913. if (ret)
  914. goto requeue;
  915. dev_info(ctrl->ctrl.device, "Successfully reconnected (%d attempts)\n",
  916. ctrl->ctrl.nr_reconnects);
  917. ctrl->ctrl.nr_reconnects = 0;
  918. return;
  919. requeue:
  920. dev_info(ctrl->ctrl.device, "Failed reconnect attempt %d/%d\n",
  921. ctrl->ctrl.nr_reconnects, ctrl->ctrl.opts->max_reconnects);
  922. nvme_rdma_reconnect_or_remove(ctrl, ret);
  923. }
  924. static void nvme_rdma_error_recovery_work(struct work_struct *work)
  925. {
  926. struct nvme_rdma_ctrl *ctrl = container_of(work,
  927. struct nvme_rdma_ctrl, err_work);
  928. nvme_stop_keep_alive(&ctrl->ctrl);
  929. flush_work(&ctrl->ctrl.async_event_work);
  930. nvme_rdma_teardown_io_queues(ctrl, false);
  931. nvme_unquiesce_io_queues(&ctrl->ctrl);
  932. nvme_rdma_teardown_admin_queue(ctrl, false);
  933. nvme_unquiesce_admin_queue(&ctrl->ctrl);
  934. nvme_auth_stop(&ctrl->ctrl);
  935. if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
  936. /* state change failure is ok if we started ctrl delete */
  937. enum nvme_ctrl_state state = nvme_ctrl_state(&ctrl->ctrl);
  938. WARN_ON_ONCE(state != NVME_CTRL_DELETING &&
  939. state != NVME_CTRL_DELETING_NOIO);
  940. return;
  941. }
  942. nvme_rdma_reconnect_or_remove(ctrl, 0);
  943. }
  944. static void nvme_rdma_error_recovery(struct nvme_rdma_ctrl *ctrl)
  945. {
  946. if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_RESETTING))
  947. return;
  948. dev_warn(ctrl->ctrl.device, "starting error recovery\n");
  949. queue_work(nvme_reset_wq, &ctrl->err_work);
  950. }
  951. static void nvme_rdma_end_request(struct nvme_rdma_request *req)
  952. {
  953. struct request *rq = blk_mq_rq_from_pdu(req);
  954. if (!refcount_dec_and_test(&req->ref))
  955. return;
  956. if (!nvme_try_complete_req(rq, req->status, req->result))
  957. nvme_rdma_complete_rq(rq);
  958. }
  959. static void nvme_rdma_wr_error(struct ib_cq *cq, struct ib_wc *wc,
  960. const char *op)
  961. {
  962. struct nvme_rdma_queue *queue = wc->qp->qp_context;
  963. struct nvme_rdma_ctrl *ctrl = queue->ctrl;
  964. if (nvme_ctrl_state(&ctrl->ctrl) == NVME_CTRL_LIVE)
  965. dev_info(ctrl->ctrl.device,
  966. "%s for CQE 0x%p failed with status %s (%d)\n",
  967. op, wc->wr_cqe,
  968. ib_wc_status_msg(wc->status), wc->status);
  969. nvme_rdma_error_recovery(ctrl);
  970. }
  971. static void nvme_rdma_memreg_done(struct ib_cq *cq, struct ib_wc *wc)
  972. {
  973. if (unlikely(wc->status != IB_WC_SUCCESS))
  974. nvme_rdma_wr_error(cq, wc, "MEMREG");
  975. }
  976. static void nvme_rdma_inv_rkey_done(struct ib_cq *cq, struct ib_wc *wc)
  977. {
  978. struct nvme_rdma_request *req =
  979. container_of(wc->wr_cqe, struct nvme_rdma_request, reg_cqe);
  980. if (unlikely(wc->status != IB_WC_SUCCESS))
  981. nvme_rdma_wr_error(cq, wc, "LOCAL_INV");
  982. else
  983. nvme_rdma_end_request(req);
  984. }
  985. static int nvme_rdma_inv_rkey(struct nvme_rdma_queue *queue,
  986. struct nvme_rdma_request *req)
  987. {
  988. struct ib_send_wr wr = {
  989. .opcode = IB_WR_LOCAL_INV,
  990. .next = NULL,
  991. .num_sge = 0,
  992. .send_flags = IB_SEND_SIGNALED,
  993. .ex.invalidate_rkey = req->mr->rkey,
  994. };
  995. req->reg_cqe.done = nvme_rdma_inv_rkey_done;
  996. wr.wr_cqe = &req->reg_cqe;
  997. return ib_post_send(queue->qp, &wr, NULL);
  998. }
  999. static void nvme_rdma_dma_unmap_req(struct ib_device *ibdev, struct request *rq)
  1000. {
  1001. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1002. if (blk_integrity_rq(rq)) {
  1003. ib_dma_unmap_sg(ibdev, req->metadata_sgl->sg_table.sgl,
  1004. req->metadata_sgl->nents, rq_dma_dir(rq));
  1005. sg_free_table_chained(&req->metadata_sgl->sg_table,
  1006. NVME_INLINE_METADATA_SG_CNT);
  1007. }
  1008. ib_dma_unmap_sg(ibdev, req->data_sgl.sg_table.sgl, req->data_sgl.nents,
  1009. rq_dma_dir(rq));
  1010. sg_free_table_chained(&req->data_sgl.sg_table, NVME_INLINE_SG_CNT);
  1011. }
  1012. static void nvme_rdma_unmap_data(struct nvme_rdma_queue *queue,
  1013. struct request *rq)
  1014. {
  1015. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1016. struct nvme_rdma_device *dev = queue->device;
  1017. struct ib_device *ibdev = dev->dev;
  1018. struct list_head *pool = &queue->qp->rdma_mrs;
  1019. if (!blk_rq_nr_phys_segments(rq))
  1020. return;
  1021. if (req->use_sig_mr)
  1022. pool = &queue->qp->sig_mrs;
  1023. if (req->mr) {
  1024. ib_mr_pool_put(queue->qp, pool, req->mr);
  1025. req->mr = NULL;
  1026. }
  1027. nvme_rdma_dma_unmap_req(ibdev, rq);
  1028. }
  1029. static int nvme_rdma_set_sg_null(struct nvme_command *c)
  1030. {
  1031. struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
  1032. sg->addr = 0;
  1033. put_unaligned_le24(0, sg->length);
  1034. put_unaligned_le32(0, sg->key);
  1035. sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
  1036. return 0;
  1037. }
  1038. static int nvme_rdma_map_sg_inline(struct nvme_rdma_queue *queue,
  1039. struct nvme_rdma_request *req, struct nvme_command *c,
  1040. int count)
  1041. {
  1042. struct nvme_sgl_desc *sg = &c->common.dptr.sgl;
  1043. struct ib_sge *sge = &req->sge[1];
  1044. struct scatterlist *sgl;
  1045. u32 len = 0;
  1046. int i;
  1047. for_each_sg(req->data_sgl.sg_table.sgl, sgl, count, i) {
  1048. sge->addr = sg_dma_address(sgl);
  1049. sge->length = sg_dma_len(sgl);
  1050. sge->lkey = queue->device->pd->local_dma_lkey;
  1051. len += sge->length;
  1052. sge++;
  1053. }
  1054. sg->addr = cpu_to_le64(queue->ctrl->ctrl.icdoff);
  1055. sg->length = cpu_to_le32(len);
  1056. sg->type = (NVME_SGL_FMT_DATA_DESC << 4) | NVME_SGL_FMT_OFFSET;
  1057. req->num_sge += count;
  1058. return 0;
  1059. }
  1060. static int nvme_rdma_map_sg_single(struct nvme_rdma_queue *queue,
  1061. struct nvme_rdma_request *req, struct nvme_command *c)
  1062. {
  1063. struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
  1064. sg->addr = cpu_to_le64(sg_dma_address(req->data_sgl.sg_table.sgl));
  1065. put_unaligned_le24(sg_dma_len(req->data_sgl.sg_table.sgl), sg->length);
  1066. put_unaligned_le32(queue->device->pd->unsafe_global_rkey, sg->key);
  1067. sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
  1068. return 0;
  1069. }
  1070. static int nvme_rdma_map_sg_fr(struct nvme_rdma_queue *queue,
  1071. struct nvme_rdma_request *req, struct nvme_command *c,
  1072. int count)
  1073. {
  1074. struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
  1075. int nr;
  1076. req->mr = ib_mr_pool_get(queue->qp, &queue->qp->rdma_mrs);
  1077. if (WARN_ON_ONCE(!req->mr))
  1078. return -EAGAIN;
  1079. /*
  1080. * Align the MR to a 4K page size to match the ctrl page size and
  1081. * the block virtual boundary.
  1082. */
  1083. nr = ib_map_mr_sg(req->mr, req->data_sgl.sg_table.sgl, count, NULL,
  1084. SZ_4K);
  1085. if (unlikely(nr < count)) {
  1086. ib_mr_pool_put(queue->qp, &queue->qp->rdma_mrs, req->mr);
  1087. req->mr = NULL;
  1088. if (nr < 0)
  1089. return nr;
  1090. return -EINVAL;
  1091. }
  1092. ib_update_fast_reg_key(req->mr, ib_inc_rkey(req->mr->rkey));
  1093. req->reg_cqe.done = nvme_rdma_memreg_done;
  1094. memset(&req->reg_wr, 0, sizeof(req->reg_wr));
  1095. req->reg_wr.wr.opcode = IB_WR_REG_MR;
  1096. req->reg_wr.wr.wr_cqe = &req->reg_cqe;
  1097. req->reg_wr.wr.num_sge = 0;
  1098. req->reg_wr.mr = req->mr;
  1099. req->reg_wr.key = req->mr->rkey;
  1100. req->reg_wr.access = IB_ACCESS_LOCAL_WRITE |
  1101. IB_ACCESS_REMOTE_READ |
  1102. IB_ACCESS_REMOTE_WRITE;
  1103. sg->addr = cpu_to_le64(req->mr->iova);
  1104. put_unaligned_le24(req->mr->length, sg->length);
  1105. put_unaligned_le32(req->mr->rkey, sg->key);
  1106. sg->type = (NVME_KEY_SGL_FMT_DATA_DESC << 4) |
  1107. NVME_SGL_FMT_INVALIDATE;
  1108. return 0;
  1109. }
  1110. static void nvme_rdma_set_sig_domain(struct blk_integrity *bi,
  1111. struct nvme_command *cmd, struct ib_sig_domain *domain,
  1112. u16 control, u8 pi_type)
  1113. {
  1114. domain->sig_type = IB_SIG_TYPE_T10_DIF;
  1115. domain->sig.dif.bg_type = IB_T10DIF_CRC;
  1116. domain->sig.dif.pi_interval = 1 << bi->interval_exp;
  1117. domain->sig.dif.ref_tag = le32_to_cpu(cmd->rw.reftag);
  1118. if (control & NVME_RW_PRINFO_PRCHK_REF)
  1119. domain->sig.dif.ref_remap = true;
  1120. domain->sig.dif.app_tag = le16_to_cpu(cmd->rw.lbat);
  1121. domain->sig.dif.apptag_check_mask = le16_to_cpu(cmd->rw.lbatm);
  1122. domain->sig.dif.app_escape = true;
  1123. if (pi_type == NVME_NS_DPS_PI_TYPE3)
  1124. domain->sig.dif.ref_escape = true;
  1125. }
  1126. static void nvme_rdma_set_sig_attrs(struct blk_integrity *bi,
  1127. struct nvme_command *cmd, struct ib_sig_attrs *sig_attrs,
  1128. u8 pi_type)
  1129. {
  1130. u16 control = le16_to_cpu(cmd->rw.control);
  1131. memset(sig_attrs, 0, sizeof(*sig_attrs));
  1132. if (control & NVME_RW_PRINFO_PRACT) {
  1133. /* for WRITE_INSERT/READ_STRIP no memory domain */
  1134. sig_attrs->mem.sig_type = IB_SIG_TYPE_NONE;
  1135. nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->wire, control,
  1136. pi_type);
  1137. /* Clear the PRACT bit since HCA will generate/verify the PI */
  1138. control &= ~NVME_RW_PRINFO_PRACT;
  1139. cmd->rw.control = cpu_to_le16(control);
  1140. } else {
  1141. /* for WRITE_PASS/READ_PASS both wire/memory domains exist */
  1142. nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->wire, control,
  1143. pi_type);
  1144. nvme_rdma_set_sig_domain(bi, cmd, &sig_attrs->mem, control,
  1145. pi_type);
  1146. }
  1147. }
  1148. static void nvme_rdma_set_prot_checks(struct nvme_command *cmd, u8 *mask)
  1149. {
  1150. *mask = 0;
  1151. if (le16_to_cpu(cmd->rw.control) & NVME_RW_PRINFO_PRCHK_REF)
  1152. *mask |= IB_SIG_CHECK_REFTAG;
  1153. if (le16_to_cpu(cmd->rw.control) & NVME_RW_PRINFO_PRCHK_GUARD)
  1154. *mask |= IB_SIG_CHECK_GUARD;
  1155. }
  1156. static void nvme_rdma_sig_done(struct ib_cq *cq, struct ib_wc *wc)
  1157. {
  1158. if (unlikely(wc->status != IB_WC_SUCCESS))
  1159. nvme_rdma_wr_error(cq, wc, "SIG");
  1160. }
  1161. static int nvme_rdma_map_sg_pi(struct nvme_rdma_queue *queue,
  1162. struct nvme_rdma_request *req, struct nvme_command *c,
  1163. int count, int pi_count)
  1164. {
  1165. struct nvme_rdma_sgl *sgl = &req->data_sgl;
  1166. struct ib_reg_wr *wr = &req->reg_wr;
  1167. struct request *rq = blk_mq_rq_from_pdu(req);
  1168. struct nvme_ns *ns = rq->q->queuedata;
  1169. struct bio *bio = rq->bio;
  1170. struct nvme_keyed_sgl_desc *sg = &c->common.dptr.ksgl;
  1171. struct blk_integrity *bi = blk_get_integrity(bio->bi_bdev->bd_disk);
  1172. u32 xfer_len;
  1173. int nr;
  1174. req->mr = ib_mr_pool_get(queue->qp, &queue->qp->sig_mrs);
  1175. if (WARN_ON_ONCE(!req->mr))
  1176. return -EAGAIN;
  1177. nr = ib_map_mr_sg_pi(req->mr, sgl->sg_table.sgl, count, NULL,
  1178. req->metadata_sgl->sg_table.sgl, pi_count, NULL,
  1179. SZ_4K);
  1180. if (unlikely(nr))
  1181. goto mr_put;
  1182. nvme_rdma_set_sig_attrs(bi, c, req->mr->sig_attrs, ns->head->pi_type);
  1183. nvme_rdma_set_prot_checks(c, &req->mr->sig_attrs->check_mask);
  1184. ib_update_fast_reg_key(req->mr, ib_inc_rkey(req->mr->rkey));
  1185. req->reg_cqe.done = nvme_rdma_sig_done;
  1186. memset(wr, 0, sizeof(*wr));
  1187. wr->wr.opcode = IB_WR_REG_MR_INTEGRITY;
  1188. wr->wr.wr_cqe = &req->reg_cqe;
  1189. wr->wr.num_sge = 0;
  1190. wr->wr.send_flags = 0;
  1191. wr->mr = req->mr;
  1192. wr->key = req->mr->rkey;
  1193. wr->access = IB_ACCESS_LOCAL_WRITE |
  1194. IB_ACCESS_REMOTE_READ |
  1195. IB_ACCESS_REMOTE_WRITE;
  1196. sg->addr = cpu_to_le64(req->mr->iova);
  1197. xfer_len = req->mr->length;
  1198. /* Check if PI is added by the HW */
  1199. if (!pi_count)
  1200. xfer_len += (xfer_len >> bi->interval_exp) * ns->head->pi_size;
  1201. put_unaligned_le24(xfer_len, sg->length);
  1202. put_unaligned_le32(req->mr->rkey, sg->key);
  1203. sg->type = NVME_KEY_SGL_FMT_DATA_DESC << 4;
  1204. return 0;
  1205. mr_put:
  1206. ib_mr_pool_put(queue->qp, &queue->qp->sig_mrs, req->mr);
  1207. req->mr = NULL;
  1208. if (nr < 0)
  1209. return nr;
  1210. return -EINVAL;
  1211. }
  1212. static int nvme_rdma_dma_map_req(struct ib_device *ibdev, struct request *rq,
  1213. int *count, int *pi_count)
  1214. {
  1215. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1216. int ret;
  1217. req->data_sgl.sg_table.sgl = (struct scatterlist *)(req + 1);
  1218. ret = sg_alloc_table_chained(&req->data_sgl.sg_table,
  1219. blk_rq_nr_phys_segments(rq), req->data_sgl.sg_table.sgl,
  1220. NVME_INLINE_SG_CNT);
  1221. if (ret)
  1222. return -ENOMEM;
  1223. req->data_sgl.nents = blk_rq_map_sg(rq->q, rq,
  1224. req->data_sgl.sg_table.sgl);
  1225. *count = ib_dma_map_sg(ibdev, req->data_sgl.sg_table.sgl,
  1226. req->data_sgl.nents, rq_dma_dir(rq));
  1227. if (unlikely(*count <= 0)) {
  1228. ret = -EIO;
  1229. goto out_free_table;
  1230. }
  1231. if (blk_integrity_rq(rq)) {
  1232. req->metadata_sgl->sg_table.sgl =
  1233. (struct scatterlist *)(req->metadata_sgl + 1);
  1234. ret = sg_alloc_table_chained(&req->metadata_sgl->sg_table,
  1235. rq->nr_integrity_segments,
  1236. req->metadata_sgl->sg_table.sgl,
  1237. NVME_INLINE_METADATA_SG_CNT);
  1238. if (unlikely(ret)) {
  1239. ret = -ENOMEM;
  1240. goto out_unmap_sg;
  1241. }
  1242. req->metadata_sgl->nents = blk_rq_map_integrity_sg(rq,
  1243. req->metadata_sgl->sg_table.sgl);
  1244. *pi_count = ib_dma_map_sg(ibdev,
  1245. req->metadata_sgl->sg_table.sgl,
  1246. req->metadata_sgl->nents,
  1247. rq_dma_dir(rq));
  1248. if (unlikely(*pi_count <= 0)) {
  1249. ret = -EIO;
  1250. goto out_free_pi_table;
  1251. }
  1252. }
  1253. return 0;
  1254. out_free_pi_table:
  1255. sg_free_table_chained(&req->metadata_sgl->sg_table,
  1256. NVME_INLINE_METADATA_SG_CNT);
  1257. out_unmap_sg:
  1258. ib_dma_unmap_sg(ibdev, req->data_sgl.sg_table.sgl, req->data_sgl.nents,
  1259. rq_dma_dir(rq));
  1260. out_free_table:
  1261. sg_free_table_chained(&req->data_sgl.sg_table, NVME_INLINE_SG_CNT);
  1262. return ret;
  1263. }
  1264. static int nvme_rdma_map_data(struct nvme_rdma_queue *queue,
  1265. struct request *rq, struct nvme_command *c)
  1266. {
  1267. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1268. struct nvme_rdma_device *dev = queue->device;
  1269. struct ib_device *ibdev = dev->dev;
  1270. int pi_count = 0;
  1271. int count, ret;
  1272. req->num_sge = 1;
  1273. refcount_set(&req->ref, 2); /* send and recv completions */
  1274. c->common.flags |= NVME_CMD_SGL_METABUF;
  1275. if (!blk_rq_nr_phys_segments(rq))
  1276. return nvme_rdma_set_sg_null(c);
  1277. ret = nvme_rdma_dma_map_req(ibdev, rq, &count, &pi_count);
  1278. if (unlikely(ret))
  1279. return ret;
  1280. if (req->use_sig_mr) {
  1281. ret = nvme_rdma_map_sg_pi(queue, req, c, count, pi_count);
  1282. goto out;
  1283. }
  1284. if (count <= dev->num_inline_segments) {
  1285. if (rq_data_dir(rq) == WRITE && nvme_rdma_queue_idx(queue) &&
  1286. queue->ctrl->use_inline_data &&
  1287. blk_rq_payload_bytes(rq) <=
  1288. nvme_rdma_inline_data_size(queue)) {
  1289. ret = nvme_rdma_map_sg_inline(queue, req, c, count);
  1290. goto out;
  1291. }
  1292. if (count == 1 && dev->pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) {
  1293. ret = nvme_rdma_map_sg_single(queue, req, c);
  1294. goto out;
  1295. }
  1296. }
  1297. ret = nvme_rdma_map_sg_fr(queue, req, c, count);
  1298. out:
  1299. if (unlikely(ret))
  1300. goto out_dma_unmap_req;
  1301. return 0;
  1302. out_dma_unmap_req:
  1303. nvme_rdma_dma_unmap_req(ibdev, rq);
  1304. return ret;
  1305. }
  1306. static void nvme_rdma_send_done(struct ib_cq *cq, struct ib_wc *wc)
  1307. {
  1308. struct nvme_rdma_qe *qe =
  1309. container_of(wc->wr_cqe, struct nvme_rdma_qe, cqe);
  1310. struct nvme_rdma_request *req =
  1311. container_of(qe, struct nvme_rdma_request, sqe);
  1312. if (unlikely(wc->status != IB_WC_SUCCESS))
  1313. nvme_rdma_wr_error(cq, wc, "SEND");
  1314. else
  1315. nvme_rdma_end_request(req);
  1316. }
  1317. static int nvme_rdma_post_send(struct nvme_rdma_queue *queue,
  1318. struct nvme_rdma_qe *qe, struct ib_sge *sge, u32 num_sge,
  1319. struct ib_send_wr *first)
  1320. {
  1321. struct ib_send_wr wr;
  1322. int ret;
  1323. sge->addr = qe->dma;
  1324. sge->length = sizeof(struct nvme_command);
  1325. sge->lkey = queue->device->pd->local_dma_lkey;
  1326. wr.next = NULL;
  1327. wr.wr_cqe = &qe->cqe;
  1328. wr.sg_list = sge;
  1329. wr.num_sge = num_sge;
  1330. wr.opcode = IB_WR_SEND;
  1331. wr.send_flags = IB_SEND_SIGNALED;
  1332. if (first)
  1333. first->next = &wr;
  1334. else
  1335. first = &wr;
  1336. ret = ib_post_send(queue->qp, first, NULL);
  1337. if (unlikely(ret)) {
  1338. dev_err(queue->ctrl->ctrl.device,
  1339. "%s failed with error code %d\n", __func__, ret);
  1340. }
  1341. return ret;
  1342. }
  1343. static int nvme_rdma_post_recv(struct nvme_rdma_queue *queue,
  1344. struct nvme_rdma_qe *qe)
  1345. {
  1346. struct ib_recv_wr wr;
  1347. struct ib_sge list;
  1348. int ret;
  1349. list.addr = qe->dma;
  1350. list.length = sizeof(struct nvme_completion);
  1351. list.lkey = queue->device->pd->local_dma_lkey;
  1352. qe->cqe.done = nvme_rdma_recv_done;
  1353. wr.next = NULL;
  1354. wr.wr_cqe = &qe->cqe;
  1355. wr.sg_list = &list;
  1356. wr.num_sge = 1;
  1357. ret = ib_post_recv(queue->qp, &wr, NULL);
  1358. if (unlikely(ret)) {
  1359. dev_err(queue->ctrl->ctrl.device,
  1360. "%s failed with error code %d\n", __func__, ret);
  1361. }
  1362. return ret;
  1363. }
  1364. static struct blk_mq_tags *nvme_rdma_tagset(struct nvme_rdma_queue *queue)
  1365. {
  1366. u32 queue_idx = nvme_rdma_queue_idx(queue);
  1367. if (queue_idx == 0)
  1368. return queue->ctrl->admin_tag_set.tags[queue_idx];
  1369. return queue->ctrl->tag_set.tags[queue_idx - 1];
  1370. }
  1371. static void nvme_rdma_async_done(struct ib_cq *cq, struct ib_wc *wc)
  1372. {
  1373. if (unlikely(wc->status != IB_WC_SUCCESS))
  1374. nvme_rdma_wr_error(cq, wc, "ASYNC");
  1375. }
  1376. static void nvme_rdma_submit_async_event(struct nvme_ctrl *arg)
  1377. {
  1378. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(arg);
  1379. struct nvme_rdma_queue *queue = &ctrl->queues[0];
  1380. struct ib_device *dev = queue->device->dev;
  1381. struct nvme_rdma_qe *sqe = &ctrl->async_event_sqe;
  1382. struct nvme_command *cmd = sqe->data;
  1383. struct ib_sge sge;
  1384. int ret;
  1385. ib_dma_sync_single_for_cpu(dev, sqe->dma, sizeof(*cmd), DMA_TO_DEVICE);
  1386. memset(cmd, 0, sizeof(*cmd));
  1387. cmd->common.opcode = nvme_admin_async_event;
  1388. cmd->common.command_id = NVME_AQ_BLK_MQ_DEPTH;
  1389. cmd->common.flags |= NVME_CMD_SGL_METABUF;
  1390. nvme_rdma_set_sg_null(cmd);
  1391. sqe->cqe.done = nvme_rdma_async_done;
  1392. ib_dma_sync_single_for_device(dev, sqe->dma, sizeof(*cmd),
  1393. DMA_TO_DEVICE);
  1394. ret = nvme_rdma_post_send(queue, sqe, &sge, 1, NULL);
  1395. WARN_ON_ONCE(ret);
  1396. }
  1397. static void nvme_rdma_process_nvme_rsp(struct nvme_rdma_queue *queue,
  1398. struct nvme_completion *cqe, struct ib_wc *wc)
  1399. {
  1400. struct request *rq;
  1401. struct nvme_rdma_request *req;
  1402. rq = nvme_find_rq(nvme_rdma_tagset(queue), cqe->command_id);
  1403. if (!rq) {
  1404. dev_err(queue->ctrl->ctrl.device,
  1405. "got bad command_id %#x on QP %#x\n",
  1406. cqe->command_id, queue->qp->qp_num);
  1407. nvme_rdma_error_recovery(queue->ctrl);
  1408. return;
  1409. }
  1410. req = blk_mq_rq_to_pdu(rq);
  1411. req->status = cqe->status;
  1412. req->result = cqe->result;
  1413. if (wc->wc_flags & IB_WC_WITH_INVALIDATE) {
  1414. if (unlikely(!req->mr ||
  1415. wc->ex.invalidate_rkey != req->mr->rkey)) {
  1416. dev_err(queue->ctrl->ctrl.device,
  1417. "Bogus remote invalidation for rkey %#x\n",
  1418. req->mr ? req->mr->rkey : 0);
  1419. nvme_rdma_error_recovery(queue->ctrl);
  1420. }
  1421. } else if (req->mr) {
  1422. int ret;
  1423. ret = nvme_rdma_inv_rkey(queue, req);
  1424. if (unlikely(ret < 0)) {
  1425. dev_err(queue->ctrl->ctrl.device,
  1426. "Queueing INV WR for rkey %#x failed (%d)\n",
  1427. req->mr->rkey, ret);
  1428. nvme_rdma_error_recovery(queue->ctrl);
  1429. }
  1430. /* the local invalidation completion will end the request */
  1431. return;
  1432. }
  1433. nvme_rdma_end_request(req);
  1434. }
  1435. static void nvme_rdma_recv_done(struct ib_cq *cq, struct ib_wc *wc)
  1436. {
  1437. struct nvme_rdma_qe *qe =
  1438. container_of(wc->wr_cqe, struct nvme_rdma_qe, cqe);
  1439. struct nvme_rdma_queue *queue = wc->qp->qp_context;
  1440. struct ib_device *ibdev = queue->device->dev;
  1441. struct nvme_completion *cqe = qe->data;
  1442. const size_t len = sizeof(struct nvme_completion);
  1443. if (unlikely(wc->status != IB_WC_SUCCESS)) {
  1444. nvme_rdma_wr_error(cq, wc, "RECV");
  1445. return;
  1446. }
  1447. /* sanity checking for received data length */
  1448. if (unlikely(wc->byte_len < len)) {
  1449. dev_err(queue->ctrl->ctrl.device,
  1450. "Unexpected nvme completion length(%d)\n", wc->byte_len);
  1451. nvme_rdma_error_recovery(queue->ctrl);
  1452. return;
  1453. }
  1454. ib_dma_sync_single_for_cpu(ibdev, qe->dma, len, DMA_FROM_DEVICE);
  1455. /*
  1456. * AEN requests are special as they don't time out and can
  1457. * survive any kind of queue freeze and often don't respond to
  1458. * aborts. We don't even bother to allocate a struct request
  1459. * for them but rather special case them here.
  1460. */
  1461. if (unlikely(nvme_is_aen_req(nvme_rdma_queue_idx(queue),
  1462. cqe->command_id)))
  1463. nvme_complete_async_event(&queue->ctrl->ctrl, cqe->status,
  1464. &cqe->result);
  1465. else
  1466. nvme_rdma_process_nvme_rsp(queue, cqe, wc);
  1467. ib_dma_sync_single_for_device(ibdev, qe->dma, len, DMA_FROM_DEVICE);
  1468. nvme_rdma_post_recv(queue, qe);
  1469. }
  1470. static int nvme_rdma_conn_established(struct nvme_rdma_queue *queue)
  1471. {
  1472. int ret, i;
  1473. for (i = 0; i < queue->queue_size; i++) {
  1474. ret = nvme_rdma_post_recv(queue, &queue->rsp_ring[i]);
  1475. if (ret)
  1476. return ret;
  1477. }
  1478. return 0;
  1479. }
  1480. static int nvme_rdma_conn_rejected(struct nvme_rdma_queue *queue,
  1481. struct rdma_cm_event *ev)
  1482. {
  1483. struct rdma_cm_id *cm_id = queue->cm_id;
  1484. int status = ev->status;
  1485. const char *rej_msg;
  1486. const struct nvme_rdma_cm_rej *rej_data;
  1487. u8 rej_data_len;
  1488. rej_msg = rdma_reject_msg(cm_id, status);
  1489. rej_data = rdma_consumer_reject_data(cm_id, ev, &rej_data_len);
  1490. if (rej_data && rej_data_len >= sizeof(u16)) {
  1491. u16 sts = le16_to_cpu(rej_data->sts);
  1492. dev_err(queue->ctrl->ctrl.device,
  1493. "Connect rejected: status %d (%s) nvme status %d (%s).\n",
  1494. status, rej_msg, sts, nvme_rdma_cm_msg(sts));
  1495. } else {
  1496. dev_err(queue->ctrl->ctrl.device,
  1497. "Connect rejected: status %d (%s).\n", status, rej_msg);
  1498. }
  1499. return -ECONNRESET;
  1500. }
  1501. static int nvme_rdma_addr_resolved(struct nvme_rdma_queue *queue)
  1502. {
  1503. struct nvme_ctrl *ctrl = &queue->ctrl->ctrl;
  1504. int ret;
  1505. ret = nvme_rdma_create_queue_ib(queue);
  1506. if (ret)
  1507. return ret;
  1508. if (ctrl->opts->tos >= 0)
  1509. rdma_set_service_type(queue->cm_id, ctrl->opts->tos);
  1510. ret = rdma_resolve_route(queue->cm_id, NVME_RDMA_CM_TIMEOUT_MS);
  1511. if (ret) {
  1512. dev_err(ctrl->device, "rdma_resolve_route failed (%d).\n",
  1513. queue->cm_error);
  1514. goto out_destroy_queue;
  1515. }
  1516. return 0;
  1517. out_destroy_queue:
  1518. nvme_rdma_destroy_queue_ib(queue);
  1519. return ret;
  1520. }
  1521. static int nvme_rdma_route_resolved(struct nvme_rdma_queue *queue)
  1522. {
  1523. struct nvme_rdma_ctrl *ctrl = queue->ctrl;
  1524. struct rdma_conn_param param = { };
  1525. struct nvme_rdma_cm_req priv = { };
  1526. int ret;
  1527. param.qp_num = queue->qp->qp_num;
  1528. param.flow_control = 1;
  1529. param.responder_resources = queue->device->dev->attrs.max_qp_rd_atom;
  1530. /* maximum retry count */
  1531. param.retry_count = 7;
  1532. param.rnr_retry_count = 7;
  1533. param.private_data = &priv;
  1534. param.private_data_len = sizeof(priv);
  1535. priv.recfmt = cpu_to_le16(NVME_RDMA_CM_FMT_1_0);
  1536. priv.qid = cpu_to_le16(nvme_rdma_queue_idx(queue));
  1537. /*
  1538. * set the admin queue depth to the minimum size
  1539. * specified by the Fabrics standard.
  1540. */
  1541. if (priv.qid == 0) {
  1542. priv.hrqsize = cpu_to_le16(NVME_AQ_DEPTH);
  1543. priv.hsqsize = cpu_to_le16(NVME_AQ_DEPTH - 1);
  1544. } else {
  1545. /*
  1546. * current interpretation of the fabrics spec
  1547. * is at minimum you make hrqsize sqsize+1, or a
  1548. * 1's based representation of sqsize.
  1549. */
  1550. priv.hrqsize = cpu_to_le16(queue->queue_size);
  1551. priv.hsqsize = cpu_to_le16(queue->ctrl->ctrl.sqsize);
  1552. /* cntlid should only be set when creating an I/O queue */
  1553. priv.cntlid = cpu_to_le16(ctrl->ctrl.cntlid);
  1554. }
  1555. ret = rdma_connect_locked(queue->cm_id, &param);
  1556. if (ret) {
  1557. dev_err(ctrl->ctrl.device,
  1558. "rdma_connect_locked failed (%d).\n", ret);
  1559. return ret;
  1560. }
  1561. return 0;
  1562. }
  1563. static int nvme_rdma_cm_handler(struct rdma_cm_id *cm_id,
  1564. struct rdma_cm_event *ev)
  1565. {
  1566. struct nvme_rdma_queue *queue = cm_id->context;
  1567. int cm_error = 0;
  1568. dev_dbg(queue->ctrl->ctrl.device, "%s (%d): status %d id %p\n",
  1569. rdma_event_msg(ev->event), ev->event,
  1570. ev->status, cm_id);
  1571. switch (ev->event) {
  1572. case RDMA_CM_EVENT_ADDR_RESOLVED:
  1573. cm_error = nvme_rdma_addr_resolved(queue);
  1574. break;
  1575. case RDMA_CM_EVENT_ROUTE_RESOLVED:
  1576. cm_error = nvme_rdma_route_resolved(queue);
  1577. break;
  1578. case RDMA_CM_EVENT_ESTABLISHED:
  1579. queue->cm_error = nvme_rdma_conn_established(queue);
  1580. /* complete cm_done regardless of success/failure */
  1581. complete(&queue->cm_done);
  1582. return 0;
  1583. case RDMA_CM_EVENT_REJECTED:
  1584. cm_error = nvme_rdma_conn_rejected(queue, ev);
  1585. break;
  1586. case RDMA_CM_EVENT_ROUTE_ERROR:
  1587. case RDMA_CM_EVENT_CONNECT_ERROR:
  1588. case RDMA_CM_EVENT_UNREACHABLE:
  1589. case RDMA_CM_EVENT_ADDR_ERROR:
  1590. dev_dbg(queue->ctrl->ctrl.device,
  1591. "CM error event %d\n", ev->event);
  1592. cm_error = -ECONNRESET;
  1593. break;
  1594. case RDMA_CM_EVENT_DISCONNECTED:
  1595. case RDMA_CM_EVENT_ADDR_CHANGE:
  1596. case RDMA_CM_EVENT_TIMEWAIT_EXIT:
  1597. dev_dbg(queue->ctrl->ctrl.device,
  1598. "disconnect received - connection closed\n");
  1599. nvme_rdma_error_recovery(queue->ctrl);
  1600. break;
  1601. case RDMA_CM_EVENT_DEVICE_REMOVAL:
  1602. /* device removal is handled via the ib_client API */
  1603. break;
  1604. default:
  1605. dev_err(queue->ctrl->ctrl.device,
  1606. "Unexpected RDMA CM event (%d)\n", ev->event);
  1607. nvme_rdma_error_recovery(queue->ctrl);
  1608. break;
  1609. }
  1610. if (cm_error) {
  1611. queue->cm_error = cm_error;
  1612. complete(&queue->cm_done);
  1613. }
  1614. return 0;
  1615. }
  1616. static void nvme_rdma_complete_timed_out(struct request *rq)
  1617. {
  1618. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1619. struct nvme_rdma_queue *queue = req->queue;
  1620. nvme_rdma_stop_queue(queue);
  1621. nvmf_complete_timed_out_request(rq);
  1622. }
  1623. static enum blk_eh_timer_return nvme_rdma_timeout(struct request *rq)
  1624. {
  1625. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1626. struct nvme_rdma_queue *queue = req->queue;
  1627. struct nvme_rdma_ctrl *ctrl = queue->ctrl;
  1628. struct nvme_command *cmd = req->req.cmd;
  1629. int qid = nvme_rdma_queue_idx(queue);
  1630. dev_warn(ctrl->ctrl.device,
  1631. "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout\n",
  1632. rq->tag, nvme_cid(rq), cmd->common.opcode,
  1633. nvme_fabrics_opcode_str(qid, cmd), qid);
  1634. if (nvme_ctrl_state(&ctrl->ctrl) != NVME_CTRL_LIVE) {
  1635. /*
  1636. * If we are resetting, connecting or deleting we should
  1637. * complete immediately because we may block controller
  1638. * teardown or setup sequence
  1639. * - ctrl disable/shutdown fabrics requests
  1640. * - connect requests
  1641. * - initialization admin requests
  1642. * - I/O requests that entered after unquiescing and
  1643. * the controller stopped responding
  1644. *
  1645. * All other requests should be cancelled by the error
  1646. * recovery work, so it's fine that we fail it here.
  1647. */
  1648. nvme_rdma_complete_timed_out(rq);
  1649. return BLK_EH_DONE;
  1650. }
  1651. /*
  1652. * LIVE state should trigger the normal error recovery which will
  1653. * handle completing this request.
  1654. */
  1655. nvme_rdma_error_recovery(ctrl);
  1656. return BLK_EH_RESET_TIMER;
  1657. }
  1658. static blk_status_t nvme_rdma_queue_rq(struct blk_mq_hw_ctx *hctx,
  1659. const struct blk_mq_queue_data *bd)
  1660. {
  1661. struct nvme_ns *ns = hctx->queue->queuedata;
  1662. struct nvme_rdma_queue *queue = hctx->driver_data;
  1663. struct request *rq = bd->rq;
  1664. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1665. struct nvme_rdma_qe *sqe = &req->sqe;
  1666. struct nvme_command *c = nvme_req(rq)->cmd;
  1667. struct ib_device *dev;
  1668. bool queue_ready = test_bit(NVME_RDMA_Q_LIVE, &queue->flags);
  1669. blk_status_t ret;
  1670. int err;
  1671. WARN_ON_ONCE(rq->tag < 0);
  1672. if (!nvme_check_ready(&queue->ctrl->ctrl, rq, queue_ready))
  1673. return nvme_fail_nonready_command(&queue->ctrl->ctrl, rq);
  1674. dev = queue->device->dev;
  1675. req->sqe.dma = ib_dma_map_single(dev, req->sqe.data,
  1676. sizeof(struct nvme_command),
  1677. DMA_TO_DEVICE);
  1678. err = ib_dma_mapping_error(dev, req->sqe.dma);
  1679. if (unlikely(err))
  1680. return BLK_STS_RESOURCE;
  1681. ib_dma_sync_single_for_cpu(dev, sqe->dma,
  1682. sizeof(struct nvme_command), DMA_TO_DEVICE);
  1683. ret = nvme_setup_cmd(ns, rq);
  1684. if (ret)
  1685. goto unmap_qe;
  1686. nvme_start_request(rq);
  1687. if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) &&
  1688. queue->pi_support &&
  1689. (c->common.opcode == nvme_cmd_write ||
  1690. c->common.opcode == nvme_cmd_read) &&
  1691. nvme_ns_has_pi(ns->head))
  1692. req->use_sig_mr = true;
  1693. else
  1694. req->use_sig_mr = false;
  1695. err = nvme_rdma_map_data(queue, rq, c);
  1696. if (unlikely(err < 0)) {
  1697. dev_err(queue->ctrl->ctrl.device,
  1698. "Failed to map data (%d)\n", err);
  1699. goto err;
  1700. }
  1701. sqe->cqe.done = nvme_rdma_send_done;
  1702. ib_dma_sync_single_for_device(dev, sqe->dma,
  1703. sizeof(struct nvme_command), DMA_TO_DEVICE);
  1704. err = nvme_rdma_post_send(queue, sqe, req->sge, req->num_sge,
  1705. req->mr ? &req->reg_wr.wr : NULL);
  1706. if (unlikely(err))
  1707. goto err_unmap;
  1708. return BLK_STS_OK;
  1709. err_unmap:
  1710. nvme_rdma_unmap_data(queue, rq);
  1711. err:
  1712. if (err == -EIO)
  1713. ret = nvme_host_path_error(rq);
  1714. else if (err == -ENOMEM || err == -EAGAIN)
  1715. ret = BLK_STS_RESOURCE;
  1716. else
  1717. ret = BLK_STS_IOERR;
  1718. nvme_cleanup_cmd(rq);
  1719. unmap_qe:
  1720. ib_dma_unmap_single(dev, req->sqe.dma, sizeof(struct nvme_command),
  1721. DMA_TO_DEVICE);
  1722. return ret;
  1723. }
  1724. static int nvme_rdma_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
  1725. {
  1726. struct nvme_rdma_queue *queue = hctx->driver_data;
  1727. return ib_process_cq_direct(queue->ib_cq, -1);
  1728. }
  1729. static void nvme_rdma_check_pi_status(struct nvme_rdma_request *req)
  1730. {
  1731. struct request *rq = blk_mq_rq_from_pdu(req);
  1732. struct ib_mr_status mr_status;
  1733. int ret;
  1734. ret = ib_check_mr_status(req->mr, IB_MR_CHECK_SIG_STATUS, &mr_status);
  1735. if (ret) {
  1736. pr_err("ib_check_mr_status failed, ret %d\n", ret);
  1737. nvme_req(rq)->status = NVME_SC_INVALID_PI;
  1738. return;
  1739. }
  1740. if (mr_status.fail_status & IB_MR_CHECK_SIG_STATUS) {
  1741. switch (mr_status.sig_err.err_type) {
  1742. case IB_SIG_BAD_GUARD:
  1743. nvme_req(rq)->status = NVME_SC_GUARD_CHECK;
  1744. break;
  1745. case IB_SIG_BAD_REFTAG:
  1746. nvme_req(rq)->status = NVME_SC_REFTAG_CHECK;
  1747. break;
  1748. case IB_SIG_BAD_APPTAG:
  1749. nvme_req(rq)->status = NVME_SC_APPTAG_CHECK;
  1750. break;
  1751. }
  1752. pr_err("PI error found type %d expected 0x%x vs actual 0x%x\n",
  1753. mr_status.sig_err.err_type, mr_status.sig_err.expected,
  1754. mr_status.sig_err.actual);
  1755. }
  1756. }
  1757. static void nvme_rdma_complete_rq(struct request *rq)
  1758. {
  1759. struct nvme_rdma_request *req = blk_mq_rq_to_pdu(rq);
  1760. struct nvme_rdma_queue *queue = req->queue;
  1761. struct ib_device *ibdev = queue->device->dev;
  1762. if (req->use_sig_mr)
  1763. nvme_rdma_check_pi_status(req);
  1764. nvme_rdma_unmap_data(queue, rq);
  1765. ib_dma_unmap_single(ibdev, req->sqe.dma, sizeof(struct nvme_command),
  1766. DMA_TO_DEVICE);
  1767. nvme_complete_rq(rq);
  1768. }
  1769. static void nvme_rdma_map_queues(struct blk_mq_tag_set *set)
  1770. {
  1771. struct nvme_rdma_ctrl *ctrl = to_rdma_ctrl(set->driver_data);
  1772. nvmf_map_queues(set, &ctrl->ctrl, ctrl->io_queues);
  1773. }
  1774. static const struct blk_mq_ops nvme_rdma_mq_ops = {
  1775. .queue_rq = nvme_rdma_queue_rq,
  1776. .complete = nvme_rdma_complete_rq,
  1777. .init_request = nvme_rdma_init_request,
  1778. .exit_request = nvme_rdma_exit_request,
  1779. .init_hctx = nvme_rdma_init_hctx,
  1780. .timeout = nvme_rdma_timeout,
  1781. .map_queues = nvme_rdma_map_queues,
  1782. .poll = nvme_rdma_poll,
  1783. };
  1784. static const struct blk_mq_ops nvme_rdma_admin_mq_ops = {
  1785. .queue_rq = nvme_rdma_queue_rq,
  1786. .complete = nvme_rdma_complete_rq,
  1787. .init_request = nvme_rdma_init_request,
  1788. .exit_request = nvme_rdma_exit_request,
  1789. .init_hctx = nvme_rdma_init_admin_hctx,
  1790. .timeout = nvme_rdma_timeout,
  1791. };
  1792. static void nvme_rdma_shutdown_ctrl(struct nvme_rdma_ctrl *ctrl, bool shutdown)
  1793. {
  1794. nvme_rdma_teardown_io_queues(ctrl, shutdown);
  1795. nvme_quiesce_admin_queue(&ctrl->ctrl);
  1796. nvme_disable_ctrl(&ctrl->ctrl, shutdown);
  1797. nvme_rdma_teardown_admin_queue(ctrl, shutdown);
  1798. }
  1799. static void nvme_rdma_delete_ctrl(struct nvme_ctrl *ctrl)
  1800. {
  1801. nvme_rdma_shutdown_ctrl(to_rdma_ctrl(ctrl), true);
  1802. }
  1803. static void nvme_rdma_reset_ctrl_work(struct work_struct *work)
  1804. {
  1805. struct nvme_rdma_ctrl *ctrl =
  1806. container_of(work, struct nvme_rdma_ctrl, ctrl.reset_work);
  1807. int ret;
  1808. nvme_stop_ctrl(&ctrl->ctrl);
  1809. nvme_rdma_shutdown_ctrl(ctrl, false);
  1810. if (!nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING)) {
  1811. /* state change failure should never happen */
  1812. WARN_ON_ONCE(1);
  1813. return;
  1814. }
  1815. ret = nvme_rdma_setup_ctrl(ctrl, false);
  1816. if (ret)
  1817. goto out_fail;
  1818. return;
  1819. out_fail:
  1820. ++ctrl->ctrl.nr_reconnects;
  1821. nvme_rdma_reconnect_or_remove(ctrl, ret);
  1822. }
  1823. static const struct nvme_ctrl_ops nvme_rdma_ctrl_ops = {
  1824. .name = "rdma",
  1825. .module = THIS_MODULE,
  1826. .flags = NVME_F_FABRICS | NVME_F_METADATA_SUPPORTED,
  1827. .reg_read32 = nvmf_reg_read32,
  1828. .reg_read64 = nvmf_reg_read64,
  1829. .reg_write32 = nvmf_reg_write32,
  1830. .subsystem_reset = nvmf_subsystem_reset,
  1831. .free_ctrl = nvme_rdma_free_ctrl,
  1832. .submit_async_event = nvme_rdma_submit_async_event,
  1833. .delete_ctrl = nvme_rdma_delete_ctrl,
  1834. .get_address = nvmf_get_address,
  1835. .stop_ctrl = nvme_rdma_stop_ctrl,
  1836. };
  1837. /*
  1838. * Fails a connection request if it matches an existing controller
  1839. * (association) with the same tuple:
  1840. * <Host NQN, Host ID, local address, remote address, remote port, SUBSYS NQN>
  1841. *
  1842. * if local address is not specified in the request, it will match an
  1843. * existing controller with all the other parameters the same and no
  1844. * local port address specified as well.
  1845. *
  1846. * The ports don't need to be compared as they are intrinsically
  1847. * already matched by the port pointers supplied.
  1848. */
  1849. static bool
  1850. nvme_rdma_existing_controller(struct nvmf_ctrl_options *opts)
  1851. {
  1852. struct nvme_rdma_ctrl *ctrl;
  1853. bool found = false;
  1854. mutex_lock(&nvme_rdma_ctrl_mutex);
  1855. list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list) {
  1856. found = nvmf_ip_options_match(&ctrl->ctrl, opts);
  1857. if (found)
  1858. break;
  1859. }
  1860. mutex_unlock(&nvme_rdma_ctrl_mutex);
  1861. return found;
  1862. }
  1863. static struct nvme_rdma_ctrl *nvme_rdma_alloc_ctrl(struct device *dev,
  1864. struct nvmf_ctrl_options *opts)
  1865. {
  1866. struct nvme_rdma_ctrl *ctrl;
  1867. int ret;
  1868. ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
  1869. if (!ctrl)
  1870. return ERR_PTR(-ENOMEM);
  1871. ctrl->ctrl.opts = opts;
  1872. INIT_LIST_HEAD(&ctrl->list);
  1873. if (!(opts->mask & NVMF_OPT_TRSVCID)) {
  1874. opts->trsvcid =
  1875. kstrdup(__stringify(NVME_RDMA_IP_PORT), GFP_KERNEL);
  1876. if (!opts->trsvcid) {
  1877. ret = -ENOMEM;
  1878. goto out_free_ctrl;
  1879. }
  1880. opts->mask |= NVMF_OPT_TRSVCID;
  1881. }
  1882. ret = inet_pton_with_scope(&init_net, AF_UNSPEC,
  1883. opts->traddr, opts->trsvcid, &ctrl->addr);
  1884. if (ret) {
  1885. pr_err("malformed address passed: %s:%s\n",
  1886. opts->traddr, opts->trsvcid);
  1887. goto out_free_ctrl;
  1888. }
  1889. if (opts->mask & NVMF_OPT_HOST_TRADDR) {
  1890. ret = inet_pton_with_scope(&init_net, AF_UNSPEC,
  1891. opts->host_traddr, NULL, &ctrl->src_addr);
  1892. if (ret) {
  1893. pr_err("malformed src address passed: %s\n",
  1894. opts->host_traddr);
  1895. goto out_free_ctrl;
  1896. }
  1897. }
  1898. if (!opts->duplicate_connect && nvme_rdma_existing_controller(opts)) {
  1899. ret = -EALREADY;
  1900. goto out_free_ctrl;
  1901. }
  1902. INIT_DELAYED_WORK(&ctrl->reconnect_work,
  1903. nvme_rdma_reconnect_ctrl_work);
  1904. INIT_WORK(&ctrl->err_work, nvme_rdma_error_recovery_work);
  1905. INIT_WORK(&ctrl->ctrl.reset_work, nvme_rdma_reset_ctrl_work);
  1906. ctrl->ctrl.queue_count = opts->nr_io_queues + opts->nr_write_queues +
  1907. opts->nr_poll_queues + 1;
  1908. ctrl->ctrl.sqsize = opts->queue_size - 1;
  1909. ctrl->ctrl.kato = opts->kato;
  1910. ret = -ENOMEM;
  1911. ctrl->queues = kcalloc(ctrl->ctrl.queue_count, sizeof(*ctrl->queues),
  1912. GFP_KERNEL);
  1913. if (!ctrl->queues)
  1914. goto out_free_ctrl;
  1915. ret = nvme_init_ctrl(&ctrl->ctrl, dev, &nvme_rdma_ctrl_ops,
  1916. 0 /* no quirks, we're perfect! */);
  1917. if (ret)
  1918. goto out_kfree_queues;
  1919. return ctrl;
  1920. out_kfree_queues:
  1921. kfree(ctrl->queues);
  1922. out_free_ctrl:
  1923. kfree(ctrl);
  1924. return ERR_PTR(ret);
  1925. }
  1926. static struct nvme_ctrl *nvme_rdma_create_ctrl(struct device *dev,
  1927. struct nvmf_ctrl_options *opts)
  1928. {
  1929. struct nvme_rdma_ctrl *ctrl;
  1930. bool changed;
  1931. int ret;
  1932. ctrl = nvme_rdma_alloc_ctrl(dev, opts);
  1933. if (IS_ERR(ctrl))
  1934. return ERR_CAST(ctrl);
  1935. ret = nvme_add_ctrl(&ctrl->ctrl);
  1936. if (ret)
  1937. goto out_put_ctrl;
  1938. changed = nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_CONNECTING);
  1939. WARN_ON_ONCE(!changed);
  1940. ret = nvme_rdma_setup_ctrl(ctrl, true);
  1941. if (ret)
  1942. goto out_uninit_ctrl;
  1943. dev_info(ctrl->ctrl.device, "new ctrl: NQN \"%s\", addr %pISpcs, hostnqn: %s\n",
  1944. nvmf_ctrl_subsysnqn(&ctrl->ctrl), &ctrl->addr, opts->host->nqn);
  1945. mutex_lock(&nvme_rdma_ctrl_mutex);
  1946. list_add_tail(&ctrl->list, &nvme_rdma_ctrl_list);
  1947. mutex_unlock(&nvme_rdma_ctrl_mutex);
  1948. return &ctrl->ctrl;
  1949. out_uninit_ctrl:
  1950. nvme_uninit_ctrl(&ctrl->ctrl);
  1951. out_put_ctrl:
  1952. nvme_put_ctrl(&ctrl->ctrl);
  1953. if (ret > 0)
  1954. ret = -EIO;
  1955. return ERR_PTR(ret);
  1956. }
  1957. static struct nvmf_transport_ops nvme_rdma_transport = {
  1958. .name = "rdma",
  1959. .module = THIS_MODULE,
  1960. .required_opts = NVMF_OPT_TRADDR,
  1961. .allowed_opts = NVMF_OPT_TRSVCID | NVMF_OPT_RECONNECT_DELAY |
  1962. NVMF_OPT_HOST_TRADDR | NVMF_OPT_CTRL_LOSS_TMO |
  1963. NVMF_OPT_NR_WRITE_QUEUES | NVMF_OPT_NR_POLL_QUEUES |
  1964. NVMF_OPT_TOS,
  1965. .create_ctrl = nvme_rdma_create_ctrl,
  1966. };
  1967. static void nvme_rdma_remove_one(struct ib_device *ib_device, void *client_data)
  1968. {
  1969. struct nvme_rdma_ctrl *ctrl;
  1970. struct nvme_rdma_device *ndev;
  1971. bool found = false;
  1972. mutex_lock(&device_list_mutex);
  1973. list_for_each_entry(ndev, &device_list, entry) {
  1974. if (ndev->dev == ib_device) {
  1975. found = true;
  1976. break;
  1977. }
  1978. }
  1979. mutex_unlock(&device_list_mutex);
  1980. if (!found)
  1981. return;
  1982. /* Delete all controllers using this device */
  1983. mutex_lock(&nvme_rdma_ctrl_mutex);
  1984. list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list) {
  1985. if (ctrl->device->dev != ib_device)
  1986. continue;
  1987. nvme_delete_ctrl(&ctrl->ctrl);
  1988. }
  1989. mutex_unlock(&nvme_rdma_ctrl_mutex);
  1990. flush_workqueue(nvme_delete_wq);
  1991. }
  1992. static struct ib_client nvme_rdma_ib_client = {
  1993. .name = "nvme_rdma",
  1994. .remove = nvme_rdma_remove_one
  1995. };
  1996. static int __init nvme_rdma_init_module(void)
  1997. {
  1998. int ret;
  1999. ret = ib_register_client(&nvme_rdma_ib_client);
  2000. if (ret)
  2001. return ret;
  2002. ret = nvmf_register_transport(&nvme_rdma_transport);
  2003. if (ret)
  2004. goto err_unreg_client;
  2005. return 0;
  2006. err_unreg_client:
  2007. ib_unregister_client(&nvme_rdma_ib_client);
  2008. return ret;
  2009. }
  2010. static void __exit nvme_rdma_cleanup_module(void)
  2011. {
  2012. struct nvme_rdma_ctrl *ctrl;
  2013. nvmf_unregister_transport(&nvme_rdma_transport);
  2014. ib_unregister_client(&nvme_rdma_ib_client);
  2015. mutex_lock(&nvme_rdma_ctrl_mutex);
  2016. list_for_each_entry(ctrl, &nvme_rdma_ctrl_list, list)
  2017. nvme_delete_ctrl(&ctrl->ctrl);
  2018. mutex_unlock(&nvme_rdma_ctrl_mutex);
  2019. flush_workqueue(nvme_delete_wq);
  2020. }
  2021. module_init(nvme_rdma_init_module);
  2022. module_exit(nvme_rdma_cleanup_module);
  2023. MODULE_DESCRIPTION("NVMe host RDMA transport driver");
  2024. MODULE_LICENSE("GPL v2");