pinctrl-axp209.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * AXP20x pinctrl and GPIO driver
  4. *
  5. * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
  6. * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/device.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/mfd/axp20x.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regmap.h>
  19. #include <linux/slab.h>
  20. #include <linux/pinctrl/consumer.h>
  21. #include <linux/pinctrl/pinconf-generic.h>
  22. #include <linux/pinctrl/pinctrl.h>
  23. #include <linux/pinctrl/pinmux.h>
  24. #define AXP20X_GPIO_FUNCTIONS 0x7
  25. #define AXP20X_GPIO_FUNCTION_OUT_LOW 0
  26. #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
  27. #define AXP20X_GPIO_FUNCTION_INPUT 2
  28. #define AXP20X_GPIO3_FUNCTIONS GENMASK(2, 1)
  29. #define AXP20X_GPIO3_FUNCTION_OUT_LOW 0
  30. #define AXP20X_GPIO3_FUNCTION_OUT_HIGH 2
  31. #define AXP20X_GPIO3_FUNCTION_INPUT 4
  32. #define AXP20X_FUNC_GPIO_OUT 0
  33. #define AXP20X_FUNC_GPIO_IN 1
  34. #define AXP20X_FUNC_LDO 2
  35. #define AXP20X_FUNC_ADC 3
  36. #define AXP20X_FUNCS_NB 4
  37. #define AXP20X_MUX_GPIO_OUT 0
  38. #define AXP20X_MUX_GPIO_IN BIT(1)
  39. #define AXP20X_MUX_ADC BIT(2)
  40. #define AXP813_MUX_ADC (BIT(2) | BIT(0))
  41. struct axp20x_pctrl_desc {
  42. const struct pinctrl_pin_desc *pins;
  43. unsigned int npins;
  44. /* Stores the pins supporting LDO function. Bit offset is pin number. */
  45. u8 ldo_mask;
  46. /* Stores the pins supporting ADC function. Bit offset is pin number. */
  47. u8 adc_mask;
  48. u8 gpio_status_offset;
  49. u8 adc_mux;
  50. };
  51. struct axp20x_pinctrl_function {
  52. const char *name;
  53. unsigned int muxval;
  54. const char **groups;
  55. unsigned int ngroups;
  56. };
  57. struct axp20x_pctl {
  58. struct gpio_chip chip;
  59. struct regmap *regmap;
  60. struct pinctrl_dev *pctl_dev;
  61. struct device *dev;
  62. const struct axp20x_pctrl_desc *desc;
  63. struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
  64. };
  65. static const struct pinctrl_pin_desc axp209_pins[] = {
  66. PINCTRL_PIN(0, "GPIO0"),
  67. PINCTRL_PIN(1, "GPIO1"),
  68. PINCTRL_PIN(2, "GPIO2"),
  69. PINCTRL_PIN(3, "GPIO3"),
  70. };
  71. static const struct pinctrl_pin_desc axp22x_pins[] = {
  72. PINCTRL_PIN(0, "GPIO0"),
  73. PINCTRL_PIN(1, "GPIO1"),
  74. };
  75. static const struct axp20x_pctrl_desc axp20x_data = {
  76. .pins = axp209_pins,
  77. .npins = ARRAY_SIZE(axp209_pins),
  78. .ldo_mask = BIT(0) | BIT(1),
  79. .adc_mask = BIT(0) | BIT(1),
  80. .gpio_status_offset = 4,
  81. .adc_mux = AXP20X_MUX_ADC,
  82. };
  83. static const struct axp20x_pctrl_desc axp22x_data = {
  84. .pins = axp22x_pins,
  85. .npins = ARRAY_SIZE(axp22x_pins),
  86. .ldo_mask = BIT(0) | BIT(1),
  87. .gpio_status_offset = 0,
  88. };
  89. static const struct axp20x_pctrl_desc axp813_data = {
  90. .pins = axp22x_pins,
  91. .npins = ARRAY_SIZE(axp22x_pins),
  92. .ldo_mask = BIT(0) | BIT(1),
  93. .adc_mask = BIT(0),
  94. .gpio_status_offset = 0,
  95. .adc_mux = AXP813_MUX_ADC,
  96. };
  97. static int axp20x_gpio_get_reg(unsigned int offset)
  98. {
  99. switch (offset) {
  100. case 0:
  101. return AXP20X_GPIO0_CTRL;
  102. case 1:
  103. return AXP20X_GPIO1_CTRL;
  104. case 2:
  105. return AXP20X_GPIO2_CTRL;
  106. }
  107. return -EINVAL;
  108. }
  109. static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  110. {
  111. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  112. unsigned int val;
  113. int ret;
  114. /* AXP209 has GPIO3 status sharing the settings register */
  115. if (offset == 3) {
  116. ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
  117. if (ret)
  118. return ret;
  119. return !!(val & BIT(0));
  120. }
  121. ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
  122. if (ret)
  123. return ret;
  124. return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
  125. }
  126. static int axp20x_gpio_get_direction(struct gpio_chip *chip,
  127. unsigned int offset)
  128. {
  129. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  130. unsigned int val;
  131. int reg, ret;
  132. /* AXP209 GPIO3 settings have a different layout */
  133. if (offset == 3) {
  134. ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val);
  135. if (ret)
  136. return ret;
  137. if (val & AXP20X_GPIO3_FUNCTION_INPUT)
  138. return GPIO_LINE_DIRECTION_IN;
  139. return GPIO_LINE_DIRECTION_OUT;
  140. }
  141. reg = axp20x_gpio_get_reg(offset);
  142. if (reg < 0)
  143. return reg;
  144. ret = regmap_read(pctl->regmap, reg, &val);
  145. if (ret)
  146. return ret;
  147. /*
  148. * This shouldn't really happen if the pin is in use already,
  149. * or if it's not in use yet, it doesn't matter since we're
  150. * going to change the value soon anyway. Default to output.
  151. */
  152. if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
  153. return GPIO_LINE_DIRECTION_OUT;
  154. /*
  155. * The GPIO directions are the three lowest values.
  156. * 2 is input, 0 and 1 are output
  157. */
  158. if (val & 2)
  159. return GPIO_LINE_DIRECTION_IN;
  160. return GPIO_LINE_DIRECTION_OUT;
  161. }
  162. static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
  163. int value)
  164. {
  165. chip->set(chip, offset, value);
  166. return 0;
  167. }
  168. static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
  169. int value)
  170. {
  171. struct axp20x_pctl *pctl = gpiochip_get_data(chip);
  172. int reg;
  173. /* AXP209 has GPIO3 status sharing the settings register */
  174. if (offset == 3) {
  175. regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
  176. AXP20X_GPIO3_FUNCTIONS,
  177. value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
  178. AXP20X_GPIO3_FUNCTION_OUT_LOW);
  179. return;
  180. }
  181. reg = axp20x_gpio_get_reg(offset);
  182. if (reg < 0)
  183. return;
  184. regmap_update_bits(pctl->regmap, reg,
  185. AXP20X_GPIO_FUNCTIONS,
  186. value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
  187. AXP20X_GPIO_FUNCTION_OUT_LOW);
  188. }
  189. static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
  190. u8 config)
  191. {
  192. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  193. int reg;
  194. /* AXP209 GPIO3 settings have a different layout */
  195. if (offset == 3) {
  196. return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
  197. AXP20X_GPIO3_FUNCTIONS,
  198. config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
  199. AXP20X_GPIO3_FUNCTION_INPUT);
  200. }
  201. reg = axp20x_gpio_get_reg(offset);
  202. if (reg < 0)
  203. return reg;
  204. return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
  205. config);
  206. }
  207. static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
  208. {
  209. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  210. return ARRAY_SIZE(pctl->funcs);
  211. }
  212. static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
  213. unsigned int selector)
  214. {
  215. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  216. return pctl->funcs[selector].name;
  217. }
  218. static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
  219. unsigned int selector,
  220. const char * const **groups,
  221. unsigned int *num_groups)
  222. {
  223. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  224. *groups = pctl->funcs[selector].groups;
  225. *num_groups = pctl->funcs[selector].ngroups;
  226. return 0;
  227. }
  228. static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
  229. unsigned int function, unsigned int group)
  230. {
  231. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  232. unsigned int mask;
  233. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  234. if (function <= AXP20X_FUNC_GPIO_IN)
  235. return axp20x_pmx_set(pctldev, group,
  236. pctl->funcs[function].muxval);
  237. if (function == AXP20X_FUNC_LDO)
  238. mask = pctl->desc->ldo_mask;
  239. else
  240. mask = pctl->desc->adc_mask;
  241. if (!(BIT(group) & mask))
  242. return -EINVAL;
  243. /*
  244. * We let the regulator framework handle the LDO muxing as muxing bits
  245. * are basically also regulators on/off bits. It's better not to enforce
  246. * any state of the regulator when selecting LDO mux so that we don't
  247. * interfere with the regulator driver.
  248. */
  249. if (function == AXP20X_FUNC_LDO)
  250. return 0;
  251. return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
  252. }
  253. static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  254. struct pinctrl_gpio_range *range,
  255. unsigned int offset, bool input)
  256. {
  257. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  258. if (input)
  259. return axp20x_pmx_set(pctldev, offset,
  260. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
  261. return axp20x_pmx_set(pctldev, offset,
  262. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
  263. }
  264. static const struct pinmux_ops axp20x_pmx_ops = {
  265. .get_functions_count = axp20x_pmx_func_cnt,
  266. .get_function_name = axp20x_pmx_func_name,
  267. .get_function_groups = axp20x_pmx_func_groups,
  268. .set_mux = axp20x_pmx_set_mux,
  269. .gpio_set_direction = axp20x_pmx_gpio_set_direction,
  270. .strict = true,
  271. };
  272. static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
  273. {
  274. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  275. return pctl->desc->npins;
  276. }
  277. static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
  278. const unsigned int **pins, unsigned int *num_pins)
  279. {
  280. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  281. *pins = (unsigned int *)&pctl->desc->pins[selector];
  282. *num_pins = 1;
  283. return 0;
  284. }
  285. static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
  286. unsigned int selector)
  287. {
  288. struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
  289. return pctl->desc->pins[selector].name;
  290. }
  291. static const struct pinctrl_ops axp20x_pctrl_ops = {
  292. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  293. .dt_free_map = pinconf_generic_dt_free_map,
  294. .get_groups_count = axp20x_groups_cnt,
  295. .get_group_name = axp20x_group_name,
  296. .get_group_pins = axp20x_group_pins,
  297. };
  298. static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
  299. unsigned int mask_len,
  300. struct axp20x_pinctrl_function *func,
  301. const struct pinctrl_pin_desc *pins)
  302. {
  303. unsigned long int mask_cpy = mask;
  304. const char **group;
  305. unsigned int ngroups = hweight8(mask);
  306. int bit;
  307. func->ngroups = ngroups;
  308. if (func->ngroups > 0) {
  309. func->groups = devm_kcalloc(dev,
  310. ngroups, sizeof(const char *),
  311. GFP_KERNEL);
  312. if (!func->groups)
  313. return -ENOMEM;
  314. group = func->groups;
  315. for_each_set_bit(bit, &mask_cpy, mask_len) {
  316. *group = pins[bit].name;
  317. group++;
  318. }
  319. }
  320. return 0;
  321. }
  322. static int axp20x_build_funcs_groups(struct platform_device *pdev)
  323. {
  324. struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
  325. int i, ret, pin, npins = pctl->desc->npins;
  326. pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
  327. pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
  328. pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
  329. pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
  330. pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
  331. /*
  332. * Muxval for LDO is useless as we won't use it.
  333. * See comment in axp20x_pmx_set_mux.
  334. */
  335. pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
  336. pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
  337. /* Every pin supports GPIO_OUT and GPIO_IN functions */
  338. for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
  339. pctl->funcs[i].ngroups = npins;
  340. pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
  341. npins, sizeof(char *),
  342. GFP_KERNEL);
  343. if (!pctl->funcs[i].groups)
  344. return -ENOMEM;
  345. for (pin = 0; pin < npins; pin++)
  346. pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
  347. }
  348. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
  349. npins, &pctl->funcs[AXP20X_FUNC_LDO],
  350. pctl->desc->pins);
  351. if (ret)
  352. return ret;
  353. ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
  354. npins, &pctl->funcs[AXP20X_FUNC_ADC],
  355. pctl->desc->pins);
  356. if (ret)
  357. return ret;
  358. return 0;
  359. }
  360. static const struct of_device_id axp20x_pctl_match[] = {
  361. { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
  362. { .compatible = "x-powers,axp221-gpio", .data = &axp22x_data, },
  363. { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
  364. { }
  365. };
  366. MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
  367. static int axp20x_pctl_probe(struct platform_device *pdev)
  368. {
  369. struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
  370. struct axp20x_pctl *pctl;
  371. struct device *dev = &pdev->dev;
  372. struct pinctrl_desc *pctrl_desc;
  373. int ret;
  374. if (!of_device_is_available(pdev->dev.of_node))
  375. return -ENODEV;
  376. if (!axp20x) {
  377. dev_err(&pdev->dev, "Parent drvdata not set\n");
  378. return -EINVAL;
  379. }
  380. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  381. if (!pctl)
  382. return -ENOMEM;
  383. pctl->chip.base = -1;
  384. pctl->chip.can_sleep = true;
  385. pctl->chip.request = gpiochip_generic_request;
  386. pctl->chip.free = gpiochip_generic_free;
  387. pctl->chip.parent = &pdev->dev;
  388. pctl->chip.label = dev_name(&pdev->dev);
  389. pctl->chip.owner = THIS_MODULE;
  390. pctl->chip.get = axp20x_gpio_get;
  391. pctl->chip.get_direction = axp20x_gpio_get_direction;
  392. pctl->chip.set = axp20x_gpio_set;
  393. pctl->chip.direction_input = pinctrl_gpio_direction_input;
  394. pctl->chip.direction_output = axp20x_gpio_output;
  395. pctl->desc = of_device_get_match_data(dev);
  396. pctl->chip.ngpio = pctl->desc->npins;
  397. pctl->regmap = axp20x->regmap;
  398. pctl->dev = &pdev->dev;
  399. platform_set_drvdata(pdev, pctl);
  400. ret = axp20x_build_funcs_groups(pdev);
  401. if (ret) {
  402. dev_err(&pdev->dev, "failed to build groups\n");
  403. return ret;
  404. }
  405. pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
  406. if (!pctrl_desc)
  407. return -ENOMEM;
  408. pctrl_desc->name = dev_name(&pdev->dev);
  409. pctrl_desc->owner = THIS_MODULE;
  410. pctrl_desc->pins = pctl->desc->pins;
  411. pctrl_desc->npins = pctl->desc->npins;
  412. pctrl_desc->pctlops = &axp20x_pctrl_ops;
  413. pctrl_desc->pmxops = &axp20x_pmx_ops;
  414. pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
  415. if (IS_ERR(pctl->pctl_dev)) {
  416. dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
  417. return PTR_ERR(pctl->pctl_dev);
  418. }
  419. ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
  420. if (ret) {
  421. dev_err(&pdev->dev, "Failed to register GPIO chip\n");
  422. return ret;
  423. }
  424. ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
  425. pctl->desc->pins->number,
  426. pctl->desc->pins->number,
  427. pctl->desc->npins);
  428. if (ret) {
  429. dev_err(&pdev->dev, "failed to add pin range\n");
  430. return ret;
  431. }
  432. dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
  433. return 0;
  434. }
  435. static struct platform_driver axp20x_pctl_driver = {
  436. .probe = axp20x_pctl_probe,
  437. .driver = {
  438. .name = "axp20x-gpio",
  439. .of_match_table = axp20x_pctl_match,
  440. },
  441. };
  442. module_platform_driver(axp20x_pctl_driver);
  443. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  444. MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
  445. MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
  446. MODULE_LICENSE("GPL");