pinctrl-sprd.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Spreadtrum pin controller driver
  4. * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
  5. */
  6. #include <linux/debugfs.h>
  7. #include <linux/err.h>
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/slab.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/pinctrl/machine.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/pinctrl/pinconf.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinmux.h>
  22. #include "../core.h"
  23. #include "../pinmux.h"
  24. #include "../pinconf.h"
  25. #include "../pinctrl-utils.h"
  26. #include "pinctrl-sprd.h"
  27. #define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
  28. #define PINCTRL_REG_OFFSET 0x20
  29. #define PINCTRL_REG_MISC_OFFSET 0x4020
  30. #define PINCTRL_REG_LEN 0x4
  31. #define PIN_FUNC_MASK (BIT(4) | BIT(5))
  32. #define PIN_FUNC_SEL_1 ~PIN_FUNC_MASK
  33. #define PIN_FUNC_SEL_2 BIT(4)
  34. #define PIN_FUNC_SEL_3 BIT(5)
  35. #define PIN_FUNC_SEL_4 PIN_FUNC_MASK
  36. #define AP_SLEEP_MODE BIT(13)
  37. #define PUBCP_SLEEP_MODE BIT(14)
  38. #define TGLDSP_SLEEP_MODE BIT(15)
  39. #define AGDSP_SLEEP_MODE BIT(16)
  40. #define CM4_SLEEP_MODE BIT(17)
  41. #define SLEEP_MODE_MASK GENMASK(5, 0)
  42. #define SLEEP_MODE_SHIFT 13
  43. #define SLEEP_INPUT BIT(1)
  44. #define SLEEP_INPUT_MASK 0x1
  45. #define SLEEP_INPUT_SHIFT 1
  46. #define SLEEP_OUTPUT BIT(0)
  47. #define SLEEP_OUTPUT_MASK 0x1
  48. #define SLEEP_OUTPUT_SHIFT 0
  49. #define DRIVE_STRENGTH_MASK GENMASK(3, 0)
  50. #define DRIVE_STRENGTH_SHIFT 19
  51. #define SLEEP_PULL_DOWN BIT(2)
  52. #define SLEEP_PULL_DOWN_MASK 0x1
  53. #define SLEEP_PULL_DOWN_SHIFT 2
  54. #define PULL_DOWN BIT(6)
  55. #define PULL_DOWN_MASK 0x1
  56. #define PULL_DOWN_SHIFT 6
  57. #define SLEEP_PULL_UP BIT(3)
  58. #define SLEEP_PULL_UP_MASK 0x1
  59. #define SLEEP_PULL_UP_SHIFT 3
  60. #define PULL_UP_4_7K (BIT(12) | BIT(7))
  61. #define PULL_UP_20K BIT(7)
  62. #define PULL_UP_MASK 0x21
  63. #define PULL_UP_SHIFT 7
  64. #define INPUT_SCHMITT BIT(11)
  65. #define INPUT_SCHMITT_MASK 0x1
  66. #define INPUT_SCHMITT_SHIFT 11
  67. enum pin_sleep_mode {
  68. AP_SLEEP = BIT(0),
  69. PUBCP_SLEEP = BIT(1),
  70. TGLDSP_SLEEP = BIT(2),
  71. AGDSP_SLEEP = BIT(3),
  72. CM4_SLEEP = BIT(4),
  73. };
  74. enum pin_func_sel {
  75. PIN_FUNC_1,
  76. PIN_FUNC_2,
  77. PIN_FUNC_3,
  78. PIN_FUNC_4,
  79. PIN_FUNC_MAX,
  80. };
  81. /**
  82. * struct sprd_pin: represent one pin's description
  83. * @name: pin name
  84. * @number: pin number
  85. * @type: pin type, can be GLOBAL_CTRL_PIN/COMMON_PIN/MISC_PIN
  86. * @reg: pin register address
  87. * @bit_offset: bit offset in pin register
  88. * @bit_width: bit width in pin register
  89. */
  90. struct sprd_pin {
  91. const char *name;
  92. unsigned int number;
  93. enum pin_type type;
  94. unsigned long reg;
  95. unsigned long bit_offset;
  96. unsigned long bit_width;
  97. };
  98. /**
  99. * struct sprd_pin_group: represent one group's description
  100. * @name: group name
  101. * @npins: pin numbers of this group
  102. * @pins: pointer to pins array
  103. */
  104. struct sprd_pin_group {
  105. const char *name;
  106. unsigned int npins;
  107. unsigned int *pins;
  108. };
  109. /**
  110. * struct sprd_pinctrl_soc_info: represent the SoC's pins description
  111. * @groups: pointer to groups of pins
  112. * @ngroups: group numbers of the whole SoC
  113. * @pins: pointer to pins description
  114. * @npins: pin numbers of the whole SoC
  115. * @grp_names: pointer to group names array
  116. */
  117. struct sprd_pinctrl_soc_info {
  118. struct sprd_pin_group *groups;
  119. unsigned int ngroups;
  120. struct sprd_pin *pins;
  121. unsigned int npins;
  122. const char **grp_names;
  123. };
  124. /**
  125. * struct sprd_pinctrl: represent the pin controller device
  126. * @dev: pointer to the device structure
  127. * @pctl: pointer to the pinctrl handle
  128. * @base: base address of the controller
  129. * @info: pointer to SoC's pins description information
  130. */
  131. struct sprd_pinctrl {
  132. struct device *dev;
  133. struct pinctrl_dev *pctl;
  134. void __iomem *base;
  135. struct sprd_pinctrl_soc_info *info;
  136. };
  137. #define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
  138. #define SPRD_PIN_CONFIG_SLEEP_MODE (PIN_CONFIG_END + 2)
  139. static int sprd_pinctrl_get_id_by_name(struct sprd_pinctrl *sprd_pctl,
  140. const char *name)
  141. {
  142. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  143. int i;
  144. for (i = 0; i < info->npins; i++) {
  145. if (!strcmp(info->pins[i].name, name))
  146. return info->pins[i].number;
  147. }
  148. return -ENODEV;
  149. }
  150. static struct sprd_pin *
  151. sprd_pinctrl_get_pin_by_id(struct sprd_pinctrl *sprd_pctl, unsigned int id)
  152. {
  153. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  154. struct sprd_pin *pin = NULL;
  155. int i;
  156. for (i = 0; i < info->npins; i++) {
  157. if (info->pins[i].number == id) {
  158. pin = &info->pins[i];
  159. break;
  160. }
  161. }
  162. return pin;
  163. }
  164. static const struct sprd_pin_group *
  165. sprd_pinctrl_find_group_by_name(struct sprd_pinctrl *sprd_pctl,
  166. const char *name)
  167. {
  168. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  169. const struct sprd_pin_group *grp = NULL;
  170. int i;
  171. for (i = 0; i < info->ngroups; i++) {
  172. if (!strcmp(info->groups[i].name, name)) {
  173. grp = &info->groups[i];
  174. break;
  175. }
  176. }
  177. return grp;
  178. }
  179. static int sprd_pctrl_group_count(struct pinctrl_dev *pctldev)
  180. {
  181. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  182. struct sprd_pinctrl_soc_info *info = pctl->info;
  183. return info->ngroups;
  184. }
  185. static const char *sprd_pctrl_group_name(struct pinctrl_dev *pctldev,
  186. unsigned int selector)
  187. {
  188. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  189. struct sprd_pinctrl_soc_info *info = pctl->info;
  190. return info->groups[selector].name;
  191. }
  192. static int sprd_pctrl_group_pins(struct pinctrl_dev *pctldev,
  193. unsigned int selector,
  194. const unsigned int **pins,
  195. unsigned int *npins)
  196. {
  197. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  198. struct sprd_pinctrl_soc_info *info = pctl->info;
  199. if (selector >= info->ngroups)
  200. return -EINVAL;
  201. *pins = info->groups[selector].pins;
  202. *npins = info->groups[selector].npins;
  203. return 0;
  204. }
  205. static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
  206. struct device_node *np,
  207. struct pinctrl_map **map,
  208. unsigned int *num_maps)
  209. {
  210. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  211. const struct sprd_pin_group *grp;
  212. unsigned long *configs = NULL;
  213. unsigned int num_configs = 0;
  214. unsigned int reserved_maps = 0;
  215. unsigned int reserve = 0;
  216. const char *function;
  217. enum pinctrl_map_type type;
  218. int ret;
  219. grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
  220. if (!grp) {
  221. dev_err(pctl->dev, "unable to find group for node %s\n",
  222. of_node_full_name(np));
  223. return -EINVAL;
  224. }
  225. ret = of_property_count_strings(np, "pins");
  226. if (ret < 0)
  227. return ret;
  228. if (ret == 1)
  229. type = PIN_MAP_TYPE_CONFIGS_PIN;
  230. else
  231. type = PIN_MAP_TYPE_CONFIGS_GROUP;
  232. ret = of_property_read_string(np, "function", &function);
  233. if (ret < 0) {
  234. if (ret != -EINVAL)
  235. dev_err(pctl->dev,
  236. "%s: could not parse property function\n",
  237. of_node_full_name(np));
  238. function = NULL;
  239. }
  240. ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
  241. &num_configs);
  242. if (ret < 0) {
  243. dev_err(pctl->dev, "%s: could not parse node property\n",
  244. of_node_full_name(np));
  245. return ret;
  246. }
  247. *map = NULL;
  248. *num_maps = 0;
  249. if (function != NULL)
  250. reserve++;
  251. if (num_configs)
  252. reserve++;
  253. ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
  254. num_maps, reserve);
  255. if (ret < 0)
  256. goto out;
  257. if (function) {
  258. ret = pinctrl_utils_add_map_mux(pctldev, map,
  259. &reserved_maps, num_maps,
  260. grp->name, function);
  261. if (ret < 0)
  262. goto out;
  263. }
  264. if (num_configs) {
  265. const char *group_or_pin;
  266. unsigned int pin_id;
  267. if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
  268. pin_id = grp->pins[0];
  269. group_or_pin = pin_get_name(pctldev, pin_id);
  270. } else {
  271. group_or_pin = grp->name;
  272. }
  273. ret = pinctrl_utils_add_map_configs(pctldev, map,
  274. &reserved_maps, num_maps,
  275. group_or_pin, configs,
  276. num_configs, type);
  277. }
  278. out:
  279. kfree(configs);
  280. return ret;
  281. }
  282. static void sprd_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  283. unsigned int offset)
  284. {
  285. seq_printf(s, "%s", dev_name(pctldev->dev));
  286. }
  287. static const struct pinctrl_ops sprd_pctrl_ops = {
  288. .get_groups_count = sprd_pctrl_group_count,
  289. .get_group_name = sprd_pctrl_group_name,
  290. .get_group_pins = sprd_pctrl_group_pins,
  291. .pin_dbg_show = sprd_pctrl_dbg_show,
  292. .dt_node_to_map = sprd_dt_node_to_map,
  293. .dt_free_map = pinctrl_utils_free_map,
  294. };
  295. static int sprd_pmx_get_function_count(struct pinctrl_dev *pctldev)
  296. {
  297. return PIN_FUNC_MAX;
  298. }
  299. static const char *sprd_pmx_get_function_name(struct pinctrl_dev *pctldev,
  300. unsigned int selector)
  301. {
  302. switch (selector) {
  303. case PIN_FUNC_1:
  304. return "func1";
  305. case PIN_FUNC_2:
  306. return "func2";
  307. case PIN_FUNC_3:
  308. return "func3";
  309. case PIN_FUNC_4:
  310. return "func4";
  311. default:
  312. return "null";
  313. }
  314. }
  315. static int sprd_pmx_get_function_groups(struct pinctrl_dev *pctldev,
  316. unsigned int selector,
  317. const char * const **groups,
  318. unsigned int * const num_groups)
  319. {
  320. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  321. struct sprd_pinctrl_soc_info *info = pctl->info;
  322. *groups = info->grp_names;
  323. *num_groups = info->ngroups;
  324. return 0;
  325. }
  326. static int sprd_pmx_set_mux(struct pinctrl_dev *pctldev,
  327. unsigned int func_selector,
  328. unsigned int group_selector)
  329. {
  330. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  331. struct sprd_pinctrl_soc_info *info = pctl->info;
  332. struct sprd_pin_group *grp = &info->groups[group_selector];
  333. unsigned int i, grp_pins = grp->npins;
  334. unsigned long reg;
  335. unsigned int val = 0;
  336. if (group_selector >= info->ngroups)
  337. return -EINVAL;
  338. switch (func_selector) {
  339. case PIN_FUNC_1:
  340. val &= PIN_FUNC_SEL_1;
  341. break;
  342. case PIN_FUNC_2:
  343. val |= PIN_FUNC_SEL_2;
  344. break;
  345. case PIN_FUNC_3:
  346. val |= PIN_FUNC_SEL_3;
  347. break;
  348. case PIN_FUNC_4:
  349. val |= PIN_FUNC_SEL_4;
  350. break;
  351. default:
  352. break;
  353. }
  354. for (i = 0; i < grp_pins; i++) {
  355. unsigned int pin_id = grp->pins[i];
  356. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  357. if (!pin || pin->type != COMMON_PIN)
  358. continue;
  359. reg = readl((void __iomem *)pin->reg);
  360. reg &= ~PIN_FUNC_MASK;
  361. reg |= val;
  362. writel(reg, (void __iomem *)pin->reg);
  363. }
  364. return 0;
  365. }
  366. static const struct pinmux_ops sprd_pmx_ops = {
  367. .get_functions_count = sprd_pmx_get_function_count,
  368. .get_function_name = sprd_pmx_get_function_name,
  369. .get_function_groups = sprd_pmx_get_function_groups,
  370. .set_mux = sprd_pmx_set_mux,
  371. };
  372. static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
  373. unsigned long *config)
  374. {
  375. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  376. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  377. unsigned int param = pinconf_to_config_param(*config);
  378. unsigned int reg, arg;
  379. if (!pin)
  380. return -EINVAL;
  381. if (pin->type == GLOBAL_CTRL_PIN) {
  382. reg = (readl((void __iomem *)pin->reg) >>
  383. pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
  384. } else {
  385. reg = readl((void __iomem *)pin->reg);
  386. }
  387. if (pin->type == GLOBAL_CTRL_PIN &&
  388. param == SPRD_PIN_CONFIG_CONTROL) {
  389. arg = reg;
  390. } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
  391. switch (param) {
  392. case SPRD_PIN_CONFIG_SLEEP_MODE:
  393. arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK;
  394. break;
  395. case PIN_CONFIG_INPUT_ENABLE:
  396. arg = (reg >> SLEEP_INPUT_SHIFT) & SLEEP_INPUT_MASK;
  397. break;
  398. case PIN_CONFIG_OUTPUT_ENABLE:
  399. arg = reg & SLEEP_OUTPUT_MASK;
  400. break;
  401. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  402. if ((reg & SLEEP_OUTPUT) || (reg & SLEEP_INPUT))
  403. return -EINVAL;
  404. arg = 1;
  405. break;
  406. case PIN_CONFIG_DRIVE_STRENGTH:
  407. arg = (reg >> DRIVE_STRENGTH_SHIFT) &
  408. DRIVE_STRENGTH_MASK;
  409. break;
  410. case PIN_CONFIG_BIAS_PULL_DOWN:
  411. /* combine sleep pull down and pull down config */
  412. arg = ((reg >> SLEEP_PULL_DOWN_SHIFT) &
  413. SLEEP_PULL_DOWN_MASK) << 16;
  414. arg |= (reg >> PULL_DOWN_SHIFT) & PULL_DOWN_MASK;
  415. break;
  416. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  417. arg = (reg >> INPUT_SCHMITT_SHIFT) & INPUT_SCHMITT_MASK;
  418. break;
  419. case PIN_CONFIG_BIAS_PULL_UP:
  420. /* combine sleep pull up and pull up config */
  421. arg = ((reg >> SLEEP_PULL_UP_SHIFT) &
  422. SLEEP_PULL_UP_MASK) << 16;
  423. arg |= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
  424. break;
  425. case PIN_CONFIG_BIAS_DISABLE:
  426. if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
  427. (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
  428. return -EINVAL;
  429. arg = 1;
  430. break;
  431. case PIN_CONFIG_SLEEP_HARDWARE_STATE:
  432. arg = 0;
  433. break;
  434. default:
  435. return -ENOTSUPP;
  436. }
  437. } else {
  438. return -ENOTSUPP;
  439. }
  440. *config = pinconf_to_config_packed(param, arg);
  441. return 0;
  442. }
  443. static unsigned int sprd_pinconf_drive(unsigned int mA)
  444. {
  445. unsigned int val = 0;
  446. switch (mA) {
  447. case 2:
  448. break;
  449. case 4:
  450. val |= BIT(19);
  451. break;
  452. case 6:
  453. val |= BIT(20);
  454. break;
  455. case 8:
  456. val |= BIT(19) | BIT(20);
  457. break;
  458. case 10:
  459. val |= BIT(21);
  460. break;
  461. case 12:
  462. val |= BIT(21) | BIT(19);
  463. break;
  464. case 14:
  465. val |= BIT(21) | BIT(20);
  466. break;
  467. case 16:
  468. val |= BIT(19) | BIT(20) | BIT(21);
  469. break;
  470. case 20:
  471. val |= BIT(22);
  472. break;
  473. case 21:
  474. val |= BIT(22) | BIT(19);
  475. break;
  476. case 24:
  477. val |= BIT(22) | BIT(20);
  478. break;
  479. case 25:
  480. val |= BIT(22) | BIT(20) | BIT(19);
  481. break;
  482. case 27:
  483. val |= BIT(22) | BIT(21);
  484. break;
  485. case 29:
  486. val |= BIT(22) | BIT(21) | BIT(19);
  487. break;
  488. case 31:
  489. val |= BIT(22) | BIT(21) | BIT(20);
  490. break;
  491. case 33:
  492. val |= BIT(22) | BIT(21) | BIT(20) | BIT(19);
  493. break;
  494. default:
  495. break;
  496. }
  497. return val;
  498. }
  499. static bool sprd_pinctrl_check_sleep_config(unsigned long *configs,
  500. unsigned int num_configs)
  501. {
  502. unsigned int param;
  503. int i;
  504. for (i = 0; i < num_configs; i++) {
  505. param = pinconf_to_config_param(configs[i]);
  506. if (param == PIN_CONFIG_SLEEP_HARDWARE_STATE)
  507. return true;
  508. }
  509. return false;
  510. }
  511. static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
  512. unsigned long *configs, unsigned int num_configs)
  513. {
  514. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  515. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  516. bool is_sleep_config;
  517. unsigned long reg;
  518. int i;
  519. if (!pin)
  520. return -EINVAL;
  521. is_sleep_config = sprd_pinctrl_check_sleep_config(configs, num_configs);
  522. for (i = 0; i < num_configs; i++) {
  523. unsigned int param, arg, shift, mask, val;
  524. param = pinconf_to_config_param(configs[i]);
  525. arg = pinconf_to_config_argument(configs[i]);
  526. val = 0;
  527. shift = 0;
  528. mask = 0;
  529. if (pin->type == GLOBAL_CTRL_PIN &&
  530. param == SPRD_PIN_CONFIG_CONTROL) {
  531. val = arg;
  532. } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) {
  533. switch (param) {
  534. case SPRD_PIN_CONFIG_SLEEP_MODE:
  535. if (arg & AP_SLEEP)
  536. val |= AP_SLEEP_MODE;
  537. if (arg & PUBCP_SLEEP)
  538. val |= PUBCP_SLEEP_MODE;
  539. if (arg & TGLDSP_SLEEP)
  540. val |= TGLDSP_SLEEP_MODE;
  541. if (arg & AGDSP_SLEEP)
  542. val |= AGDSP_SLEEP_MODE;
  543. if (arg & CM4_SLEEP)
  544. val |= CM4_SLEEP_MODE;
  545. mask = SLEEP_MODE_MASK;
  546. shift = SLEEP_MODE_SHIFT;
  547. break;
  548. case PIN_CONFIG_INPUT_ENABLE:
  549. if (is_sleep_config == true) {
  550. if (arg > 0)
  551. val |= SLEEP_INPUT;
  552. else
  553. val &= ~SLEEP_INPUT;
  554. mask = SLEEP_INPUT_MASK;
  555. shift = SLEEP_INPUT_SHIFT;
  556. }
  557. break;
  558. case PIN_CONFIG_OUTPUT_ENABLE:
  559. if (is_sleep_config == true) {
  560. if (arg > 0)
  561. val |= SLEEP_OUTPUT;
  562. else
  563. val &= ~SLEEP_OUTPUT;
  564. mask = SLEEP_OUTPUT_MASK;
  565. shift = SLEEP_OUTPUT_SHIFT;
  566. }
  567. break;
  568. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  569. if (is_sleep_config == true) {
  570. val = shift = 0;
  571. mask = SLEEP_OUTPUT | SLEEP_INPUT;
  572. }
  573. break;
  574. case PIN_CONFIG_DRIVE_STRENGTH:
  575. if (arg < 2 || arg > 60)
  576. return -EINVAL;
  577. val = sprd_pinconf_drive(arg);
  578. mask = DRIVE_STRENGTH_MASK;
  579. shift = DRIVE_STRENGTH_SHIFT;
  580. break;
  581. case PIN_CONFIG_BIAS_PULL_DOWN:
  582. if (is_sleep_config == true) {
  583. val |= SLEEP_PULL_DOWN;
  584. mask = SLEEP_PULL_DOWN_MASK;
  585. shift = SLEEP_PULL_DOWN_SHIFT;
  586. } else {
  587. val |= PULL_DOWN;
  588. mask = PULL_DOWN_MASK;
  589. shift = PULL_DOWN_SHIFT;
  590. }
  591. break;
  592. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  593. if (arg > 0)
  594. val |= INPUT_SCHMITT;
  595. else
  596. val &= ~INPUT_SCHMITT;
  597. mask = INPUT_SCHMITT_MASK;
  598. shift = INPUT_SCHMITT_SHIFT;
  599. break;
  600. case PIN_CONFIG_BIAS_PULL_UP:
  601. if (is_sleep_config) {
  602. val |= SLEEP_PULL_UP;
  603. mask = SLEEP_PULL_UP_MASK;
  604. shift = SLEEP_PULL_UP_SHIFT;
  605. } else {
  606. if (arg == 20000)
  607. val |= PULL_UP_20K;
  608. else if (arg == 4700)
  609. val |= PULL_UP_4_7K;
  610. mask = PULL_UP_MASK;
  611. shift = PULL_UP_SHIFT;
  612. }
  613. break;
  614. case PIN_CONFIG_BIAS_DISABLE:
  615. if (is_sleep_config == true) {
  616. val = shift = 0;
  617. mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
  618. } else {
  619. val = shift = 0;
  620. mask = PULL_DOWN | PULL_UP_20K |
  621. PULL_UP_4_7K;
  622. }
  623. break;
  624. case PIN_CONFIG_SLEEP_HARDWARE_STATE:
  625. continue;
  626. default:
  627. return -ENOTSUPP;
  628. }
  629. } else {
  630. return -ENOTSUPP;
  631. }
  632. if (pin->type == GLOBAL_CTRL_PIN) {
  633. reg = readl((void __iomem *)pin->reg);
  634. reg &= ~(PINCTRL_BIT_MASK(pin->bit_width)
  635. << pin->bit_offset);
  636. reg |= (val & PINCTRL_BIT_MASK(pin->bit_width))
  637. << pin->bit_offset;
  638. writel(reg, (void __iomem *)pin->reg);
  639. } else {
  640. reg = readl((void __iomem *)pin->reg);
  641. reg &= ~(mask << shift);
  642. reg |= val;
  643. writel(reg, (void __iomem *)pin->reg);
  644. }
  645. }
  646. return 0;
  647. }
  648. static int sprd_pinconf_group_get(struct pinctrl_dev *pctldev,
  649. unsigned int selector, unsigned long *config)
  650. {
  651. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  652. struct sprd_pinctrl_soc_info *info = pctl->info;
  653. struct sprd_pin_group *grp;
  654. unsigned int pin_id;
  655. if (selector >= info->ngroups)
  656. return -EINVAL;
  657. grp = &info->groups[selector];
  658. pin_id = grp->pins[0];
  659. return sprd_pinconf_get(pctldev, pin_id, config);
  660. }
  661. static int sprd_pinconf_group_set(struct pinctrl_dev *pctldev,
  662. unsigned int selector,
  663. unsigned long *configs,
  664. unsigned int num_configs)
  665. {
  666. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  667. struct sprd_pinctrl_soc_info *info = pctl->info;
  668. struct sprd_pin_group *grp;
  669. int ret, i;
  670. if (selector >= info->ngroups)
  671. return -EINVAL;
  672. grp = &info->groups[selector];
  673. for (i = 0; i < grp->npins; i++) {
  674. unsigned int pin_id = grp->pins[i];
  675. ret = sprd_pinconf_set(pctldev, pin_id, configs, num_configs);
  676. if (ret)
  677. return ret;
  678. }
  679. return 0;
  680. }
  681. static int sprd_pinconf_get_config(struct pinctrl_dev *pctldev,
  682. unsigned int pin_id,
  683. unsigned long *config)
  684. {
  685. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  686. struct sprd_pin *pin = sprd_pinctrl_get_pin_by_id(pctl, pin_id);
  687. if (!pin)
  688. return -EINVAL;
  689. if (pin->type == GLOBAL_CTRL_PIN) {
  690. *config = (readl((void __iomem *)pin->reg) >>
  691. pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width);
  692. } else {
  693. *config = readl((void __iomem *)pin->reg);
  694. }
  695. return 0;
  696. }
  697. static void sprd_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  698. struct seq_file *s, unsigned int pin_id)
  699. {
  700. unsigned long config;
  701. int ret;
  702. ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
  703. if (ret)
  704. return;
  705. seq_printf(s, "0x%lx", config);
  706. }
  707. static void sprd_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
  708. struct seq_file *s,
  709. unsigned int selector)
  710. {
  711. struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  712. struct sprd_pinctrl_soc_info *info = pctl->info;
  713. struct sprd_pin_group *grp;
  714. unsigned long config;
  715. const char *name;
  716. int i, ret;
  717. if (selector >= info->ngroups)
  718. return;
  719. grp = &info->groups[selector];
  720. seq_putc(s, '\n');
  721. for (i = 0; i < grp->npins; i++, config++) {
  722. unsigned int pin_id = grp->pins[i];
  723. name = pin_get_name(pctldev, pin_id);
  724. ret = sprd_pinconf_get_config(pctldev, pin_id, &config);
  725. if (ret)
  726. return;
  727. seq_printf(s, "%s: 0x%lx ", name, config);
  728. }
  729. }
  730. static const struct pinconf_ops sprd_pinconf_ops = {
  731. .is_generic = true,
  732. .pin_config_get = sprd_pinconf_get,
  733. .pin_config_set = sprd_pinconf_set,
  734. .pin_config_group_get = sprd_pinconf_group_get,
  735. .pin_config_group_set = sprd_pinconf_group_set,
  736. .pin_config_dbg_show = sprd_pinconf_dbg_show,
  737. .pin_config_group_dbg_show = sprd_pinconf_group_dbg_show,
  738. };
  739. static const struct pinconf_generic_params sprd_dt_params[] = {
  740. {"sprd,control", SPRD_PIN_CONFIG_CONTROL, 0},
  741. {"sprd,sleep-mode", SPRD_PIN_CONFIG_SLEEP_MODE, 0},
  742. };
  743. #ifdef CONFIG_DEBUG_FS
  744. static const struct pin_config_item sprd_conf_items[] = {
  745. PCONFDUMP(SPRD_PIN_CONFIG_CONTROL, "global control", NULL, true),
  746. PCONFDUMP(SPRD_PIN_CONFIG_SLEEP_MODE, "sleep mode", NULL, true),
  747. };
  748. #endif
  749. static struct pinctrl_desc sprd_pinctrl_desc = {
  750. .pctlops = &sprd_pctrl_ops,
  751. .pmxops = &sprd_pmx_ops,
  752. .confops = &sprd_pinconf_ops,
  753. .num_custom_params = ARRAY_SIZE(sprd_dt_params),
  754. .custom_params = sprd_dt_params,
  755. #ifdef CONFIG_DEBUG_FS
  756. .custom_conf_items = sprd_conf_items,
  757. #endif
  758. .owner = THIS_MODULE,
  759. };
  760. static int sprd_pinctrl_parse_groups(struct device_node *np,
  761. struct sprd_pinctrl *sprd_pctl,
  762. struct sprd_pin_group *grp)
  763. {
  764. struct property *prop;
  765. const char *pin_name;
  766. int ret, i = 0;
  767. ret = of_property_count_strings(np, "pins");
  768. if (ret < 0)
  769. return ret;
  770. grp->name = np->name;
  771. grp->npins = ret;
  772. grp->pins = devm_kcalloc(sprd_pctl->dev,
  773. grp->npins, sizeof(unsigned int),
  774. GFP_KERNEL);
  775. if (!grp->pins)
  776. return -ENOMEM;
  777. of_property_for_each_string(np, "pins", prop, pin_name) {
  778. ret = sprd_pinctrl_get_id_by_name(sprd_pctl, pin_name);
  779. if (ret >= 0)
  780. grp->pins[i++] = ret;
  781. }
  782. for (i = 0; i < grp->npins; i++) {
  783. dev_dbg(sprd_pctl->dev,
  784. "Group[%s] contains [%d] pins: id = %d\n",
  785. grp->name, grp->npins, grp->pins[i]);
  786. }
  787. return 0;
  788. }
  789. static unsigned int sprd_pinctrl_get_groups(struct device_node *np)
  790. {
  791. struct device_node *child;
  792. unsigned int group_cnt, cnt;
  793. group_cnt = of_get_child_count(np);
  794. for_each_child_of_node(np, child) {
  795. cnt = of_get_child_count(child);
  796. if (cnt > 0)
  797. group_cnt += cnt;
  798. }
  799. return group_cnt;
  800. }
  801. static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl)
  802. {
  803. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  804. struct device_node *np = sprd_pctl->dev->of_node;
  805. struct sprd_pin_group *grp;
  806. const char **temp;
  807. int ret;
  808. if (!np)
  809. return -ENODEV;
  810. info->ngroups = sprd_pinctrl_get_groups(np);
  811. if (!info->ngroups)
  812. return 0;
  813. info->groups = devm_kcalloc(sprd_pctl->dev,
  814. info->ngroups,
  815. sizeof(struct sprd_pin_group),
  816. GFP_KERNEL);
  817. if (!info->groups)
  818. return -ENOMEM;
  819. info->grp_names = devm_kcalloc(sprd_pctl->dev,
  820. info->ngroups, sizeof(char *),
  821. GFP_KERNEL);
  822. if (!info->grp_names)
  823. return -ENOMEM;
  824. temp = info->grp_names;
  825. grp = info->groups;
  826. for_each_child_of_node_scoped(np, child) {
  827. ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp);
  828. if (ret)
  829. return ret;
  830. *temp++ = grp->name;
  831. grp++;
  832. if (of_get_child_count(child) > 0) {
  833. for_each_child_of_node_scoped(child, sub_child) {
  834. ret = sprd_pinctrl_parse_groups(sub_child,
  835. sprd_pctl, grp);
  836. if (ret)
  837. return ret;
  838. *temp++ = grp->name;
  839. grp++;
  840. }
  841. }
  842. }
  843. return 0;
  844. }
  845. static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
  846. struct sprd_pins_info *sprd_soc_pin_info,
  847. int pins_cnt)
  848. {
  849. struct sprd_pinctrl_soc_info *info = sprd_pctl->info;
  850. unsigned int ctrl_pin = 0, com_pin = 0;
  851. struct sprd_pin *pin;
  852. int i;
  853. info->npins = pins_cnt;
  854. info->pins = devm_kcalloc(sprd_pctl->dev,
  855. info->npins, sizeof(struct sprd_pin),
  856. GFP_KERNEL);
  857. if (!info->pins)
  858. return -ENOMEM;
  859. for (i = 0, pin = info->pins; i < info->npins; i++, pin++) {
  860. unsigned int reg;
  861. pin->name = sprd_soc_pin_info[i].name;
  862. pin->type = sprd_soc_pin_info[i].type;
  863. pin->number = sprd_soc_pin_info[i].num;
  864. reg = sprd_soc_pin_info[i].reg;
  865. if (pin->type == GLOBAL_CTRL_PIN) {
  866. pin->reg = (unsigned long)sprd_pctl->base +
  867. PINCTRL_REG_LEN * reg;
  868. pin->bit_offset = sprd_soc_pin_info[i].bit_offset;
  869. pin->bit_width = sprd_soc_pin_info[i].bit_width;
  870. ctrl_pin++;
  871. } else if (pin->type == COMMON_PIN) {
  872. pin->reg = (unsigned long)sprd_pctl->base +
  873. PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
  874. (i - ctrl_pin);
  875. com_pin++;
  876. } else if (pin->type == MISC_PIN) {
  877. pin->reg = (unsigned long)sprd_pctl->base +
  878. PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
  879. (i - ctrl_pin - com_pin);
  880. }
  881. }
  882. for (i = 0, pin = info->pins; i < info->npins; pin++, i++) {
  883. dev_dbg(sprd_pctl->dev, "pin name[%s-%d], type = %d, "
  884. "bit offset = %ld, bit width = %ld, reg = 0x%lx\n",
  885. pin->name, pin->number, pin->type,
  886. pin->bit_offset, pin->bit_width, pin->reg);
  887. }
  888. return 0;
  889. }
  890. int sprd_pinctrl_core_probe(struct platform_device *pdev,
  891. struct sprd_pins_info *sprd_soc_pin_info,
  892. int pins_cnt)
  893. {
  894. struct sprd_pinctrl *sprd_pctl;
  895. struct sprd_pinctrl_soc_info *pinctrl_info;
  896. struct pinctrl_pin_desc *pin_desc;
  897. int ret, i;
  898. sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl),
  899. GFP_KERNEL);
  900. if (!sprd_pctl)
  901. return -ENOMEM;
  902. sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0);
  903. if (IS_ERR(sprd_pctl->base))
  904. return PTR_ERR(sprd_pctl->base);
  905. pinctrl_info = devm_kzalloc(&pdev->dev,
  906. sizeof(struct sprd_pinctrl_soc_info),
  907. GFP_KERNEL);
  908. if (!pinctrl_info)
  909. return -ENOMEM;
  910. sprd_pctl->info = pinctrl_info;
  911. sprd_pctl->dev = &pdev->dev;
  912. platform_set_drvdata(pdev, sprd_pctl);
  913. ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
  914. if (ret) {
  915. dev_err(&pdev->dev, "fail to add pins information\n");
  916. return ret;
  917. }
  918. ret = sprd_pinctrl_parse_dt(sprd_pctl);
  919. if (ret) {
  920. dev_err(&pdev->dev, "fail to parse dt properties\n");
  921. return ret;
  922. }
  923. pin_desc = devm_kcalloc(&pdev->dev,
  924. pinctrl_info->npins,
  925. sizeof(struct pinctrl_pin_desc),
  926. GFP_KERNEL);
  927. if (!pin_desc)
  928. return -ENOMEM;
  929. for (i = 0; i < pinctrl_info->npins; i++) {
  930. pin_desc[i].number = pinctrl_info->pins[i].number;
  931. pin_desc[i].name = pinctrl_info->pins[i].name;
  932. pin_desc[i].drv_data = pinctrl_info;
  933. }
  934. sprd_pinctrl_desc.pins = pin_desc;
  935. sprd_pinctrl_desc.name = dev_name(&pdev->dev);
  936. sprd_pinctrl_desc.npins = pinctrl_info->npins;
  937. sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
  938. &pdev->dev, (void *)sprd_pctl);
  939. if (IS_ERR(sprd_pctl->pctl)) {
  940. dev_err(&pdev->dev, "could not register pinctrl driver\n");
  941. return PTR_ERR(sprd_pctl->pctl);
  942. }
  943. return 0;
  944. }
  945. EXPORT_SYMBOL_GPL(sprd_pinctrl_core_probe);
  946. void sprd_pinctrl_remove(struct platform_device *pdev)
  947. {
  948. struct sprd_pinctrl *sprd_pctl = platform_get_drvdata(pdev);
  949. pinctrl_unregister(sprd_pctl->pctl);
  950. }
  951. EXPORT_SYMBOL_GPL(sprd_pinctrl_remove);
  952. void sprd_pinctrl_shutdown(struct platform_device *pdev)
  953. {
  954. struct pinctrl *pinctl;
  955. struct pinctrl_state *state;
  956. pinctl = devm_pinctrl_get(&pdev->dev);
  957. if (IS_ERR(pinctl))
  958. return;
  959. state = pinctrl_lookup_state(pinctl, "shutdown");
  960. if (IS_ERR(state))
  961. return;
  962. pinctrl_select_state(pinctl, state);
  963. }
  964. EXPORT_SYMBOL_GPL(sprd_pinctrl_shutdown);
  965. MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
  966. MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
  967. MODULE_LICENSE("GPL v2");