s5m8767.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Copyright (c) 2011 Samsung Electronics Co., Ltd
  4. // http://www.samsung.com
  5. #include <linux/cleanup.h>
  6. #include <linux/err.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/gpio/consumer.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regulator/driver.h>
  12. #include <linux/regulator/machine.h>
  13. #include <linux/mfd/samsung/core.h>
  14. #include <linux/mfd/samsung/s5m8767.h>
  15. #include <linux/regulator/of_regulator.h>
  16. #include <linux/regmap.h>
  17. #define S5M8767_OPMODE_NORMAL_MODE 0x1
  18. struct s5m8767_info {
  19. struct device *dev;
  20. struct sec_pmic_dev *iodev;
  21. int num_regulators;
  22. struct sec_opmode_data *opmode;
  23. int ramp_delay;
  24. bool buck2_ramp;
  25. bool buck3_ramp;
  26. bool buck4_ramp;
  27. bool buck2_gpiodvs;
  28. bool buck3_gpiodvs;
  29. bool buck4_gpiodvs;
  30. u8 buck2_vol[8];
  31. u8 buck3_vol[8];
  32. u8 buck4_vol[8];
  33. int buck_gpios[3];
  34. int buck_ds[3];
  35. int buck_gpioindex;
  36. };
  37. struct sec_voltage_desc {
  38. int max;
  39. int min;
  40. int step;
  41. };
  42. static const struct sec_voltage_desc buck_voltage_val1 = {
  43. .max = 2225000,
  44. .min = 650000,
  45. .step = 6250,
  46. };
  47. static const struct sec_voltage_desc buck_voltage_val2 = {
  48. .max = 1600000,
  49. .min = 600000,
  50. .step = 6250,
  51. };
  52. static const struct sec_voltage_desc buck_voltage_val3 = {
  53. .max = 3000000,
  54. .min = 750000,
  55. .step = 12500,
  56. };
  57. static const struct sec_voltage_desc ldo_voltage_val1 = {
  58. .max = 3950000,
  59. .min = 800000,
  60. .step = 50000,
  61. };
  62. static const struct sec_voltage_desc ldo_voltage_val2 = {
  63. .max = 2375000,
  64. .min = 800000,
  65. .step = 25000,
  66. };
  67. static const struct sec_voltage_desc *reg_voltage_map[] = {
  68. [S5M8767_LDO1] = &ldo_voltage_val2,
  69. [S5M8767_LDO2] = &ldo_voltage_val2,
  70. [S5M8767_LDO3] = &ldo_voltage_val1,
  71. [S5M8767_LDO4] = &ldo_voltage_val1,
  72. [S5M8767_LDO5] = &ldo_voltage_val1,
  73. [S5M8767_LDO6] = &ldo_voltage_val2,
  74. [S5M8767_LDO7] = &ldo_voltage_val2,
  75. [S5M8767_LDO8] = &ldo_voltage_val2,
  76. [S5M8767_LDO9] = &ldo_voltage_val1,
  77. [S5M8767_LDO10] = &ldo_voltage_val1,
  78. [S5M8767_LDO11] = &ldo_voltage_val1,
  79. [S5M8767_LDO12] = &ldo_voltage_val1,
  80. [S5M8767_LDO13] = &ldo_voltage_val1,
  81. [S5M8767_LDO14] = &ldo_voltage_val1,
  82. [S5M8767_LDO15] = &ldo_voltage_val2,
  83. [S5M8767_LDO16] = &ldo_voltage_val1,
  84. [S5M8767_LDO17] = &ldo_voltage_val1,
  85. [S5M8767_LDO18] = &ldo_voltage_val1,
  86. [S5M8767_LDO19] = &ldo_voltage_val1,
  87. [S5M8767_LDO20] = &ldo_voltage_val1,
  88. [S5M8767_LDO21] = &ldo_voltage_val1,
  89. [S5M8767_LDO22] = &ldo_voltage_val1,
  90. [S5M8767_LDO23] = &ldo_voltage_val1,
  91. [S5M8767_LDO24] = &ldo_voltage_val1,
  92. [S5M8767_LDO25] = &ldo_voltage_val1,
  93. [S5M8767_LDO26] = &ldo_voltage_val1,
  94. [S5M8767_LDO27] = &ldo_voltage_val1,
  95. [S5M8767_LDO28] = &ldo_voltage_val1,
  96. [S5M8767_BUCK1] = &buck_voltage_val1,
  97. [S5M8767_BUCK2] = &buck_voltage_val2,
  98. [S5M8767_BUCK3] = &buck_voltage_val2,
  99. [S5M8767_BUCK4] = &buck_voltage_val2,
  100. [S5M8767_BUCK5] = &buck_voltage_val1,
  101. [S5M8767_BUCK6] = &buck_voltage_val1,
  102. [S5M8767_BUCK7] = &buck_voltage_val3,
  103. [S5M8767_BUCK8] = &buck_voltage_val3,
  104. [S5M8767_BUCK9] = &buck_voltage_val3,
  105. };
  106. static const unsigned int s5m8767_opmode_reg[][4] = {
  107. /* {OFF, ON, LOWPOWER, SUSPEND} */
  108. /* LDO1 ... LDO28 */
  109. {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
  110. {0x0, 0x3, 0x2, 0x1},
  111. {0x0, 0x3, 0x2, 0x1},
  112. {0x0, 0x0, 0x0, 0x0},
  113. {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
  114. {0x0, 0x3, 0x2, 0x1},
  115. {0x0, 0x3, 0x2, 0x1},
  116. {0x0, 0x3, 0x2, 0x1},
  117. {0x0, 0x3, 0x2, 0x1},
  118. {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
  119. {0x0, 0x3, 0x2, 0x1},
  120. {0x0, 0x3, 0x2, 0x1},
  121. {0x0, 0x3, 0x2, 0x1},
  122. {0x0, 0x3, 0x2, 0x1},
  123. {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
  124. {0x0, 0x3, 0x2, 0x1},
  125. {0x0, 0x3, 0x2, 0x1},
  126. {0x0, 0x0, 0x0, 0x0},
  127. {0x0, 0x3, 0x2, 0x1},
  128. {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
  129. {0x0, 0x3, 0x2, 0x1},
  130. {0x0, 0x3, 0x2, 0x1},
  131. {0x0, 0x0, 0x0, 0x0},
  132. {0x0, 0x3, 0x2, 0x1},
  133. {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
  134. {0x0, 0x3, 0x2, 0x1},
  135. {0x0, 0x3, 0x2, 0x1},
  136. {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
  137. /* BUCK1 ... BUCK9 */
  138. {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
  139. {0x0, 0x3, 0x1, 0x1},
  140. {0x0, 0x3, 0x1, 0x1},
  141. {0x0, 0x3, 0x1, 0x1},
  142. {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
  143. {0x0, 0x3, 0x1, 0x1},
  144. {0x0, 0x3, 0x1, 0x1},
  145. {0x0, 0x3, 0x1, 0x1},
  146. {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
  147. };
  148. static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
  149. int *reg, int *enable_ctrl)
  150. {
  151. int i;
  152. unsigned int mode;
  153. switch (reg_id) {
  154. case S5M8767_LDO1 ... S5M8767_LDO2:
  155. *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  156. break;
  157. case S5M8767_LDO3 ... S5M8767_LDO28:
  158. *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  159. break;
  160. case S5M8767_BUCK1:
  161. *reg = S5M8767_REG_BUCK1CTRL1;
  162. break;
  163. case S5M8767_BUCK2 ... S5M8767_BUCK4:
  164. *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
  165. break;
  166. case S5M8767_BUCK5:
  167. *reg = S5M8767_REG_BUCK5CTRL1;
  168. break;
  169. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  170. *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
  171. break;
  172. default:
  173. return -EINVAL;
  174. }
  175. for (i = 0; i < s5m8767->num_regulators; i++) {
  176. if (s5m8767->opmode[i].id == reg_id) {
  177. mode = s5m8767->opmode[i].mode;
  178. break;
  179. }
  180. }
  181. if (i >= s5m8767->num_regulators)
  182. return -EINVAL;
  183. *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
  184. return 0;
  185. }
  186. static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
  187. {
  188. int reg;
  189. switch (reg_id) {
  190. case S5M8767_LDO1 ... S5M8767_LDO2:
  191. reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  192. break;
  193. case S5M8767_LDO3 ... S5M8767_LDO28:
  194. reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  195. break;
  196. case S5M8767_BUCK1:
  197. reg = S5M8767_REG_BUCK1CTRL2;
  198. break;
  199. case S5M8767_BUCK2:
  200. reg = S5M8767_REG_BUCK2DVS1;
  201. if (s5m8767->buck2_gpiodvs)
  202. reg += s5m8767->buck_gpioindex;
  203. break;
  204. case S5M8767_BUCK3:
  205. reg = S5M8767_REG_BUCK3DVS1;
  206. if (s5m8767->buck3_gpiodvs)
  207. reg += s5m8767->buck_gpioindex;
  208. break;
  209. case S5M8767_BUCK4:
  210. reg = S5M8767_REG_BUCK4DVS1;
  211. if (s5m8767->buck4_gpiodvs)
  212. reg += s5m8767->buck_gpioindex;
  213. break;
  214. case S5M8767_BUCK5:
  215. reg = S5M8767_REG_BUCK5CTRL2;
  216. break;
  217. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  218. reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
  219. break;
  220. default:
  221. return -EINVAL;
  222. }
  223. return reg;
  224. }
  225. static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
  226. int min_vol)
  227. {
  228. int selector = 0;
  229. if (desc == NULL)
  230. return -EINVAL;
  231. if (min_vol > desc->max)
  232. return -EINVAL;
  233. if (min_vol < desc->min)
  234. min_vol = desc->min;
  235. selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
  236. if (desc->min + desc->step * selector > desc->max)
  237. return -EINVAL;
  238. return selector;
  239. }
  240. static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
  241. {
  242. int temp_index = s5m8767->buck_gpioindex;
  243. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  244. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  245. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  246. return 0;
  247. }
  248. static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
  249. {
  250. int temp_index = s5m8767->buck_gpioindex;
  251. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  252. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  253. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  254. return 0;
  255. }
  256. static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
  257. unsigned selector)
  258. {
  259. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  260. int reg_id = rdev_get_id(rdev);
  261. int old_index, index = 0;
  262. u8 *buck234_vol = NULL;
  263. switch (reg_id) {
  264. case S5M8767_LDO1 ... S5M8767_LDO28:
  265. break;
  266. case S5M8767_BUCK1 ... S5M8767_BUCK6:
  267. if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
  268. buck234_vol = &s5m8767->buck2_vol[0];
  269. else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
  270. buck234_vol = &s5m8767->buck3_vol[0];
  271. else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
  272. buck234_vol = &s5m8767->buck4_vol[0];
  273. break;
  274. case S5M8767_BUCK7 ... S5M8767_BUCK8:
  275. return -EINVAL;
  276. case S5M8767_BUCK9:
  277. break;
  278. default:
  279. return -EINVAL;
  280. }
  281. /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
  282. if (buck234_vol) {
  283. while (*buck234_vol != selector) {
  284. buck234_vol++;
  285. index++;
  286. }
  287. old_index = s5m8767->buck_gpioindex;
  288. s5m8767->buck_gpioindex = index;
  289. if (index > old_index)
  290. return s5m8767_set_high(s5m8767);
  291. else
  292. return s5m8767_set_low(s5m8767);
  293. } else {
  294. return regulator_set_voltage_sel_regmap(rdev, selector);
  295. }
  296. }
  297. static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
  298. unsigned int old_sel,
  299. unsigned int new_sel)
  300. {
  301. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  302. if ((old_sel < new_sel) && s5m8767->ramp_delay)
  303. return DIV_ROUND_UP(rdev->desc->uV_step * (new_sel - old_sel),
  304. s5m8767->ramp_delay * 1000);
  305. return 0;
  306. }
  307. static const struct regulator_ops s5m8767_ops = {
  308. .list_voltage = regulator_list_voltage_linear,
  309. .is_enabled = regulator_is_enabled_regmap,
  310. .enable = regulator_enable_regmap,
  311. .disable = regulator_disable_regmap,
  312. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  313. .set_voltage_sel = s5m8767_set_voltage_sel,
  314. .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
  315. };
  316. static const struct regulator_ops s5m8767_buck78_ops = {
  317. .list_voltage = regulator_list_voltage_linear,
  318. .is_enabled = regulator_is_enabled_regmap,
  319. .enable = regulator_enable_regmap,
  320. .disable = regulator_disable_regmap,
  321. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  322. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  323. };
  324. #define s5m8767_regulator_desc(_name) { \
  325. .name = #_name, \
  326. .id = S5M8767_##_name, \
  327. .ops = &s5m8767_ops, \
  328. .type = REGULATOR_VOLTAGE, \
  329. .owner = THIS_MODULE, \
  330. }
  331. #define s5m8767_regulator_buck78_desc(_name) { \
  332. .name = #_name, \
  333. .id = S5M8767_##_name, \
  334. .ops = &s5m8767_buck78_ops, \
  335. .type = REGULATOR_VOLTAGE, \
  336. .owner = THIS_MODULE, \
  337. }
  338. static struct regulator_desc regulators[] = {
  339. s5m8767_regulator_desc(LDO1),
  340. s5m8767_regulator_desc(LDO2),
  341. s5m8767_regulator_desc(LDO3),
  342. s5m8767_regulator_desc(LDO4),
  343. s5m8767_regulator_desc(LDO5),
  344. s5m8767_regulator_desc(LDO6),
  345. s5m8767_regulator_desc(LDO7),
  346. s5m8767_regulator_desc(LDO8),
  347. s5m8767_regulator_desc(LDO9),
  348. s5m8767_regulator_desc(LDO10),
  349. s5m8767_regulator_desc(LDO11),
  350. s5m8767_regulator_desc(LDO12),
  351. s5m8767_regulator_desc(LDO13),
  352. s5m8767_regulator_desc(LDO14),
  353. s5m8767_regulator_desc(LDO15),
  354. s5m8767_regulator_desc(LDO16),
  355. s5m8767_regulator_desc(LDO17),
  356. s5m8767_regulator_desc(LDO18),
  357. s5m8767_regulator_desc(LDO19),
  358. s5m8767_regulator_desc(LDO20),
  359. s5m8767_regulator_desc(LDO21),
  360. s5m8767_regulator_desc(LDO22),
  361. s5m8767_regulator_desc(LDO23),
  362. s5m8767_regulator_desc(LDO24),
  363. s5m8767_regulator_desc(LDO25),
  364. s5m8767_regulator_desc(LDO26),
  365. s5m8767_regulator_desc(LDO27),
  366. s5m8767_regulator_desc(LDO28),
  367. s5m8767_regulator_desc(BUCK1),
  368. s5m8767_regulator_desc(BUCK2),
  369. s5m8767_regulator_desc(BUCK3),
  370. s5m8767_regulator_desc(BUCK4),
  371. s5m8767_regulator_desc(BUCK5),
  372. s5m8767_regulator_desc(BUCK6),
  373. s5m8767_regulator_buck78_desc(BUCK7),
  374. s5m8767_regulator_buck78_desc(BUCK8),
  375. s5m8767_regulator_desc(BUCK9),
  376. };
  377. /*
  378. * Enable GPIO control over BUCK9 in regulator_config for that regulator.
  379. */
  380. static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
  381. struct sec_regulator_data *rdata,
  382. struct regulator_config *config)
  383. {
  384. int i, mode = 0;
  385. if (rdata->id != S5M8767_BUCK9)
  386. return;
  387. /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
  388. for (i = 0; i < s5m8767->num_regulators; i++) {
  389. const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
  390. if (opmode->id == rdata->id) {
  391. mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
  392. break;
  393. }
  394. }
  395. if (mode != S5M8767_ENCTRL_USE_GPIO) {
  396. dev_warn(s5m8767->dev,
  397. "ext-control for %pOFn: mismatched op_mode (%x), ignoring\n",
  398. rdata->reg_node, mode);
  399. return;
  400. }
  401. if (!rdata->ext_control_gpiod) {
  402. dev_warn(s5m8767->dev,
  403. "ext-control for %pOFn: GPIO not valid, ignoring\n",
  404. rdata->reg_node);
  405. return;
  406. }
  407. config->ena_gpiod = rdata->ext_control_gpiod;
  408. }
  409. /*
  410. * Turn on GPIO control over BUCK9.
  411. */
  412. static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
  413. struct regulator_dev *rdev)
  414. {
  415. int id = rdev_get_id(rdev);
  416. int ret, reg, enable_ctrl;
  417. if (id != S5M8767_BUCK9)
  418. return -EINVAL;
  419. ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
  420. if (ret)
  421. return ret;
  422. return regmap_update_bits(s5m8767->iodev->regmap_pmic,
  423. reg, S5M8767_ENCTRL_MASK,
  424. S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
  425. }
  426. #ifdef CONFIG_OF
  427. static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
  428. struct sec_platform_data *pdata,
  429. struct device_node *pmic_np)
  430. {
  431. int i, gpio;
  432. for (i = 0; i < 3; i++) {
  433. gpio = of_get_named_gpio(pmic_np,
  434. "s5m8767,pmic-buck-dvs-gpios", i);
  435. if (!gpio_is_valid(gpio)) {
  436. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  437. return -EINVAL;
  438. }
  439. pdata->buck_gpios[i] = gpio;
  440. }
  441. return 0;
  442. }
  443. static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
  444. struct sec_platform_data *pdata,
  445. struct device_node *pmic_np)
  446. {
  447. int i, gpio;
  448. for (i = 0; i < 3; i++) {
  449. gpio = of_get_named_gpio(pmic_np,
  450. "s5m8767,pmic-buck-ds-gpios", i);
  451. if (!gpio_is_valid(gpio)) {
  452. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  453. return -EINVAL;
  454. }
  455. pdata->buck_ds[i] = gpio;
  456. }
  457. return 0;
  458. }
  459. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  460. struct sec_platform_data *pdata)
  461. {
  462. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  463. struct device_node *pmic_np, *reg_np;
  464. struct sec_regulator_data *rdata;
  465. struct sec_opmode_data *rmode;
  466. unsigned int i, dvs_voltage_nr = 8, ret;
  467. pmic_np = iodev->dev->of_node;
  468. if (!pmic_np) {
  469. dev_err(iodev->dev, "could not find pmic sub-node\n");
  470. return -ENODEV;
  471. }
  472. struct device_node *regulators_np __free(device_node) = of_get_child_by_name(pmic_np,
  473. "regulators");
  474. if (!regulators_np) {
  475. dev_err(iodev->dev, "could not find regulators sub-node\n");
  476. return -EINVAL;
  477. }
  478. /* count the number of regulators to be supported in pmic */
  479. pdata->num_regulators = of_get_child_count(regulators_np);
  480. rdata = devm_kcalloc(&pdev->dev,
  481. pdata->num_regulators, sizeof(*rdata),
  482. GFP_KERNEL);
  483. if (!rdata)
  484. return -ENOMEM;
  485. rmode = devm_kcalloc(&pdev->dev,
  486. pdata->num_regulators, sizeof(*rmode),
  487. GFP_KERNEL);
  488. if (!rmode)
  489. return -ENOMEM;
  490. pdata->regulators = rdata;
  491. pdata->opmode = rmode;
  492. for_each_child_of_node(regulators_np, reg_np) {
  493. for (i = 0; i < ARRAY_SIZE(regulators); i++)
  494. if (of_node_name_eq(reg_np, regulators[i].name))
  495. break;
  496. if (i == ARRAY_SIZE(regulators)) {
  497. dev_warn(iodev->dev,
  498. "don't know how to configure regulator %pOFn\n",
  499. reg_np);
  500. continue;
  501. }
  502. rdata->ext_control_gpiod = devm_fwnode_gpiod_get(
  503. &pdev->dev,
  504. of_fwnode_handle(reg_np),
  505. "s5m8767,pmic-ext-control",
  506. GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
  507. "s5m8767");
  508. if (PTR_ERR(rdata->ext_control_gpiod) == -ENOENT) {
  509. rdata->ext_control_gpiod = NULL;
  510. } else if (IS_ERR(rdata->ext_control_gpiod)) {
  511. of_node_put(reg_np);
  512. return PTR_ERR(rdata->ext_control_gpiod);
  513. }
  514. rdata->id = i;
  515. rdata->initdata = of_get_regulator_init_data(
  516. &pdev->dev, reg_np,
  517. &regulators[i]);
  518. rdata->reg_node = reg_np;
  519. rdata++;
  520. rmode->id = i;
  521. if (of_property_read_u32(reg_np, "op_mode",
  522. &rmode->mode)) {
  523. dev_warn(iodev->dev,
  524. "no op_mode property at %pOF\n",
  525. reg_np);
  526. rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
  527. }
  528. rmode++;
  529. }
  530. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs")) {
  531. pdata->buck2_gpiodvs = true;
  532. if (of_property_read_u32_array(pmic_np,
  533. "s5m8767,pmic-buck2-dvs-voltage",
  534. pdata->buck2_voltage, dvs_voltage_nr)) {
  535. dev_err(iodev->dev, "buck2 voltages not specified\n");
  536. return -EINVAL;
  537. }
  538. }
  539. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs")) {
  540. pdata->buck3_gpiodvs = true;
  541. if (of_property_read_u32_array(pmic_np,
  542. "s5m8767,pmic-buck3-dvs-voltage",
  543. pdata->buck3_voltage, dvs_voltage_nr)) {
  544. dev_err(iodev->dev, "buck3 voltages not specified\n");
  545. return -EINVAL;
  546. }
  547. }
  548. if (of_property_read_bool(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs")) {
  549. pdata->buck4_gpiodvs = true;
  550. if (of_property_read_u32_array(pmic_np,
  551. "s5m8767,pmic-buck4-dvs-voltage",
  552. pdata->buck4_voltage, dvs_voltage_nr)) {
  553. dev_err(iodev->dev, "buck4 voltages not specified\n");
  554. return -EINVAL;
  555. }
  556. }
  557. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  558. pdata->buck4_gpiodvs) {
  559. ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
  560. if (ret)
  561. return -EINVAL;
  562. if (of_property_read_u32(pmic_np,
  563. "s5m8767,pmic-buck-default-dvs-idx",
  564. &pdata->buck_default_idx)) {
  565. pdata->buck_default_idx = 0;
  566. } else {
  567. if (pdata->buck_default_idx >= 8) {
  568. pdata->buck_default_idx = 0;
  569. dev_info(iodev->dev,
  570. "invalid value for default dvs index, use 0\n");
  571. }
  572. }
  573. }
  574. ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
  575. if (ret)
  576. return -EINVAL;
  577. pdata->buck2_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck2-ramp-enable");
  578. pdata->buck3_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck3-ramp-enable");
  579. pdata->buck4_ramp_enable = of_property_read_bool(pmic_np, "s5m8767,pmic-buck4-ramp-enable");
  580. if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
  581. || pdata->buck4_ramp_enable) {
  582. if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
  583. &pdata->buck_ramp_delay))
  584. pdata->buck_ramp_delay = 0;
  585. }
  586. return 0;
  587. }
  588. #else
  589. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  590. struct sec_platform_data *pdata)
  591. {
  592. return 0;
  593. }
  594. #endif /* CONFIG_OF */
  595. static int s5m8767_pmic_probe(struct platform_device *pdev)
  596. {
  597. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  598. struct sec_platform_data *pdata = iodev->pdata;
  599. struct regulator_config config = { };
  600. struct s5m8767_info *s5m8767;
  601. int i, ret, buck_init;
  602. if (!pdata) {
  603. dev_err(pdev->dev.parent, "Platform data not supplied\n");
  604. return -ENODEV;
  605. }
  606. if (iodev->dev->of_node) {
  607. ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
  608. if (ret)
  609. return ret;
  610. }
  611. if (pdata->buck2_gpiodvs) {
  612. if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
  613. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  614. return -EINVAL;
  615. }
  616. }
  617. if (pdata->buck3_gpiodvs) {
  618. if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
  619. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  620. return -EINVAL;
  621. }
  622. }
  623. if (pdata->buck4_gpiodvs) {
  624. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
  625. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  626. return -EINVAL;
  627. }
  628. }
  629. s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
  630. GFP_KERNEL);
  631. if (!s5m8767)
  632. return -ENOMEM;
  633. s5m8767->dev = &pdev->dev;
  634. s5m8767->iodev = iodev;
  635. s5m8767->num_regulators = pdata->num_regulators;
  636. platform_set_drvdata(pdev, s5m8767);
  637. s5m8767->buck_gpioindex = pdata->buck_default_idx;
  638. s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
  639. s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
  640. s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
  641. s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
  642. s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
  643. s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
  644. s5m8767->buck_ds[0] = pdata->buck_ds[0];
  645. s5m8767->buck_ds[1] = pdata->buck_ds[1];
  646. s5m8767->buck_ds[2] = pdata->buck_ds[2];
  647. s5m8767->ramp_delay = pdata->buck_ramp_delay;
  648. s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
  649. s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
  650. s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
  651. s5m8767->opmode = pdata->opmode;
  652. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  653. pdata->buck2_init);
  654. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
  655. buck_init);
  656. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  657. pdata->buck3_init);
  658. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
  659. buck_init);
  660. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  661. pdata->buck4_init);
  662. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
  663. buck_init);
  664. for (i = 0; i < 8; i++) {
  665. if (s5m8767->buck2_gpiodvs) {
  666. s5m8767->buck2_vol[i] =
  667. s5m8767_convert_voltage_to_sel(
  668. &buck_voltage_val2,
  669. pdata->buck2_voltage[i]);
  670. }
  671. if (s5m8767->buck3_gpiodvs) {
  672. s5m8767->buck3_vol[i] =
  673. s5m8767_convert_voltage_to_sel(
  674. &buck_voltage_val2,
  675. pdata->buck3_voltage[i]);
  676. }
  677. if (s5m8767->buck4_gpiodvs) {
  678. s5m8767->buck4_vol[i] =
  679. s5m8767_convert_voltage_to_sel(
  680. &buck_voltage_val2,
  681. pdata->buck4_voltage[i]);
  682. }
  683. }
  684. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  685. pdata->buck4_gpiodvs) {
  686. if (!gpio_is_valid(pdata->buck_gpios[0]) ||
  687. !gpio_is_valid(pdata->buck_gpios[1]) ||
  688. !gpio_is_valid(pdata->buck_gpios[2])) {
  689. dev_err(&pdev->dev, "GPIO NOT VALID\n");
  690. return -EINVAL;
  691. }
  692. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
  693. "S5M8767 SET1");
  694. if (ret)
  695. return ret;
  696. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
  697. "S5M8767 SET2");
  698. if (ret)
  699. return ret;
  700. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
  701. "S5M8767 SET3");
  702. if (ret)
  703. return ret;
  704. /* SET1 GPIO */
  705. gpio_direction_output(pdata->buck_gpios[0],
  706. (s5m8767->buck_gpioindex >> 2) & 0x1);
  707. /* SET2 GPIO */
  708. gpio_direction_output(pdata->buck_gpios[1],
  709. (s5m8767->buck_gpioindex >> 1) & 0x1);
  710. /* SET3 GPIO */
  711. gpio_direction_output(pdata->buck_gpios[2],
  712. (s5m8767->buck_gpioindex >> 0) & 0x1);
  713. }
  714. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
  715. if (ret)
  716. return ret;
  717. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
  718. if (ret)
  719. return ret;
  720. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
  721. if (ret)
  722. return ret;
  723. /* DS2 GPIO */
  724. gpio_direction_output(pdata->buck_ds[0], 0x0);
  725. /* DS3 GPIO */
  726. gpio_direction_output(pdata->buck_ds[1], 0x0);
  727. /* DS4 GPIO */
  728. gpio_direction_output(pdata->buck_ds[2], 0x0);
  729. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  730. S5M8767_REG_BUCK2CTRL, 1 << 1,
  731. (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
  732. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  733. S5M8767_REG_BUCK3CTRL, 1 << 1,
  734. (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
  735. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  736. S5M8767_REG_BUCK4CTRL, 1 << 1,
  737. (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
  738. /* Initialize GPIO DVS registers */
  739. for (i = 0; i < 8; i++) {
  740. if (s5m8767->buck2_gpiodvs) {
  741. regmap_write(s5m8767->iodev->regmap_pmic,
  742. S5M8767_REG_BUCK2DVS1 + i,
  743. s5m8767->buck2_vol[i]);
  744. }
  745. if (s5m8767->buck3_gpiodvs) {
  746. regmap_write(s5m8767->iodev->regmap_pmic,
  747. S5M8767_REG_BUCK3DVS1 + i,
  748. s5m8767->buck3_vol[i]);
  749. }
  750. if (s5m8767->buck4_gpiodvs) {
  751. regmap_write(s5m8767->iodev->regmap_pmic,
  752. S5M8767_REG_BUCK4DVS1 + i,
  753. s5m8767->buck4_vol[i]);
  754. }
  755. }
  756. if (s5m8767->buck2_ramp)
  757. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  758. S5M8767_REG_DVSRAMP, 0x08, 0x08);
  759. if (s5m8767->buck3_ramp)
  760. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  761. S5M8767_REG_DVSRAMP, 0x04, 0x04);
  762. if (s5m8767->buck4_ramp)
  763. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  764. S5M8767_REG_DVSRAMP, 0x02, 0x02);
  765. if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
  766. || s5m8767->buck4_ramp) {
  767. unsigned int val;
  768. switch (s5m8767->ramp_delay) {
  769. case 5:
  770. val = S5M8767_DVS_BUCK_RAMP_5;
  771. break;
  772. case 10:
  773. val = S5M8767_DVS_BUCK_RAMP_10;
  774. break;
  775. case 25:
  776. val = S5M8767_DVS_BUCK_RAMP_25;
  777. break;
  778. case 50:
  779. val = S5M8767_DVS_BUCK_RAMP_50;
  780. break;
  781. case 100:
  782. val = S5M8767_DVS_BUCK_RAMP_100;
  783. break;
  784. default:
  785. val = S5M8767_DVS_BUCK_RAMP_10;
  786. }
  787. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  788. S5M8767_REG_DVSRAMP,
  789. S5M8767_DVS_BUCK_RAMP_MASK,
  790. val << S5M8767_DVS_BUCK_RAMP_SHIFT);
  791. }
  792. for (i = 0; i < pdata->num_regulators; i++) {
  793. const struct sec_voltage_desc *desc;
  794. unsigned int id = pdata->regulators[i].id;
  795. int enable_reg, enable_val;
  796. struct regulator_dev *rdev;
  797. BUILD_BUG_ON(ARRAY_SIZE(regulators) != ARRAY_SIZE(reg_voltage_map));
  798. if (WARN_ON_ONCE(id >= ARRAY_SIZE(regulators)))
  799. continue;
  800. desc = reg_voltage_map[id];
  801. if (desc) {
  802. regulators[id].n_voltages =
  803. (desc->max - desc->min) / desc->step + 1;
  804. regulators[id].min_uV = desc->min;
  805. regulators[id].uV_step = desc->step;
  806. regulators[id].vsel_reg =
  807. s5m8767_get_vsel_reg(id, s5m8767);
  808. if (id < S5M8767_BUCK1)
  809. regulators[id].vsel_mask = 0x3f;
  810. else
  811. regulators[id].vsel_mask = 0xff;
  812. ret = s5m8767_get_register(s5m8767, id, &enable_reg,
  813. &enable_val);
  814. if (ret) {
  815. dev_err(s5m8767->dev, "error reading registers\n");
  816. return ret;
  817. }
  818. regulators[id].enable_reg = enable_reg;
  819. regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
  820. regulators[id].enable_val = enable_val;
  821. }
  822. config.dev = s5m8767->dev;
  823. config.init_data = pdata->regulators[i].initdata;
  824. config.driver_data = s5m8767;
  825. config.regmap = iodev->regmap_pmic;
  826. config.of_node = pdata->regulators[i].reg_node;
  827. config.ena_gpiod = NULL;
  828. if (pdata->regulators[i].ext_control_gpiod) {
  829. /* Assigns config.ena_gpiod */
  830. s5m8767_regulator_config_ext_control(s5m8767,
  831. &pdata->regulators[i], &config);
  832. /*
  833. * Hand the GPIO descriptor management over to the
  834. * regulator core, remove it from devres management.
  835. */
  836. devm_gpiod_unhinge(s5m8767->dev, config.ena_gpiod);
  837. }
  838. rdev = devm_regulator_register(&pdev->dev, &regulators[id],
  839. &config);
  840. if (IS_ERR(rdev)) {
  841. ret = PTR_ERR(rdev);
  842. dev_err(s5m8767->dev, "regulator init failed for %d\n",
  843. id);
  844. return ret;
  845. }
  846. if (pdata->regulators[i].ext_control_gpiod) {
  847. ret = s5m8767_enable_ext_control(s5m8767, rdev);
  848. if (ret < 0) {
  849. dev_err(s5m8767->dev,
  850. "failed to enable gpio control over %s: %d\n",
  851. rdev->desc->name, ret);
  852. return ret;
  853. }
  854. }
  855. }
  856. return 0;
  857. }
  858. static const struct platform_device_id s5m8767_pmic_id[] = {
  859. { "s5m8767-pmic", 0},
  860. { },
  861. };
  862. MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
  863. static struct platform_driver s5m8767_pmic_driver = {
  864. .driver = {
  865. .name = "s5m8767-pmic",
  866. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  867. },
  868. .probe = s5m8767_pmic_probe,
  869. .id_table = s5m8767_pmic_id,
  870. };
  871. module_platform_driver(s5m8767_pmic_driver);
  872. /* Module information */
  873. MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
  874. MODULE_DESCRIPTION("Samsung S5M8767 Regulator Driver");
  875. MODULE_LICENSE("GPL");