spi-cavium-octeon.c 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2011, 2012 Cavium, Inc.
  7. */
  8. #include <linux/platform_device.h>
  9. #include <linux/spi/spi.h>
  10. #include <linux/module.h>
  11. #include <linux/io.h>
  12. #include <linux/of.h>
  13. #include <asm/octeon/octeon.h>
  14. #include "spi-cavium.h"
  15. static int octeon_spi_probe(struct platform_device *pdev)
  16. {
  17. void __iomem *reg_base;
  18. struct spi_controller *host;
  19. struct octeon_spi *p;
  20. int err = -ENOENT;
  21. host = spi_alloc_host(&pdev->dev, sizeof(struct octeon_spi));
  22. if (!host)
  23. return -ENOMEM;
  24. p = spi_controller_get_devdata(host);
  25. platform_set_drvdata(pdev, host);
  26. reg_base = devm_platform_ioremap_resource(pdev, 0);
  27. if (IS_ERR(reg_base)) {
  28. err = PTR_ERR(reg_base);
  29. goto fail;
  30. }
  31. p->register_base = reg_base;
  32. p->sys_freq = octeon_get_io_clock_rate();
  33. p->regs.config = 0;
  34. p->regs.status = 0x08;
  35. p->regs.tx = 0x10;
  36. p->regs.data = 0x80;
  37. host->num_chipselect = 4;
  38. host->mode_bits = SPI_CPHA |
  39. SPI_CPOL |
  40. SPI_CS_HIGH |
  41. SPI_LSB_FIRST |
  42. SPI_3WIRE;
  43. host->transfer_one_message = octeon_spi_transfer_one_message;
  44. host->bits_per_word_mask = SPI_BPW_MASK(8);
  45. host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
  46. host->dev.of_node = pdev->dev.of_node;
  47. err = devm_spi_register_controller(&pdev->dev, host);
  48. if (err) {
  49. dev_err(&pdev->dev, "register host failed: %d\n", err);
  50. goto fail;
  51. }
  52. dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
  53. return 0;
  54. fail:
  55. spi_controller_put(host);
  56. return err;
  57. }
  58. static void octeon_spi_remove(struct platform_device *pdev)
  59. {
  60. struct spi_controller *host = platform_get_drvdata(pdev);
  61. struct octeon_spi *p = spi_controller_get_devdata(host);
  62. /* Clear the CSENA* and put everything in a known state. */
  63. writeq(0, p->register_base + OCTEON_SPI_CFG(p));
  64. }
  65. static const struct of_device_id octeon_spi_match[] = {
  66. { .compatible = "cavium,octeon-3010-spi", },
  67. {},
  68. };
  69. MODULE_DEVICE_TABLE(of, octeon_spi_match);
  70. static struct platform_driver octeon_spi_driver = {
  71. .driver = {
  72. .name = "spi-octeon",
  73. .of_match_table = octeon_spi_match,
  74. },
  75. .probe = octeon_spi_probe,
  76. .remove_new = octeon_spi_remove,
  77. };
  78. module_platform_driver(octeon_spi_driver);
  79. MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
  80. MODULE_AUTHOR("David Daney");
  81. MODULE_LICENSE("GPL");