intel_quark_dts_thermal.c 11 KB

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  1. /*
  2. * intel_quark_dts_thermal.c
  3. *
  4. * This file is provided under a dual BSD/GPLv2 license. When using or
  5. * redistributing this file, you may do so under either license.
  6. *
  7. * GPL LICENSE SUMMARY
  8. *
  9. * Copyright(c) 2015 Intel Corporation.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * Contact Information:
  21. * Ong Boon Leong <boon.leong.ong@intel.com>
  22. * Intel Malaysia, Penang
  23. *
  24. * BSD LICENSE
  25. *
  26. * Copyright(c) 2015 Intel Corporation.
  27. *
  28. * Redistribution and use in source and binary forms, with or without
  29. * modification, are permitted provided that the following conditions
  30. * are met:
  31. *
  32. * * Redistributions of source code must retain the above copyright
  33. * notice, this list of conditions and the following disclaimer.
  34. * * Redistributions in binary form must reproduce the above copyright
  35. * notice, this list of conditions and the following disclaimer in
  36. * the documentation and/or other materials provided with the
  37. * distribution.
  38. * * Neither the name of Intel Corporation nor the names of its
  39. * contributors may be used to endorse or promote products derived
  40. * from this software without specific prior written permission.
  41. *
  42. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  43. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  44. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  45. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  46. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  47. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  48. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  49. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  50. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  51. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  52. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  53. *
  54. * Quark DTS thermal driver is implemented by referencing
  55. * intel_soc_dts_thermal.c.
  56. */
  57. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  58. #include <linux/module.h>
  59. #include <linux/slab.h>
  60. #include <linux/interrupt.h>
  61. #include <linux/thermal.h>
  62. #include <asm/cpu_device_id.h>
  63. #include <asm/iosf_mbi.h>
  64. /* DTS reset is programmed via QRK_MBI_UNIT_SOC */
  65. #define QRK_DTS_REG_OFFSET_RESET 0x34
  66. #define QRK_DTS_RESET_BIT BIT(0)
  67. /* DTS enable is programmed via QRK_MBI_UNIT_RMU */
  68. #define QRK_DTS_REG_OFFSET_ENABLE 0xB0
  69. #define QRK_DTS_ENABLE_BIT BIT(15)
  70. /* Temperature Register is read via QRK_MBI_UNIT_RMU */
  71. #define QRK_DTS_REG_OFFSET_TEMP 0xB1
  72. #define QRK_DTS_MASK_TEMP 0xFF
  73. #define QRK_DTS_OFFSET_TEMP 0
  74. #define QRK_DTS_OFFSET_REL_TEMP 16
  75. #define QRK_DTS_TEMP_BASE 50
  76. /* Programmable Trip Point Register is configured via QRK_MBI_UNIT_RMU */
  77. #define QRK_DTS_REG_OFFSET_PTPS 0xB2
  78. #define QRK_DTS_MASK_TP_THRES 0xFF
  79. #define QRK_DTS_SHIFT_TP 8
  80. #define QRK_DTS_ID_TP_CRITICAL 0
  81. #define QRK_DTS_ID_TP_HOT 1
  82. #define QRK_DTS_SAFE_TP_THRES 105
  83. /* Thermal Sensor Register Lock */
  84. #define QRK_DTS_REG_OFFSET_LOCK 0x71
  85. #define QRK_DTS_LOCK_BIT BIT(5)
  86. /* Quark DTS has 2 trip points: hot & catastrophic */
  87. #define QRK_MAX_DTS_TRIPS 2
  88. #define DEFAULT_POLL_DELAY 2000
  89. struct soc_sensor_entry {
  90. bool locked;
  91. u32 store_ptps;
  92. u32 store_dts_enable;
  93. struct thermal_zone_device *tzone;
  94. };
  95. static struct soc_sensor_entry *soc_dts;
  96. static int polling_delay = DEFAULT_POLL_DELAY;
  97. module_param(polling_delay, int, 0644);
  98. MODULE_PARM_DESC(polling_delay,
  99. "Polling interval for checking trip points (in milliseconds)");
  100. static DEFINE_MUTEX(dts_update_mutex);
  101. static int soc_dts_enable(struct thermal_zone_device *tzd)
  102. {
  103. u32 out;
  104. struct soc_sensor_entry *aux_entry = thermal_zone_device_priv(tzd);
  105. int ret;
  106. ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  107. QRK_DTS_REG_OFFSET_ENABLE, &out);
  108. if (ret)
  109. return ret;
  110. if (out & QRK_DTS_ENABLE_BIT)
  111. return 0;
  112. if (!aux_entry->locked) {
  113. out |= QRK_DTS_ENABLE_BIT;
  114. ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, MBI_REG_WRITE,
  115. QRK_DTS_REG_OFFSET_ENABLE, out);
  116. if (ret)
  117. return ret;
  118. } else {
  119. pr_info("DTS is locked. Cannot enable DTS\n");
  120. ret = -EPERM;
  121. }
  122. return ret;
  123. }
  124. static int soc_dts_disable(struct thermal_zone_device *tzd)
  125. {
  126. u32 out;
  127. struct soc_sensor_entry *aux_entry = thermal_zone_device_priv(tzd);
  128. int ret;
  129. ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  130. QRK_DTS_REG_OFFSET_ENABLE, &out);
  131. if (ret)
  132. return ret;
  133. if (!(out & QRK_DTS_ENABLE_BIT))
  134. return 0;
  135. if (!aux_entry->locked) {
  136. out &= ~QRK_DTS_ENABLE_BIT;
  137. ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, MBI_REG_WRITE,
  138. QRK_DTS_REG_OFFSET_ENABLE, out);
  139. if (ret)
  140. return ret;
  141. } else {
  142. pr_info("DTS is locked. Cannot disable DTS\n");
  143. ret = -EPERM;
  144. }
  145. return ret;
  146. }
  147. static int get_trip_temp(int trip)
  148. {
  149. int status, temp;
  150. u32 out;
  151. mutex_lock(&dts_update_mutex);
  152. status = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  153. QRK_DTS_REG_OFFSET_PTPS, &out);
  154. mutex_unlock(&dts_update_mutex);
  155. if (status)
  156. return THERMAL_TEMP_INVALID;
  157. /*
  158. * Thermal Sensor Programmable Trip Point Register has 8-bit
  159. * fields for critical (catastrophic) and hot set trip point
  160. * thresholds. The threshold value is always offset by its
  161. * temperature base (50 degree Celsius).
  162. */
  163. temp = (out >> (trip * QRK_DTS_SHIFT_TP)) & QRK_DTS_MASK_TP_THRES;
  164. temp -= QRK_DTS_TEMP_BASE;
  165. return temp;
  166. }
  167. static int update_trip_temp(struct soc_sensor_entry *aux_entry,
  168. int trip_index, int temp)
  169. {
  170. u32 out;
  171. u32 temp_out;
  172. u32 store_ptps;
  173. int ret;
  174. mutex_lock(&dts_update_mutex);
  175. if (aux_entry->locked) {
  176. ret = -EPERM;
  177. goto failed;
  178. }
  179. ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  180. QRK_DTS_REG_OFFSET_PTPS, &store_ptps);
  181. if (ret)
  182. goto failed;
  183. /*
  184. * Protection against unsafe trip point thresdhold value.
  185. * As Quark X1000 data-sheet does not provide any recommendation
  186. * regarding the safe trip point threshold value to use, we choose
  187. * the safe value according to the threshold value set by UEFI BIOS.
  188. */
  189. if (temp > QRK_DTS_SAFE_TP_THRES)
  190. temp = QRK_DTS_SAFE_TP_THRES;
  191. /*
  192. * Thermal Sensor Programmable Trip Point Register has 8-bit
  193. * fields for critical (catastrophic) and hot set trip point
  194. * thresholds. The threshold value is always offset by its
  195. * temperature base (50 degree Celsius).
  196. */
  197. temp_out = temp + QRK_DTS_TEMP_BASE;
  198. out = (store_ptps & ~(QRK_DTS_MASK_TP_THRES <<
  199. (trip_index * QRK_DTS_SHIFT_TP)));
  200. out |= (temp_out & QRK_DTS_MASK_TP_THRES) <<
  201. (trip_index * QRK_DTS_SHIFT_TP);
  202. ret = iosf_mbi_write(QRK_MBI_UNIT_RMU, MBI_REG_WRITE,
  203. QRK_DTS_REG_OFFSET_PTPS, out);
  204. failed:
  205. mutex_unlock(&dts_update_mutex);
  206. return ret;
  207. }
  208. static inline int sys_set_trip_temp(struct thermal_zone_device *tzd,
  209. const struct thermal_trip *trip,
  210. int temp)
  211. {
  212. unsigned int trip_index;
  213. switch (trip->type) {
  214. case THERMAL_TRIP_HOT:
  215. trip_index = QRK_DTS_ID_TP_HOT;
  216. break;
  217. case THERMAL_TRIP_CRITICAL:
  218. trip_index = QRK_DTS_ID_TP_CRITICAL;
  219. break;
  220. default:
  221. return -EINVAL;
  222. }
  223. return update_trip_temp(thermal_zone_device_priv(tzd), trip_index, temp);
  224. }
  225. static int sys_get_curr_temp(struct thermal_zone_device *tzd,
  226. int *temp)
  227. {
  228. u32 out;
  229. int ret;
  230. mutex_lock(&dts_update_mutex);
  231. ret = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  232. QRK_DTS_REG_OFFSET_TEMP, &out);
  233. mutex_unlock(&dts_update_mutex);
  234. if (ret)
  235. return ret;
  236. /*
  237. * Thermal Sensor Temperature Register has 8-bit field
  238. * for temperature value (offset by temperature base
  239. * 50 degree Celsius).
  240. */
  241. out = (out >> QRK_DTS_OFFSET_TEMP) & QRK_DTS_MASK_TEMP;
  242. *temp = out - QRK_DTS_TEMP_BASE;
  243. return 0;
  244. }
  245. static int sys_change_mode(struct thermal_zone_device *tzd,
  246. enum thermal_device_mode mode)
  247. {
  248. int ret;
  249. mutex_lock(&dts_update_mutex);
  250. if (mode == THERMAL_DEVICE_ENABLED)
  251. ret = soc_dts_enable(tzd);
  252. else
  253. ret = soc_dts_disable(tzd);
  254. mutex_unlock(&dts_update_mutex);
  255. return ret;
  256. }
  257. static const struct thermal_zone_device_ops tzone_ops = {
  258. .get_temp = sys_get_curr_temp,
  259. .set_trip_temp = sys_set_trip_temp,
  260. .change_mode = sys_change_mode,
  261. };
  262. static void free_soc_dts(struct soc_sensor_entry *aux_entry)
  263. {
  264. if (aux_entry) {
  265. if (!aux_entry->locked) {
  266. mutex_lock(&dts_update_mutex);
  267. iosf_mbi_write(QRK_MBI_UNIT_RMU, MBI_REG_WRITE,
  268. QRK_DTS_REG_OFFSET_ENABLE,
  269. aux_entry->store_dts_enable);
  270. iosf_mbi_write(QRK_MBI_UNIT_RMU, MBI_REG_WRITE,
  271. QRK_DTS_REG_OFFSET_PTPS,
  272. aux_entry->store_ptps);
  273. mutex_unlock(&dts_update_mutex);
  274. }
  275. thermal_zone_device_unregister(aux_entry->tzone);
  276. kfree(aux_entry);
  277. }
  278. }
  279. static struct soc_sensor_entry *alloc_soc_dts(void)
  280. {
  281. struct thermal_trip trips[QRK_MAX_DTS_TRIPS] = { 0 };
  282. struct soc_sensor_entry *aux_entry;
  283. int err;
  284. u32 out;
  285. aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
  286. if (!aux_entry) {
  287. err = -ENOMEM;
  288. return ERR_PTR(-ENOMEM);
  289. }
  290. /* Check if DTS register is locked */
  291. err = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  292. QRK_DTS_REG_OFFSET_LOCK, &out);
  293. if (err)
  294. goto err_ret;
  295. aux_entry->locked = !!(out & QRK_DTS_LOCK_BIT);
  296. /* Store DTS default state if DTS registers are not locked */
  297. if (!aux_entry->locked) {
  298. /* Store DTS default enable for restore on exit */
  299. err = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  300. QRK_DTS_REG_OFFSET_ENABLE,
  301. &aux_entry->store_dts_enable);
  302. if (err)
  303. goto err_ret;
  304. /* Store DTS default PTPS register for restore on exit */
  305. err = iosf_mbi_read(QRK_MBI_UNIT_RMU, MBI_REG_READ,
  306. QRK_DTS_REG_OFFSET_PTPS,
  307. &aux_entry->store_ptps);
  308. if (err)
  309. goto err_ret;
  310. trips[QRK_DTS_ID_TP_CRITICAL].flags |= THERMAL_TRIP_FLAG_RW_TEMP;
  311. trips[QRK_DTS_ID_TP_HOT].flags |= THERMAL_TRIP_FLAG_RW_TEMP;
  312. }
  313. trips[QRK_DTS_ID_TP_CRITICAL].temperature = get_trip_temp(QRK_DTS_ID_TP_CRITICAL);
  314. trips[QRK_DTS_ID_TP_CRITICAL].type = THERMAL_TRIP_CRITICAL;
  315. trips[QRK_DTS_ID_TP_HOT].temperature = get_trip_temp(QRK_DTS_ID_TP_HOT);
  316. trips[QRK_DTS_ID_TP_HOT].type = THERMAL_TRIP_HOT;
  317. aux_entry->tzone = thermal_zone_device_register_with_trips("quark_dts",
  318. trips,
  319. QRK_MAX_DTS_TRIPS,
  320. aux_entry,
  321. &tzone_ops,
  322. NULL, 0, polling_delay);
  323. if (IS_ERR(aux_entry->tzone)) {
  324. err = PTR_ERR(aux_entry->tzone);
  325. goto err_ret;
  326. }
  327. err = thermal_zone_device_enable(aux_entry->tzone);
  328. if (err)
  329. goto err_aux_status;
  330. return aux_entry;
  331. err_aux_status:
  332. thermal_zone_device_unregister(aux_entry->tzone);
  333. err_ret:
  334. kfree(aux_entry);
  335. return ERR_PTR(err);
  336. }
  337. static const struct x86_cpu_id qrk_thermal_ids[] __initconst = {
  338. X86_MATCH_VENDOR_FAM_MODEL(INTEL, 5, INTEL_FAM5_QUARK_X1000, NULL),
  339. {}
  340. };
  341. MODULE_DEVICE_TABLE(x86cpu, qrk_thermal_ids);
  342. static int __init intel_quark_thermal_init(void)
  343. {
  344. if (!x86_match_cpu(qrk_thermal_ids) || !iosf_mbi_available())
  345. return -ENODEV;
  346. soc_dts = alloc_soc_dts();
  347. if (IS_ERR(soc_dts))
  348. return PTR_ERR(soc_dts);
  349. return 0;
  350. }
  351. static void __exit intel_quark_thermal_exit(void)
  352. {
  353. free_soc_dts(soc_dts);
  354. }
  355. module_init(intel_quark_thermal_init)
  356. module_exit(intel_quark_thermal_exit)
  357. MODULE_DESCRIPTION("Intel Quark DTS Thermal Driver");
  358. MODULE_AUTHOR("Ong Boon Leong <boon.leong.ong@intel.com>");
  359. MODULE_LICENSE("Dual BSD/GPL");