sprd_serial.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/console.h>
  7. #include <linux/delay.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/dma/sprd-dma.h>
  11. #include <linux/io.h>
  12. #include <linux/ioport.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/serial.h>
  19. #include <linux/slab.h>
  20. #include <linux/tty.h>
  21. #include <linux/tty_flip.h>
  22. /* device name */
  23. #define UART_NR_MAX 8
  24. #define SPRD_TTY_NAME "ttyS"
  25. #define SPRD_FIFO_SIZE 128
  26. #define SPRD_DEF_RATE 26000000
  27. #define SPRD_BAUD_IO_LIMIT 3000000
  28. #define SPRD_TIMEOUT 256000
  29. /* the offset of serial registers and BITs for them */
  30. /* data registers */
  31. #define SPRD_TXD 0x0000
  32. #define SPRD_RXD 0x0004
  33. /* line status register and its BITs */
  34. #define SPRD_LSR 0x0008
  35. #define SPRD_LSR_OE BIT(4)
  36. #define SPRD_LSR_FE BIT(3)
  37. #define SPRD_LSR_PE BIT(2)
  38. #define SPRD_LSR_BI BIT(7)
  39. #define SPRD_LSR_TX_OVER BIT(15)
  40. /* data number in TX and RX fifo */
  41. #define SPRD_STS1 0x000C
  42. #define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
  43. #define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
  44. /* interrupt enable register and its BITs */
  45. #define SPRD_IEN 0x0010
  46. #define SPRD_IEN_RX_FULL BIT(0)
  47. #define SPRD_IEN_TX_EMPTY BIT(1)
  48. #define SPRD_IEN_BREAK_DETECT BIT(7)
  49. #define SPRD_IEN_TIMEOUT BIT(13)
  50. /* interrupt clear register */
  51. #define SPRD_ICLR 0x0014
  52. #define SPRD_ICLR_TIMEOUT BIT(13)
  53. /* line control register */
  54. #define SPRD_LCR 0x0018
  55. #define SPRD_LCR_STOP_1BIT 0x10
  56. #define SPRD_LCR_STOP_2BIT 0x30
  57. #define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
  58. #define SPRD_LCR_DATA_LEN5 0x0
  59. #define SPRD_LCR_DATA_LEN6 0x4
  60. #define SPRD_LCR_DATA_LEN7 0x8
  61. #define SPRD_LCR_DATA_LEN8 0xc
  62. #define SPRD_LCR_PARITY (BIT(0) | BIT(1))
  63. #define SPRD_LCR_PARITY_EN 0x2
  64. #define SPRD_LCR_EVEN_PAR 0x0
  65. #define SPRD_LCR_ODD_PAR 0x1
  66. /* control register 1 */
  67. #define SPRD_CTL1 0x001C
  68. #define SPRD_DMA_EN BIT(15)
  69. #define SPRD_LOOPBACK_EN BIT(14)
  70. #define RX_HW_FLOW_CTL_THLD BIT(6)
  71. #define RX_HW_FLOW_CTL_EN BIT(7)
  72. #define TX_HW_FLOW_CTL_EN BIT(8)
  73. #define RX_TOUT_THLD_DEF 0x3E00
  74. #define RX_HFC_THLD_DEF 0x40
  75. /* fifo threshold register */
  76. #define SPRD_CTL2 0x0020
  77. #define THLD_TX_EMPTY 0x40
  78. #define THLD_TX_EMPTY_SHIFT 8
  79. #define THLD_RX_FULL 0x40
  80. #define THLD_RX_FULL_MASK GENMASK(6, 0)
  81. /* config baud rate register */
  82. #define SPRD_CLKD0 0x0024
  83. #define SPRD_CLKD0_MASK GENMASK(15, 0)
  84. #define SPRD_CLKD1 0x0028
  85. #define SPRD_CLKD1_MASK GENMASK(20, 16)
  86. #define SPRD_CLKD1_SHIFT 16
  87. /* interrupt mask status register */
  88. #define SPRD_IMSR 0x002C
  89. #define SPRD_IMSR_RX_FIFO_FULL BIT(0)
  90. #define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
  91. #define SPRD_IMSR_BREAK_DETECT BIT(7)
  92. #define SPRD_IMSR_TIMEOUT BIT(13)
  93. #define SPRD_DEFAULT_SOURCE_CLK 26000000
  94. #define SPRD_RX_DMA_STEP 1
  95. #define SPRD_RX_FIFO_FULL 1
  96. #define SPRD_TX_FIFO_FULL 0x20
  97. #define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
  98. struct sprd_uart_dma {
  99. struct dma_chan *chn;
  100. unsigned char *virt;
  101. dma_addr_t phys_addr;
  102. dma_cookie_t cookie;
  103. u32 trans_len;
  104. bool enable;
  105. };
  106. struct sprd_uart_port {
  107. struct uart_port port;
  108. char name[16];
  109. struct clk *clk;
  110. struct sprd_uart_dma tx_dma;
  111. struct sprd_uart_dma rx_dma;
  112. dma_addr_t pos;
  113. unsigned char *rx_buf_tail;
  114. };
  115. static struct sprd_uart_port *sprd_port[UART_NR_MAX];
  116. static int sprd_ports_num;
  117. static int sprd_start_dma_rx(struct uart_port *port);
  118. static int sprd_tx_dma_config(struct uart_port *port);
  119. static inline unsigned int serial_in(struct uart_port *port,
  120. unsigned int offset)
  121. {
  122. return readl_relaxed(port->membase + offset);
  123. }
  124. static inline void serial_out(struct uart_port *port, unsigned int offset,
  125. int value)
  126. {
  127. writel_relaxed(value, port->membase + offset);
  128. }
  129. static unsigned int sprd_tx_empty(struct uart_port *port)
  130. {
  131. if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  132. return 0;
  133. else
  134. return TIOCSER_TEMT;
  135. }
  136. static unsigned int sprd_get_mctrl(struct uart_port *port)
  137. {
  138. return TIOCM_DSR | TIOCM_CTS;
  139. }
  140. static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
  141. {
  142. u32 val = serial_in(port, SPRD_CTL1);
  143. if (mctrl & TIOCM_LOOP)
  144. val |= SPRD_LOOPBACK_EN;
  145. else
  146. val &= ~SPRD_LOOPBACK_EN;
  147. serial_out(port, SPRD_CTL1, val);
  148. }
  149. static void sprd_stop_rx(struct uart_port *port)
  150. {
  151. struct sprd_uart_port *sp =
  152. container_of(port, struct sprd_uart_port, port);
  153. unsigned int ien, iclr;
  154. if (sp->rx_dma.enable)
  155. dmaengine_terminate_all(sp->rx_dma.chn);
  156. iclr = serial_in(port, SPRD_ICLR);
  157. ien = serial_in(port, SPRD_IEN);
  158. ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
  159. iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
  160. serial_out(port, SPRD_IEN, ien);
  161. serial_out(port, SPRD_ICLR, iclr);
  162. }
  163. static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
  164. {
  165. u32 val = serial_in(port, SPRD_CTL1);
  166. if (enable)
  167. val |= SPRD_DMA_EN;
  168. else
  169. val &= ~SPRD_DMA_EN;
  170. serial_out(port, SPRD_CTL1, val);
  171. }
  172. static void sprd_stop_tx_dma(struct uart_port *port)
  173. {
  174. struct sprd_uart_port *sp =
  175. container_of(port, struct sprd_uart_port, port);
  176. struct dma_tx_state state;
  177. u32 trans_len;
  178. dmaengine_pause(sp->tx_dma.chn);
  179. dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
  180. if (state.residue) {
  181. trans_len = state.residue - sp->tx_dma.phys_addr;
  182. uart_xmit_advance(port, trans_len);
  183. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  184. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  185. }
  186. dmaengine_terminate_all(sp->tx_dma.chn);
  187. sp->tx_dma.trans_len = 0;
  188. }
  189. static int sprd_tx_buf_remap(struct uart_port *port)
  190. {
  191. struct sprd_uart_port *sp =
  192. container_of(port, struct sprd_uart_port, port);
  193. struct tty_port *tport = &port->state->port;
  194. unsigned char *tail;
  195. sp->tx_dma.trans_len = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
  196. UART_XMIT_SIZE);
  197. sp->tx_dma.phys_addr = dma_map_single(port->dev, tail,
  198. sp->tx_dma.trans_len,
  199. DMA_TO_DEVICE);
  200. return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
  201. }
  202. static void sprd_complete_tx_dma(void *data)
  203. {
  204. struct uart_port *port = (struct uart_port *)data;
  205. struct sprd_uart_port *sp =
  206. container_of(port, struct sprd_uart_port, port);
  207. struct tty_port *tport = &port->state->port;
  208. unsigned long flags;
  209. uart_port_lock_irqsave(port, &flags);
  210. dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
  211. sp->tx_dma.trans_len, DMA_TO_DEVICE);
  212. uart_xmit_advance(port, sp->tx_dma.trans_len);
  213. if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
  214. uart_write_wakeup(port);
  215. if (kfifo_is_empty(&tport->xmit_fifo) || sprd_tx_buf_remap(port) ||
  216. sprd_tx_dma_config(port))
  217. sp->tx_dma.trans_len = 0;
  218. uart_port_unlock_irqrestore(port, flags);
  219. }
  220. static int sprd_uart_dma_submit(struct uart_port *port,
  221. struct sprd_uart_dma *ud, u32 trans_len,
  222. enum dma_transfer_direction direction,
  223. dma_async_tx_callback callback)
  224. {
  225. struct dma_async_tx_descriptor *dma_des;
  226. unsigned long flags;
  227. flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
  228. SPRD_DMA_NO_TRG,
  229. SPRD_DMA_FRAG_REQ,
  230. SPRD_DMA_TRANS_INT);
  231. dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
  232. direction, flags);
  233. if (!dma_des)
  234. return -ENODEV;
  235. dma_des->callback = callback;
  236. dma_des->callback_param = port;
  237. ud->cookie = dmaengine_submit(dma_des);
  238. if (dma_submit_error(ud->cookie))
  239. return dma_submit_error(ud->cookie);
  240. dma_async_issue_pending(ud->chn);
  241. return 0;
  242. }
  243. static int sprd_tx_dma_config(struct uart_port *port)
  244. {
  245. struct sprd_uart_port *sp =
  246. container_of(port, struct sprd_uart_port, port);
  247. u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
  248. SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
  249. int ret;
  250. struct dma_slave_config cfg = {
  251. .dst_addr = port->mapbase + SPRD_TXD,
  252. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  253. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  254. .src_maxburst = burst,
  255. };
  256. ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
  257. if (ret < 0)
  258. return ret;
  259. return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
  260. DMA_MEM_TO_DEV, sprd_complete_tx_dma);
  261. }
  262. static void sprd_start_tx_dma(struct uart_port *port)
  263. {
  264. struct sprd_uart_port *sp =
  265. container_of(port, struct sprd_uart_port, port);
  266. struct tty_port *tport = &port->state->port;
  267. if (port->x_char) {
  268. serial_out(port, SPRD_TXD, port->x_char);
  269. port->icount.tx++;
  270. port->x_char = 0;
  271. return;
  272. }
  273. if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
  274. sprd_stop_tx_dma(port);
  275. return;
  276. }
  277. if (sp->tx_dma.trans_len)
  278. return;
  279. if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
  280. sp->tx_dma.trans_len = 0;
  281. }
  282. static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
  283. {
  284. u32 val = serial_in(port, SPRD_CTL2);
  285. val &= ~THLD_RX_FULL_MASK;
  286. val |= thld & THLD_RX_FULL_MASK;
  287. serial_out(port, SPRD_CTL2, val);
  288. }
  289. static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
  290. {
  291. sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  292. &sp->rx_dma.phys_addr, GFP_KERNEL);
  293. if (!sp->rx_dma.virt)
  294. return -ENOMEM;
  295. return 0;
  296. }
  297. static void sprd_rx_free_buf(struct sprd_uart_port *sp)
  298. {
  299. if (sp->rx_dma.virt)
  300. dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
  301. sp->rx_dma.virt, sp->rx_dma.phys_addr);
  302. sp->rx_dma.virt = NULL;
  303. }
  304. static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
  305. {
  306. struct sprd_uart_port *sp =
  307. container_of(port, struct sprd_uart_port, port);
  308. struct dma_slave_config cfg = {
  309. .src_addr = port->mapbase + SPRD_RXD,
  310. .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  311. .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  312. .src_maxburst = burst,
  313. };
  314. return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
  315. }
  316. static void sprd_uart_dma_rx(struct uart_port *port)
  317. {
  318. struct sprd_uart_port *sp =
  319. container_of(port, struct sprd_uart_port, port);
  320. struct tty_port *tty = &port->state->port;
  321. port->icount.rx += sp->rx_dma.trans_len;
  322. tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
  323. tty_flip_buffer_push(tty);
  324. }
  325. static void sprd_uart_dma_irq(struct uart_port *port)
  326. {
  327. struct sprd_uart_port *sp =
  328. container_of(port, struct sprd_uart_port, port);
  329. struct dma_tx_state state;
  330. enum dma_status status;
  331. status = dmaengine_tx_status(sp->rx_dma.chn,
  332. sp->rx_dma.cookie, &state);
  333. if (status == DMA_ERROR)
  334. sprd_stop_rx(port);
  335. if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
  336. return;
  337. if (!state.residue) {
  338. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  339. sp->rx_dma.phys_addr - sp->pos;
  340. sp->pos = sp->rx_dma.phys_addr;
  341. } else {
  342. sp->rx_dma.trans_len = state.residue - sp->pos;
  343. sp->pos = state.residue;
  344. }
  345. sprd_uart_dma_rx(port);
  346. sp->rx_buf_tail += sp->rx_dma.trans_len;
  347. }
  348. static void sprd_complete_rx_dma(void *data)
  349. {
  350. struct uart_port *port = (struct uart_port *)data;
  351. struct sprd_uart_port *sp =
  352. container_of(port, struct sprd_uart_port, port);
  353. struct dma_tx_state state;
  354. enum dma_status status;
  355. unsigned long flags;
  356. uart_port_lock_irqsave(port, &flags);
  357. status = dmaengine_tx_status(sp->rx_dma.chn,
  358. sp->rx_dma.cookie, &state);
  359. if (status != DMA_COMPLETE) {
  360. sprd_stop_rx(port);
  361. uart_port_unlock_irqrestore(port, flags);
  362. return;
  363. }
  364. if (sp->pos != sp->rx_dma.phys_addr) {
  365. sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
  366. sp->rx_dma.phys_addr - sp->pos;
  367. sprd_uart_dma_rx(port);
  368. sp->rx_buf_tail += sp->rx_dma.trans_len;
  369. }
  370. if (sprd_start_dma_rx(port))
  371. sprd_stop_rx(port);
  372. uart_port_unlock_irqrestore(port, flags);
  373. }
  374. static int sprd_start_dma_rx(struct uart_port *port)
  375. {
  376. struct sprd_uart_port *sp =
  377. container_of(port, struct sprd_uart_port, port);
  378. int ret;
  379. if (!sp->rx_dma.enable)
  380. return 0;
  381. sp->pos = sp->rx_dma.phys_addr;
  382. sp->rx_buf_tail = sp->rx_dma.virt;
  383. sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
  384. ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
  385. if (ret)
  386. return ret;
  387. return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
  388. DMA_DEV_TO_MEM, sprd_complete_rx_dma);
  389. }
  390. static void sprd_release_dma(struct uart_port *port)
  391. {
  392. struct sprd_uart_port *sp =
  393. container_of(port, struct sprd_uart_port, port);
  394. sprd_uart_dma_enable(port, false);
  395. if (sp->rx_dma.enable)
  396. dma_release_channel(sp->rx_dma.chn);
  397. if (sp->tx_dma.enable)
  398. dma_release_channel(sp->tx_dma.chn);
  399. sp->tx_dma.enable = false;
  400. sp->rx_dma.enable = false;
  401. }
  402. static void sprd_request_dma(struct uart_port *port)
  403. {
  404. struct sprd_uart_port *sp =
  405. container_of(port, struct sprd_uart_port, port);
  406. sp->tx_dma.enable = true;
  407. sp->rx_dma.enable = true;
  408. sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
  409. if (IS_ERR(sp->tx_dma.chn)) {
  410. dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
  411. PTR_ERR(sp->tx_dma.chn));
  412. sp->tx_dma.enable = false;
  413. }
  414. sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
  415. if (IS_ERR(sp->rx_dma.chn)) {
  416. dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
  417. PTR_ERR(sp->rx_dma.chn));
  418. sp->rx_dma.enable = false;
  419. }
  420. }
  421. static void sprd_stop_tx(struct uart_port *port)
  422. {
  423. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  424. port);
  425. unsigned int ien, iclr;
  426. if (sp->tx_dma.enable) {
  427. sprd_stop_tx_dma(port);
  428. return;
  429. }
  430. iclr = serial_in(port, SPRD_ICLR);
  431. ien = serial_in(port, SPRD_IEN);
  432. iclr |= SPRD_IEN_TX_EMPTY;
  433. ien &= ~SPRD_IEN_TX_EMPTY;
  434. serial_out(port, SPRD_IEN, ien);
  435. serial_out(port, SPRD_ICLR, iclr);
  436. }
  437. static void sprd_start_tx(struct uart_port *port)
  438. {
  439. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  440. port);
  441. unsigned int ien;
  442. if (sp->tx_dma.enable) {
  443. sprd_start_tx_dma(port);
  444. return;
  445. }
  446. ien = serial_in(port, SPRD_IEN);
  447. if (!(ien & SPRD_IEN_TX_EMPTY)) {
  448. ien |= SPRD_IEN_TX_EMPTY;
  449. serial_out(port, SPRD_IEN, ien);
  450. }
  451. }
  452. /* The Sprd serial does not support this function. */
  453. static void sprd_break_ctl(struct uart_port *port, int break_state)
  454. {
  455. /* nothing to do */
  456. }
  457. static int handle_lsr_errors(struct uart_port *port,
  458. u8 *flag,
  459. unsigned int *lsr)
  460. {
  461. int ret = 0;
  462. /* statistics */
  463. if (*lsr & SPRD_LSR_BI) {
  464. *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
  465. port->icount.brk++;
  466. ret = uart_handle_break(port);
  467. if (ret)
  468. return ret;
  469. } else if (*lsr & SPRD_LSR_PE)
  470. port->icount.parity++;
  471. else if (*lsr & SPRD_LSR_FE)
  472. port->icount.frame++;
  473. if (*lsr & SPRD_LSR_OE)
  474. port->icount.overrun++;
  475. /* mask off conditions which should be ignored */
  476. *lsr &= port->read_status_mask;
  477. if (*lsr & SPRD_LSR_BI)
  478. *flag = TTY_BREAK;
  479. else if (*lsr & SPRD_LSR_PE)
  480. *flag = TTY_PARITY;
  481. else if (*lsr & SPRD_LSR_FE)
  482. *flag = TTY_FRAME;
  483. return ret;
  484. }
  485. static inline void sprd_rx(struct uart_port *port)
  486. {
  487. struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
  488. port);
  489. struct tty_port *tty = &port->state->port;
  490. unsigned int lsr, max_count = SPRD_TIMEOUT;
  491. u8 ch, flag;
  492. if (sp->rx_dma.enable) {
  493. sprd_uart_dma_irq(port);
  494. return;
  495. }
  496. while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
  497. max_count--) {
  498. lsr = serial_in(port, SPRD_LSR);
  499. ch = serial_in(port, SPRD_RXD);
  500. flag = TTY_NORMAL;
  501. port->icount.rx++;
  502. if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
  503. SPRD_LSR_FE | SPRD_LSR_OE))
  504. if (handle_lsr_errors(port, &flag, &lsr))
  505. continue;
  506. if (uart_handle_sysrq_char(port, ch))
  507. continue;
  508. uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
  509. }
  510. tty_flip_buffer_push(tty);
  511. }
  512. static inline void sprd_tx(struct uart_port *port)
  513. {
  514. u8 ch;
  515. uart_port_tx_limited(port, ch, THLD_TX_EMPTY,
  516. true,
  517. serial_out(port, SPRD_TXD, ch),
  518. ({}));
  519. }
  520. /* this handles the interrupt from one port */
  521. static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
  522. {
  523. struct uart_port *port = dev_id;
  524. unsigned int ims;
  525. uart_port_lock(port);
  526. ims = serial_in(port, SPRD_IMSR);
  527. if (!ims) {
  528. uart_port_unlock(port);
  529. return IRQ_NONE;
  530. }
  531. if (ims & SPRD_IMSR_TIMEOUT)
  532. serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
  533. if (ims & SPRD_IMSR_BREAK_DETECT)
  534. serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
  535. if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
  536. SPRD_IMSR_TIMEOUT))
  537. sprd_rx(port);
  538. if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
  539. sprd_tx(port);
  540. uart_port_unlock(port);
  541. return IRQ_HANDLED;
  542. }
  543. static void sprd_uart_dma_startup(struct uart_port *port,
  544. struct sprd_uart_port *sp)
  545. {
  546. int ret;
  547. sprd_request_dma(port);
  548. if (!(sp->rx_dma.enable || sp->tx_dma.enable))
  549. return;
  550. ret = sprd_start_dma_rx(port);
  551. if (ret) {
  552. sp->rx_dma.enable = false;
  553. dma_release_channel(sp->rx_dma.chn);
  554. dev_warn(port->dev, "fail to start RX dma mode\n");
  555. }
  556. sprd_uart_dma_enable(port, true);
  557. }
  558. static int sprd_startup(struct uart_port *port)
  559. {
  560. int ret = 0;
  561. unsigned int ien, fc;
  562. unsigned int timeout;
  563. struct sprd_uart_port *sp;
  564. unsigned long flags;
  565. serial_out(port, SPRD_CTL2,
  566. THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
  567. /* clear rx fifo */
  568. timeout = SPRD_TIMEOUT;
  569. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
  570. serial_in(port, SPRD_RXD);
  571. /* clear tx fifo */
  572. timeout = SPRD_TIMEOUT;
  573. while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  574. cpu_relax();
  575. /* clear interrupt */
  576. serial_out(port, SPRD_IEN, 0);
  577. serial_out(port, SPRD_ICLR, ~0);
  578. /* allocate irq */
  579. sp = container_of(port, struct sprd_uart_port, port);
  580. snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
  581. sprd_uart_dma_startup(port, sp);
  582. ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
  583. IRQF_SHARED, sp->name, port);
  584. if (ret) {
  585. dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
  586. port->irq, ret);
  587. return ret;
  588. }
  589. fc = serial_in(port, SPRD_CTL1);
  590. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  591. serial_out(port, SPRD_CTL1, fc);
  592. /* enable interrupt */
  593. uart_port_lock_irqsave(port, &flags);
  594. ien = serial_in(port, SPRD_IEN);
  595. ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
  596. if (!sp->rx_dma.enable)
  597. ien |= SPRD_IEN_RX_FULL;
  598. serial_out(port, SPRD_IEN, ien);
  599. uart_port_unlock_irqrestore(port, flags);
  600. return 0;
  601. }
  602. static void sprd_shutdown(struct uart_port *port)
  603. {
  604. sprd_release_dma(port);
  605. serial_out(port, SPRD_IEN, 0);
  606. serial_out(port, SPRD_ICLR, ~0);
  607. devm_free_irq(port->dev, port->irq, port);
  608. }
  609. static void sprd_set_termios(struct uart_port *port, struct ktermios *termios,
  610. const struct ktermios *old)
  611. {
  612. unsigned int baud, quot;
  613. unsigned int lcr = 0, fc;
  614. unsigned long flags;
  615. /* ask the core to calculate the divisor for us */
  616. baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
  617. quot = port->uartclk / baud;
  618. /* set data length */
  619. switch (termios->c_cflag & CSIZE) {
  620. case CS5:
  621. lcr |= SPRD_LCR_DATA_LEN5;
  622. break;
  623. case CS6:
  624. lcr |= SPRD_LCR_DATA_LEN6;
  625. break;
  626. case CS7:
  627. lcr |= SPRD_LCR_DATA_LEN7;
  628. break;
  629. case CS8:
  630. default:
  631. lcr |= SPRD_LCR_DATA_LEN8;
  632. break;
  633. }
  634. /* calculate stop bits */
  635. lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
  636. if (termios->c_cflag & CSTOPB)
  637. lcr |= SPRD_LCR_STOP_2BIT;
  638. else
  639. lcr |= SPRD_LCR_STOP_1BIT;
  640. /* calculate parity */
  641. lcr &= ~SPRD_LCR_PARITY;
  642. termios->c_cflag &= ~CMSPAR; /* no support mark/space */
  643. if (termios->c_cflag & PARENB) {
  644. lcr |= SPRD_LCR_PARITY_EN;
  645. if (termios->c_cflag & PARODD)
  646. lcr |= SPRD_LCR_ODD_PAR;
  647. else
  648. lcr |= SPRD_LCR_EVEN_PAR;
  649. }
  650. uart_port_lock_irqsave(port, &flags);
  651. /* update the per-port timeout */
  652. uart_update_timeout(port, termios->c_cflag, baud);
  653. port->read_status_mask = SPRD_LSR_OE;
  654. if (termios->c_iflag & INPCK)
  655. port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
  656. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  657. port->read_status_mask |= SPRD_LSR_BI;
  658. /* characters to ignore */
  659. port->ignore_status_mask = 0;
  660. if (termios->c_iflag & IGNPAR)
  661. port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
  662. if (termios->c_iflag & IGNBRK) {
  663. port->ignore_status_mask |= SPRD_LSR_BI;
  664. /*
  665. * If we're ignoring parity and break indicators,
  666. * ignore overruns too (for real raw support).
  667. */
  668. if (termios->c_iflag & IGNPAR)
  669. port->ignore_status_mask |= SPRD_LSR_OE;
  670. }
  671. /* flow control */
  672. fc = serial_in(port, SPRD_CTL1);
  673. fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
  674. if (termios->c_cflag & CRTSCTS) {
  675. fc |= RX_HW_FLOW_CTL_THLD;
  676. fc |= RX_HW_FLOW_CTL_EN;
  677. fc |= TX_HW_FLOW_CTL_EN;
  678. }
  679. /* clock divider bit0~bit15 */
  680. serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
  681. /* clock divider bit16~bit20 */
  682. serial_out(port, SPRD_CLKD1,
  683. (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
  684. serial_out(port, SPRD_LCR, lcr);
  685. fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
  686. serial_out(port, SPRD_CTL1, fc);
  687. uart_port_unlock_irqrestore(port, flags);
  688. /* Don't rewrite B0 */
  689. if (tty_termios_baud_rate(termios))
  690. tty_termios_encode_baud_rate(termios, baud, baud);
  691. }
  692. static const char *sprd_type(struct uart_port *port)
  693. {
  694. return "SPX";
  695. }
  696. static void sprd_release_port(struct uart_port *port)
  697. {
  698. /* nothing to do */
  699. }
  700. static int sprd_request_port(struct uart_port *port)
  701. {
  702. return 0;
  703. }
  704. static void sprd_config_port(struct uart_port *port, int flags)
  705. {
  706. if (flags & UART_CONFIG_TYPE)
  707. port->type = PORT_SPRD;
  708. }
  709. static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
  710. {
  711. if (ser->type != PORT_SPRD)
  712. return -EINVAL;
  713. if (port->irq != ser->irq)
  714. return -EINVAL;
  715. if (port->iotype != ser->io_type)
  716. return -EINVAL;
  717. return 0;
  718. }
  719. static void sprd_pm(struct uart_port *port, unsigned int state,
  720. unsigned int oldstate)
  721. {
  722. struct sprd_uart_port *sup =
  723. container_of(port, struct sprd_uart_port, port);
  724. switch (state) {
  725. case UART_PM_STATE_ON:
  726. clk_prepare_enable(sup->clk);
  727. break;
  728. case UART_PM_STATE_OFF:
  729. clk_disable_unprepare(sup->clk);
  730. break;
  731. }
  732. }
  733. #ifdef CONFIG_CONSOLE_POLL
  734. static int sprd_poll_init(struct uart_port *port)
  735. {
  736. if (port->state->pm_state != UART_PM_STATE_ON) {
  737. sprd_pm(port, UART_PM_STATE_ON, 0);
  738. port->state->pm_state = UART_PM_STATE_ON;
  739. }
  740. return 0;
  741. }
  742. static int sprd_poll_get_char(struct uart_port *port)
  743. {
  744. while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
  745. cpu_relax();
  746. return serial_in(port, SPRD_RXD);
  747. }
  748. static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
  749. {
  750. while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
  751. cpu_relax();
  752. serial_out(port, SPRD_TXD, ch);
  753. }
  754. #endif
  755. static const struct uart_ops serial_sprd_ops = {
  756. .tx_empty = sprd_tx_empty,
  757. .get_mctrl = sprd_get_mctrl,
  758. .set_mctrl = sprd_set_mctrl,
  759. .stop_tx = sprd_stop_tx,
  760. .start_tx = sprd_start_tx,
  761. .stop_rx = sprd_stop_rx,
  762. .break_ctl = sprd_break_ctl,
  763. .startup = sprd_startup,
  764. .shutdown = sprd_shutdown,
  765. .set_termios = sprd_set_termios,
  766. .type = sprd_type,
  767. .release_port = sprd_release_port,
  768. .request_port = sprd_request_port,
  769. .config_port = sprd_config_port,
  770. .verify_port = sprd_verify_port,
  771. .pm = sprd_pm,
  772. #ifdef CONFIG_CONSOLE_POLL
  773. .poll_init = sprd_poll_init,
  774. .poll_get_char = sprd_poll_get_char,
  775. .poll_put_char = sprd_poll_put_char,
  776. #endif
  777. };
  778. #ifdef CONFIG_SERIAL_SPRD_CONSOLE
  779. static void wait_for_xmitr(struct uart_port *port)
  780. {
  781. unsigned int status, tmout = 10000;
  782. /* wait up to 10ms for the character(s) to be sent */
  783. do {
  784. status = serial_in(port, SPRD_STS1);
  785. if (--tmout == 0)
  786. break;
  787. udelay(1);
  788. } while (status & SPRD_TX_FIFO_CNT_MASK);
  789. }
  790. static void sprd_console_putchar(struct uart_port *port, unsigned char ch)
  791. {
  792. wait_for_xmitr(port);
  793. serial_out(port, SPRD_TXD, ch);
  794. }
  795. static void sprd_console_write(struct console *co, const char *s,
  796. unsigned int count)
  797. {
  798. struct uart_port *port = &sprd_port[co->index]->port;
  799. int locked = 1;
  800. unsigned long flags;
  801. if (port->sysrq)
  802. locked = 0;
  803. else if (oops_in_progress)
  804. locked = uart_port_trylock_irqsave(port, &flags);
  805. else
  806. uart_port_lock_irqsave(port, &flags);
  807. uart_console_write(port, s, count, sprd_console_putchar);
  808. /* wait for transmitter to become empty */
  809. wait_for_xmitr(port);
  810. if (locked)
  811. uart_port_unlock_irqrestore(port, flags);
  812. }
  813. static int sprd_console_setup(struct console *co, char *options)
  814. {
  815. struct sprd_uart_port *sprd_uart_port;
  816. int baud = 115200;
  817. int bits = 8;
  818. int parity = 'n';
  819. int flow = 'n';
  820. if (co->index >= UART_NR_MAX || co->index < 0)
  821. co->index = 0;
  822. sprd_uart_port = sprd_port[co->index];
  823. if (!sprd_uart_port || !sprd_uart_port->port.membase) {
  824. pr_info("serial port %d not yet initialized\n", co->index);
  825. return -ENODEV;
  826. }
  827. if (options)
  828. uart_parse_options(options, &baud, &parity, &bits, &flow);
  829. return uart_set_options(&sprd_uart_port->port, co, baud,
  830. parity, bits, flow);
  831. }
  832. static struct uart_driver sprd_uart_driver;
  833. static struct console sprd_console = {
  834. .name = SPRD_TTY_NAME,
  835. .write = sprd_console_write,
  836. .device = uart_console_device,
  837. .setup = sprd_console_setup,
  838. .flags = CON_PRINTBUFFER,
  839. .index = -1,
  840. .data = &sprd_uart_driver,
  841. };
  842. static int __init sprd_serial_console_init(void)
  843. {
  844. register_console(&sprd_console);
  845. return 0;
  846. }
  847. console_initcall(sprd_serial_console_init);
  848. #define SPRD_CONSOLE (&sprd_console)
  849. /* Support for earlycon */
  850. static void sprd_putc(struct uart_port *port, unsigned char c)
  851. {
  852. unsigned int timeout = SPRD_TIMEOUT;
  853. while (timeout-- &&
  854. !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
  855. cpu_relax();
  856. writeb(c, port->membase + SPRD_TXD);
  857. }
  858. static void sprd_early_write(struct console *con, const char *s, unsigned int n)
  859. {
  860. struct earlycon_device *dev = con->data;
  861. uart_console_write(&dev->port, s, n, sprd_putc);
  862. }
  863. static int __init sprd_early_console_setup(struct earlycon_device *device,
  864. const char *opt)
  865. {
  866. if (!device->port.membase)
  867. return -ENODEV;
  868. device->con->write = sprd_early_write;
  869. return 0;
  870. }
  871. OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
  872. sprd_early_console_setup);
  873. #else /* !CONFIG_SERIAL_SPRD_CONSOLE */
  874. #define SPRD_CONSOLE NULL
  875. #endif
  876. static struct uart_driver sprd_uart_driver = {
  877. .owner = THIS_MODULE,
  878. .driver_name = "sprd_serial",
  879. .dev_name = SPRD_TTY_NAME,
  880. .major = 0,
  881. .minor = 0,
  882. .nr = UART_NR_MAX,
  883. .cons = SPRD_CONSOLE,
  884. };
  885. static void sprd_remove(struct platform_device *dev)
  886. {
  887. struct sprd_uart_port *sup = platform_get_drvdata(dev);
  888. if (sup) {
  889. uart_remove_one_port(&sprd_uart_driver, &sup->port);
  890. sprd_port[sup->port.line] = NULL;
  891. sprd_rx_free_buf(sup);
  892. sprd_ports_num--;
  893. }
  894. if (!sprd_ports_num)
  895. uart_unregister_driver(&sprd_uart_driver);
  896. }
  897. static bool sprd_uart_is_console(struct uart_port *uport)
  898. {
  899. struct console *cons = sprd_uart_driver.cons;
  900. if ((cons && cons->index >= 0 && cons->index == uport->line) ||
  901. of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
  902. return true;
  903. return false;
  904. }
  905. static int sprd_clk_init(struct uart_port *uport)
  906. {
  907. struct clk *clk_uart, *clk_parent;
  908. struct sprd_uart_port *u = container_of(uport, struct sprd_uart_port, port);
  909. clk_uart = devm_clk_get(uport->dev, "uart");
  910. if (IS_ERR(clk_uart)) {
  911. dev_warn(uport->dev, "uart%d can't get uart clock\n",
  912. uport->line);
  913. clk_uart = NULL;
  914. }
  915. clk_parent = devm_clk_get(uport->dev, "source");
  916. if (IS_ERR(clk_parent)) {
  917. dev_warn(uport->dev, "uart%d can't get source clock\n",
  918. uport->line);
  919. clk_parent = NULL;
  920. }
  921. if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
  922. uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
  923. else
  924. uport->uartclk = clk_get_rate(clk_uart);
  925. u->clk = devm_clk_get(uport->dev, "enable");
  926. if (IS_ERR(u->clk)) {
  927. if (PTR_ERR(u->clk) == -EPROBE_DEFER)
  928. return -EPROBE_DEFER;
  929. dev_warn(uport->dev, "uart%d can't get enable clock\n",
  930. uport->line);
  931. /* To keep console alive even if the error occurred */
  932. if (!sprd_uart_is_console(uport))
  933. return PTR_ERR(u->clk);
  934. u->clk = NULL;
  935. }
  936. return 0;
  937. }
  938. static int sprd_probe(struct platform_device *pdev)
  939. {
  940. struct resource *res;
  941. struct uart_port *up;
  942. struct sprd_uart_port *sport;
  943. int irq;
  944. int index;
  945. int ret;
  946. index = of_alias_get_id(pdev->dev.of_node, "serial");
  947. if (index < 0 || index >= UART_NR_MAX) {
  948. dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
  949. return -EINVAL;
  950. }
  951. sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
  952. if (!sport)
  953. return -ENOMEM;
  954. up = &sport->port;
  955. up->dev = &pdev->dev;
  956. up->line = index;
  957. up->type = PORT_SPRD;
  958. up->iotype = UPIO_MEM;
  959. up->uartclk = SPRD_DEF_RATE;
  960. up->fifosize = SPRD_FIFO_SIZE;
  961. up->ops = &serial_sprd_ops;
  962. up->flags = UPF_BOOT_AUTOCONF;
  963. up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
  964. ret = sprd_clk_init(up);
  965. if (ret)
  966. return ret;
  967. up->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  968. if (IS_ERR(up->membase))
  969. return PTR_ERR(up->membase);
  970. up->mapbase = res->start;
  971. irq = platform_get_irq(pdev, 0);
  972. if (irq < 0)
  973. return irq;
  974. up->irq = irq;
  975. /*
  976. * Allocate one dma buffer to prepare for receive transfer, in case
  977. * memory allocation failure at runtime.
  978. */
  979. ret = sprd_rx_alloc_buf(sport);
  980. if (ret)
  981. return ret;
  982. if (!sprd_ports_num) {
  983. ret = uart_register_driver(&sprd_uart_driver);
  984. if (ret < 0) {
  985. pr_err("Failed to register SPRD-UART driver\n");
  986. goto free_rx_buf;
  987. }
  988. }
  989. sprd_ports_num++;
  990. sprd_port[index] = sport;
  991. ret = uart_add_one_port(&sprd_uart_driver, up);
  992. if (ret)
  993. goto clean_port;
  994. platform_set_drvdata(pdev, up);
  995. return 0;
  996. clean_port:
  997. sprd_port[index] = NULL;
  998. if (--sprd_ports_num == 0)
  999. uart_unregister_driver(&sprd_uart_driver);
  1000. free_rx_buf:
  1001. sprd_rx_free_buf(sport);
  1002. return ret;
  1003. }
  1004. #ifdef CONFIG_PM_SLEEP
  1005. static int sprd_suspend(struct device *dev)
  1006. {
  1007. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1008. uart_suspend_port(&sprd_uart_driver, &sup->port);
  1009. return 0;
  1010. }
  1011. static int sprd_resume(struct device *dev)
  1012. {
  1013. struct sprd_uart_port *sup = dev_get_drvdata(dev);
  1014. uart_resume_port(&sprd_uart_driver, &sup->port);
  1015. return 0;
  1016. }
  1017. #endif
  1018. static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
  1019. static const struct of_device_id serial_ids[] = {
  1020. {.compatible = "sprd,sc9836-uart",},
  1021. {}
  1022. };
  1023. MODULE_DEVICE_TABLE(of, serial_ids);
  1024. static struct platform_driver sprd_platform_driver = {
  1025. .probe = sprd_probe,
  1026. .remove_new = sprd_remove,
  1027. .driver = {
  1028. .name = "sprd_serial",
  1029. .of_match_table = serial_ids,
  1030. .pm = &sprd_pm_ops,
  1031. },
  1032. };
  1033. module_platform_driver(sprd_platform_driver);
  1034. MODULE_LICENSE("GPL v2");
  1035. MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");