xhci-dbgcap.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * xhci-dbgcap.c - xHCI debug capability support
  4. *
  5. * Copyright (C) 2017 Intel Corporation
  6. *
  7. * Author: Lu Baolu <baolu.lu@linux.intel.com>
  8. */
  9. #include <linux/bug.h>
  10. #include <linux/device.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/errno.h>
  13. #include <linux/kstrtox.h>
  14. #include <linux/list.h>
  15. #include <linux/nls.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/string.h>
  20. #include <linux/sysfs.h>
  21. #include <linux/types.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/io-64-nonatomic-lo-hi.h>
  24. #include <asm/byteorder.h>
  25. #include "xhci.h"
  26. #include "xhci-trace.h"
  27. #include "xhci-dbgcap.h"
  28. static void dbc_free_ctx(struct device *dev, struct xhci_container_ctx *ctx)
  29. {
  30. if (!ctx)
  31. return;
  32. dma_free_coherent(dev, ctx->size, ctx->bytes, ctx->dma);
  33. kfree(ctx);
  34. }
  35. /* we use only one segment for DbC rings */
  36. static void dbc_ring_free(struct device *dev, struct xhci_ring *ring)
  37. {
  38. if (!ring)
  39. return;
  40. if (ring->first_seg) {
  41. dma_free_coherent(dev, TRB_SEGMENT_SIZE,
  42. ring->first_seg->trbs,
  43. ring->first_seg->dma);
  44. kfree(ring->first_seg);
  45. }
  46. kfree(ring);
  47. }
  48. static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
  49. {
  50. struct usb_string_descriptor *s_desc;
  51. u32 string_length;
  52. /* Serial string: */
  53. s_desc = (struct usb_string_descriptor *)strings->serial;
  54. utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
  55. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  56. DBC_MAX_STRING_LENGTH);
  57. s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
  58. s_desc->bDescriptorType = USB_DT_STRING;
  59. string_length = s_desc->bLength;
  60. string_length <<= 8;
  61. /* Product string: */
  62. s_desc = (struct usb_string_descriptor *)strings->product;
  63. utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
  64. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  65. DBC_MAX_STRING_LENGTH);
  66. s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
  67. s_desc->bDescriptorType = USB_DT_STRING;
  68. string_length += s_desc->bLength;
  69. string_length <<= 8;
  70. /* Manufacture string: */
  71. s_desc = (struct usb_string_descriptor *)strings->manufacturer;
  72. utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
  73. strlen(DBC_STRING_MANUFACTURER),
  74. UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
  75. DBC_MAX_STRING_LENGTH);
  76. s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
  77. s_desc->bDescriptorType = USB_DT_STRING;
  78. string_length += s_desc->bLength;
  79. string_length <<= 8;
  80. /* String0: */
  81. strings->string0[0] = 4;
  82. strings->string0[1] = USB_DT_STRING;
  83. strings->string0[2] = 0x09;
  84. strings->string0[3] = 0x04;
  85. string_length += 4;
  86. return string_length;
  87. }
  88. static void xhci_dbc_init_ep_contexts(struct xhci_dbc *dbc)
  89. {
  90. struct xhci_ep_ctx *ep_ctx;
  91. unsigned int max_burst;
  92. dma_addr_t deq;
  93. max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
  94. /* Populate bulk out endpoint context: */
  95. ep_ctx = dbc_bulkout_ctx(dbc);
  96. deq = dbc_bulkout_enq(dbc);
  97. ep_ctx->ep_info = 0;
  98. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
  99. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
  100. /* Populate bulk in endpoint context: */
  101. ep_ctx = dbc_bulkin_ctx(dbc);
  102. deq = dbc_bulkin_enq(dbc);
  103. ep_ctx->ep_info = 0;
  104. ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
  105. ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
  106. }
  107. static void xhci_dbc_init_contexts(struct xhci_dbc *dbc, u32 string_length)
  108. {
  109. struct dbc_info_context *info;
  110. u32 dev_info;
  111. dma_addr_t dma;
  112. if (!dbc)
  113. return;
  114. /* Populate info Context: */
  115. info = (struct dbc_info_context *)dbc->ctx->bytes;
  116. dma = dbc->string_dma;
  117. info->string0 = cpu_to_le64(dma);
  118. info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
  119. info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
  120. info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
  121. info->length = cpu_to_le32(string_length);
  122. /* Populate bulk in and out endpoint contexts: */
  123. xhci_dbc_init_ep_contexts(dbc);
  124. /* Set DbC context and info registers: */
  125. lo_hi_writeq(dbc->ctx->dma, &dbc->regs->dccp);
  126. dev_info = (dbc->idVendor << 16) | dbc->bInterfaceProtocol;
  127. writel(dev_info, &dbc->regs->devinfo1);
  128. dev_info = (dbc->bcdDevice << 16) | dbc->idProduct;
  129. writel(dev_info, &dbc->regs->devinfo2);
  130. }
  131. static void xhci_dbc_giveback(struct dbc_request *req, int status)
  132. __releases(&dbc->lock)
  133. __acquires(&dbc->lock)
  134. {
  135. struct xhci_dbc *dbc = req->dbc;
  136. struct device *dev = dbc->dev;
  137. list_del_init(&req->list_pending);
  138. req->trb_dma = 0;
  139. req->trb = NULL;
  140. if (req->status == -EINPROGRESS)
  141. req->status = status;
  142. trace_xhci_dbc_giveback_request(req);
  143. dma_unmap_single(dev,
  144. req->dma,
  145. req->length,
  146. dbc_ep_dma_direction(req));
  147. /* Give back the transfer request: */
  148. spin_unlock(&dbc->lock);
  149. req->complete(dbc, req);
  150. spin_lock(&dbc->lock);
  151. }
  152. static void trb_to_noop(union xhci_trb *trb)
  153. {
  154. trb->generic.field[0] = 0;
  155. trb->generic.field[1] = 0;
  156. trb->generic.field[2] = 0;
  157. trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
  158. trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
  159. }
  160. static void xhci_dbc_flush_single_request(struct dbc_request *req)
  161. {
  162. trb_to_noop(req->trb);
  163. xhci_dbc_giveback(req, -ESHUTDOWN);
  164. }
  165. static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
  166. {
  167. struct dbc_request *req, *tmp;
  168. list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
  169. xhci_dbc_flush_single_request(req);
  170. }
  171. static void xhci_dbc_flush_requests(struct xhci_dbc *dbc)
  172. {
  173. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
  174. xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
  175. }
  176. struct dbc_request *
  177. dbc_alloc_request(struct xhci_dbc *dbc, unsigned int direction, gfp_t flags)
  178. {
  179. struct dbc_request *req;
  180. if (direction != BULK_IN &&
  181. direction != BULK_OUT)
  182. return NULL;
  183. if (!dbc)
  184. return NULL;
  185. req = kzalloc(sizeof(*req), flags);
  186. if (!req)
  187. return NULL;
  188. req->dbc = dbc;
  189. INIT_LIST_HEAD(&req->list_pending);
  190. INIT_LIST_HEAD(&req->list_pool);
  191. req->direction = direction;
  192. trace_xhci_dbc_alloc_request(req);
  193. return req;
  194. }
  195. void
  196. dbc_free_request(struct dbc_request *req)
  197. {
  198. trace_xhci_dbc_free_request(req);
  199. kfree(req);
  200. }
  201. static void
  202. xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
  203. u32 field2, u32 field3, u32 field4)
  204. {
  205. union xhci_trb *trb, *next;
  206. trb = ring->enqueue;
  207. trb->generic.field[0] = cpu_to_le32(field1);
  208. trb->generic.field[1] = cpu_to_le32(field2);
  209. trb->generic.field[2] = cpu_to_le32(field3);
  210. trb->generic.field[3] = cpu_to_le32(field4);
  211. trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
  212. ring->num_trbs_free--;
  213. next = ++(ring->enqueue);
  214. if (TRB_TYPE_LINK_LE32(next->link.control)) {
  215. next->link.control ^= cpu_to_le32(TRB_CYCLE);
  216. ring->enqueue = ring->enq_seg->trbs;
  217. ring->cycle_state ^= 1;
  218. }
  219. }
  220. static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
  221. struct dbc_request *req)
  222. {
  223. u64 addr;
  224. union xhci_trb *trb;
  225. unsigned int num_trbs;
  226. struct xhci_dbc *dbc = req->dbc;
  227. struct xhci_ring *ring = dep->ring;
  228. u32 length, control, cycle;
  229. num_trbs = count_trbs(req->dma, req->length);
  230. WARN_ON(num_trbs != 1);
  231. if (ring->num_trbs_free < num_trbs)
  232. return -EBUSY;
  233. addr = req->dma;
  234. trb = ring->enqueue;
  235. cycle = ring->cycle_state;
  236. length = TRB_LEN(req->length);
  237. control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
  238. if (cycle)
  239. control &= cpu_to_le32(~TRB_CYCLE);
  240. else
  241. control |= cpu_to_le32(TRB_CYCLE);
  242. req->trb = ring->enqueue;
  243. req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
  244. xhci_dbc_queue_trb(ring,
  245. lower_32_bits(addr),
  246. upper_32_bits(addr),
  247. length, control);
  248. /*
  249. * Add a barrier between writes of trb fields and flipping
  250. * the cycle bit:
  251. */
  252. wmb();
  253. if (cycle)
  254. trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
  255. else
  256. trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
  257. writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
  258. return 0;
  259. }
  260. static int
  261. dbc_ep_do_queue(struct dbc_request *req)
  262. {
  263. int ret;
  264. struct xhci_dbc *dbc = req->dbc;
  265. struct device *dev = dbc->dev;
  266. struct dbc_ep *dep = &dbc->eps[req->direction];
  267. if (!req->length || !req->buf)
  268. return -EINVAL;
  269. req->actual = 0;
  270. req->status = -EINPROGRESS;
  271. req->dma = dma_map_single(dev,
  272. req->buf,
  273. req->length,
  274. dbc_ep_dma_direction(dep));
  275. if (dma_mapping_error(dev, req->dma)) {
  276. dev_err(dbc->dev, "failed to map buffer\n");
  277. return -EFAULT;
  278. }
  279. ret = xhci_dbc_queue_bulk_tx(dep, req);
  280. if (ret) {
  281. dev_err(dbc->dev, "failed to queue trbs\n");
  282. dma_unmap_single(dev,
  283. req->dma,
  284. req->length,
  285. dbc_ep_dma_direction(dep));
  286. return -EFAULT;
  287. }
  288. list_add_tail(&req->list_pending, &dep->list_pending);
  289. return 0;
  290. }
  291. int dbc_ep_queue(struct dbc_request *req)
  292. {
  293. unsigned long flags;
  294. struct xhci_dbc *dbc = req->dbc;
  295. int ret = -ESHUTDOWN;
  296. if (!dbc)
  297. return -ENODEV;
  298. if (req->direction != BULK_IN &&
  299. req->direction != BULK_OUT)
  300. return -EINVAL;
  301. spin_lock_irqsave(&dbc->lock, flags);
  302. if (dbc->state == DS_CONFIGURED)
  303. ret = dbc_ep_do_queue(req);
  304. spin_unlock_irqrestore(&dbc->lock, flags);
  305. mod_delayed_work(system_wq, &dbc->event_work, 0);
  306. trace_xhci_dbc_queue_request(req);
  307. return ret;
  308. }
  309. static inline void xhci_dbc_do_eps_init(struct xhci_dbc *dbc, bool direction)
  310. {
  311. struct dbc_ep *dep;
  312. dep = &dbc->eps[direction];
  313. dep->dbc = dbc;
  314. dep->direction = direction;
  315. dep->ring = direction ? dbc->ring_in : dbc->ring_out;
  316. INIT_LIST_HEAD(&dep->list_pending);
  317. }
  318. static void xhci_dbc_eps_init(struct xhci_dbc *dbc)
  319. {
  320. xhci_dbc_do_eps_init(dbc, BULK_OUT);
  321. xhci_dbc_do_eps_init(dbc, BULK_IN);
  322. }
  323. static void xhci_dbc_eps_exit(struct xhci_dbc *dbc)
  324. {
  325. memset(dbc->eps, 0, sizeof_field(struct xhci_dbc, eps));
  326. }
  327. static int dbc_erst_alloc(struct device *dev, struct xhci_ring *evt_ring,
  328. struct xhci_erst *erst, gfp_t flags)
  329. {
  330. erst->entries = dma_alloc_coherent(dev, sizeof(*erst->entries),
  331. &erst->erst_dma_addr, flags);
  332. if (!erst->entries)
  333. return -ENOMEM;
  334. erst->num_entries = 1;
  335. erst->entries[0].seg_addr = cpu_to_le64(evt_ring->first_seg->dma);
  336. erst->entries[0].seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  337. erst->entries[0].rsvd = 0;
  338. return 0;
  339. }
  340. static void dbc_erst_free(struct device *dev, struct xhci_erst *erst)
  341. {
  342. dma_free_coherent(dev, sizeof(*erst->entries), erst->entries,
  343. erst->erst_dma_addr);
  344. erst->entries = NULL;
  345. }
  346. static struct xhci_container_ctx *
  347. dbc_alloc_ctx(struct device *dev, gfp_t flags)
  348. {
  349. struct xhci_container_ctx *ctx;
  350. ctx = kzalloc(sizeof(*ctx), flags);
  351. if (!ctx)
  352. return NULL;
  353. /* xhci 7.6.9, all three contexts; info, ep-out and ep-in. Each 64 bytes*/
  354. ctx->size = 3 * DBC_CONTEXT_SIZE;
  355. ctx->bytes = dma_alloc_coherent(dev, ctx->size, &ctx->dma, flags);
  356. if (!ctx->bytes) {
  357. kfree(ctx);
  358. return NULL;
  359. }
  360. return ctx;
  361. }
  362. static void xhci_dbc_ring_init(struct xhci_ring *ring)
  363. {
  364. struct xhci_segment *seg = ring->first_seg;
  365. /* clear all trbs on ring in case of old ring */
  366. memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
  367. /* Only event ring does not use link TRB */
  368. if (ring->type != TYPE_EVENT) {
  369. union xhci_trb *trb = &seg->trbs[TRBS_PER_SEGMENT - 1];
  370. trb->link.segment_ptr = cpu_to_le64(ring->first_seg->dma);
  371. trb->link.control = cpu_to_le32(LINK_TOGGLE | TRB_TYPE(TRB_LINK));
  372. }
  373. xhci_initialize_ring_info(ring, 1);
  374. }
  375. static int xhci_dbc_reinit_ep_rings(struct xhci_dbc *dbc)
  376. {
  377. struct xhci_ring *in_ring = dbc->eps[BULK_IN].ring;
  378. struct xhci_ring *out_ring = dbc->eps[BULK_OUT].ring;
  379. if (!in_ring || !out_ring || !dbc->ctx) {
  380. dev_warn(dbc->dev, "Can't re-init unallocated endpoints\n");
  381. return -ENODEV;
  382. }
  383. xhci_dbc_ring_init(in_ring);
  384. xhci_dbc_ring_init(out_ring);
  385. /* set ep context enqueue, dequeue, and cycle to initial values */
  386. xhci_dbc_init_ep_contexts(dbc);
  387. return 0;
  388. }
  389. static struct xhci_ring *
  390. xhci_dbc_ring_alloc(struct device *dev, enum xhci_ring_type type, gfp_t flags)
  391. {
  392. struct xhci_ring *ring;
  393. struct xhci_segment *seg;
  394. dma_addr_t dma;
  395. ring = kzalloc(sizeof(*ring), flags);
  396. if (!ring)
  397. return NULL;
  398. ring->num_segs = 1;
  399. ring->type = type;
  400. seg = kzalloc(sizeof(*seg), flags);
  401. if (!seg)
  402. goto seg_fail;
  403. ring->first_seg = seg;
  404. ring->last_seg = seg;
  405. seg->next = seg;
  406. seg->trbs = dma_alloc_coherent(dev, TRB_SEGMENT_SIZE, &dma, flags);
  407. if (!seg->trbs)
  408. goto dma_fail;
  409. seg->dma = dma;
  410. INIT_LIST_HEAD(&ring->td_list);
  411. xhci_dbc_ring_init(ring);
  412. return ring;
  413. dma_fail:
  414. kfree(seg);
  415. seg_fail:
  416. kfree(ring);
  417. return NULL;
  418. }
  419. static int xhci_dbc_mem_init(struct xhci_dbc *dbc, gfp_t flags)
  420. {
  421. int ret;
  422. dma_addr_t deq;
  423. u32 string_length;
  424. struct device *dev = dbc->dev;
  425. /* Allocate various rings for events and transfers: */
  426. dbc->ring_evt = xhci_dbc_ring_alloc(dev, TYPE_EVENT, flags);
  427. if (!dbc->ring_evt)
  428. goto evt_fail;
  429. dbc->ring_in = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
  430. if (!dbc->ring_in)
  431. goto in_fail;
  432. dbc->ring_out = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
  433. if (!dbc->ring_out)
  434. goto out_fail;
  435. /* Allocate and populate ERST: */
  436. ret = dbc_erst_alloc(dev, dbc->ring_evt, &dbc->erst, flags);
  437. if (ret)
  438. goto erst_fail;
  439. /* Allocate context data structure: */
  440. dbc->ctx = dbc_alloc_ctx(dev, flags); /* was sysdev, and is still */
  441. if (!dbc->ctx)
  442. goto ctx_fail;
  443. /* Allocate the string table: */
  444. dbc->string_size = sizeof(*dbc->string);
  445. dbc->string = dma_alloc_coherent(dev, dbc->string_size,
  446. &dbc->string_dma, flags);
  447. if (!dbc->string)
  448. goto string_fail;
  449. /* Setup ERST register: */
  450. writel(dbc->erst.num_entries, &dbc->regs->ersts);
  451. lo_hi_writeq(dbc->erst.erst_dma_addr, &dbc->regs->erstba);
  452. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  453. dbc->ring_evt->dequeue);
  454. lo_hi_writeq(deq, &dbc->regs->erdp);
  455. /* Setup strings and contexts: */
  456. string_length = xhci_dbc_populate_strings(dbc->string);
  457. xhci_dbc_init_contexts(dbc, string_length);
  458. xhci_dbc_eps_init(dbc);
  459. dbc->state = DS_INITIALIZED;
  460. return 0;
  461. string_fail:
  462. dbc_free_ctx(dev, dbc->ctx);
  463. dbc->ctx = NULL;
  464. ctx_fail:
  465. dbc_erst_free(dev, &dbc->erst);
  466. erst_fail:
  467. dbc_ring_free(dev, dbc->ring_out);
  468. dbc->ring_out = NULL;
  469. out_fail:
  470. dbc_ring_free(dev, dbc->ring_in);
  471. dbc->ring_in = NULL;
  472. in_fail:
  473. dbc_ring_free(dev, dbc->ring_evt);
  474. dbc->ring_evt = NULL;
  475. evt_fail:
  476. return -ENOMEM;
  477. }
  478. static void xhci_dbc_mem_cleanup(struct xhci_dbc *dbc)
  479. {
  480. if (!dbc)
  481. return;
  482. xhci_dbc_eps_exit(dbc);
  483. dma_free_coherent(dbc->dev, dbc->string_size, dbc->string, dbc->string_dma);
  484. dbc->string = NULL;
  485. dbc_free_ctx(dbc->dev, dbc->ctx);
  486. dbc->ctx = NULL;
  487. dbc_erst_free(dbc->dev, &dbc->erst);
  488. dbc_ring_free(dbc->dev, dbc->ring_out);
  489. dbc_ring_free(dbc->dev, dbc->ring_in);
  490. dbc_ring_free(dbc->dev, dbc->ring_evt);
  491. dbc->ring_in = NULL;
  492. dbc->ring_out = NULL;
  493. dbc->ring_evt = NULL;
  494. }
  495. static int xhci_do_dbc_start(struct xhci_dbc *dbc)
  496. {
  497. int ret;
  498. u32 ctrl;
  499. if (dbc->state != DS_DISABLED)
  500. return -EINVAL;
  501. writel(0, &dbc->regs->control);
  502. ret = xhci_handshake(&dbc->regs->control,
  503. DBC_CTRL_DBC_ENABLE,
  504. 0, 1000);
  505. if (ret)
  506. return ret;
  507. ret = xhci_dbc_mem_init(dbc, GFP_ATOMIC);
  508. if (ret)
  509. return ret;
  510. ctrl = readl(&dbc->regs->control);
  511. writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
  512. &dbc->regs->control);
  513. ret = xhci_handshake(&dbc->regs->control,
  514. DBC_CTRL_DBC_ENABLE,
  515. DBC_CTRL_DBC_ENABLE, 1000);
  516. if (ret)
  517. return ret;
  518. dbc->state = DS_ENABLED;
  519. return 0;
  520. }
  521. static int xhci_do_dbc_stop(struct xhci_dbc *dbc)
  522. {
  523. if (dbc->state == DS_DISABLED)
  524. return -EINVAL;
  525. writel(0, &dbc->regs->control);
  526. dbc->state = DS_DISABLED;
  527. return 0;
  528. }
  529. static int xhci_dbc_start(struct xhci_dbc *dbc)
  530. {
  531. int ret;
  532. unsigned long flags;
  533. WARN_ON(!dbc);
  534. pm_runtime_get_sync(dbc->dev); /* note this was self.controller */
  535. spin_lock_irqsave(&dbc->lock, flags);
  536. ret = xhci_do_dbc_start(dbc);
  537. spin_unlock_irqrestore(&dbc->lock, flags);
  538. if (ret) {
  539. pm_runtime_put(dbc->dev); /* note this was self.controller */
  540. return ret;
  541. }
  542. return mod_delayed_work(system_wq, &dbc->event_work,
  543. msecs_to_jiffies(dbc->poll_interval));
  544. }
  545. static void xhci_dbc_stop(struct xhci_dbc *dbc)
  546. {
  547. int ret;
  548. unsigned long flags;
  549. WARN_ON(!dbc);
  550. switch (dbc->state) {
  551. case DS_DISABLED:
  552. return;
  553. case DS_CONFIGURED:
  554. spin_lock(&dbc->lock);
  555. xhci_dbc_flush_requests(dbc);
  556. spin_unlock(&dbc->lock);
  557. if (dbc->driver->disconnect)
  558. dbc->driver->disconnect(dbc);
  559. break;
  560. default:
  561. break;
  562. }
  563. cancel_delayed_work_sync(&dbc->event_work);
  564. spin_lock_irqsave(&dbc->lock, flags);
  565. ret = xhci_do_dbc_stop(dbc);
  566. spin_unlock_irqrestore(&dbc->lock, flags);
  567. if (ret)
  568. return;
  569. xhci_dbc_mem_cleanup(dbc);
  570. pm_runtime_put_sync(dbc->dev); /* note, was self.controller */
  571. }
  572. static void
  573. handle_ep_halt_changes(struct xhci_dbc *dbc, struct dbc_ep *dep, bool halted)
  574. {
  575. if (halted) {
  576. dev_info(dbc->dev, "DbC Endpoint halted\n");
  577. dep->halted = 1;
  578. } else if (dep->halted) {
  579. dev_info(dbc->dev, "DbC Endpoint halt cleared\n");
  580. dep->halted = 0;
  581. if (!list_empty(&dep->list_pending))
  582. writel(DBC_DOOR_BELL_TARGET(dep->direction),
  583. &dbc->regs->doorbell);
  584. }
  585. }
  586. static void
  587. dbc_handle_port_status(struct xhci_dbc *dbc, union xhci_trb *event)
  588. {
  589. u32 portsc;
  590. portsc = readl(&dbc->regs->portsc);
  591. if (portsc & DBC_PORTSC_CONN_CHANGE)
  592. dev_info(dbc->dev, "DbC port connect change\n");
  593. if (portsc & DBC_PORTSC_RESET_CHANGE)
  594. dev_info(dbc->dev, "DbC port reset change\n");
  595. if (portsc & DBC_PORTSC_LINK_CHANGE)
  596. dev_info(dbc->dev, "DbC port link status change\n");
  597. if (portsc & DBC_PORTSC_CONFIG_CHANGE)
  598. dev_info(dbc->dev, "DbC config error change\n");
  599. /* Port reset change bit will be cleared in other place: */
  600. writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
  601. }
  602. static void dbc_handle_xfer_event(struct xhci_dbc *dbc, union xhci_trb *event)
  603. {
  604. struct dbc_ep *dep;
  605. struct xhci_ring *ring;
  606. int ep_id;
  607. int status;
  608. struct xhci_ep_ctx *ep_ctx;
  609. u32 comp_code;
  610. size_t remain_length;
  611. struct dbc_request *req = NULL, *r;
  612. comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
  613. remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
  614. ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
  615. dep = (ep_id == EPID_OUT) ?
  616. get_out_ep(dbc) : get_in_ep(dbc);
  617. ep_ctx = (ep_id == EPID_OUT) ?
  618. dbc_bulkout_ctx(dbc) : dbc_bulkin_ctx(dbc);
  619. ring = dep->ring;
  620. /* Match the pending request: */
  621. list_for_each_entry(r, &dep->list_pending, list_pending) {
  622. if (r->trb_dma == event->trans_event.buffer) {
  623. req = r;
  624. break;
  625. }
  626. if (r->status == -COMP_STALL_ERROR) {
  627. dev_warn(dbc->dev, "Give back stale stalled req\n");
  628. ring->num_trbs_free++;
  629. xhci_dbc_giveback(r, 0);
  630. }
  631. }
  632. if (!req) {
  633. dev_warn(dbc->dev, "no matched request\n");
  634. return;
  635. }
  636. trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
  637. switch (comp_code) {
  638. case COMP_SUCCESS:
  639. remain_length = 0;
  640. fallthrough;
  641. case COMP_SHORT_PACKET:
  642. status = 0;
  643. break;
  644. case COMP_TRB_ERROR:
  645. case COMP_BABBLE_DETECTED_ERROR:
  646. case COMP_USB_TRANSACTION_ERROR:
  647. dev_warn(dbc->dev, "tx error %d detected\n", comp_code);
  648. status = -comp_code;
  649. break;
  650. case COMP_STALL_ERROR:
  651. dev_warn(dbc->dev, "Stall error at bulk TRB %llx, remaining %zu, ep deq %llx\n",
  652. event->trans_event.buffer, remain_length, ep_ctx->deq);
  653. status = 0;
  654. dep->halted = 1;
  655. /*
  656. * xHC DbC may trigger a STALL bulk xfer event when host sends a
  657. * ClearFeature(ENDPOINT_HALT) request even if there wasn't an
  658. * active bulk transfer.
  659. *
  660. * Don't give back this transfer request as hardware will later
  661. * start processing TRBs starting from this 'STALLED' TRB,
  662. * causing TRBs and requests to be out of sync.
  663. *
  664. * If STALL event shows some bytes were transferred then assume
  665. * it's an actual transfer issue and give back the request.
  666. * In this case mark the TRB as No-Op to avoid hw from using the
  667. * TRB again.
  668. */
  669. if ((ep_ctx->deq & ~TRB_CYCLE) == event->trans_event.buffer) {
  670. dev_dbg(dbc->dev, "Ep stopped on Stalled TRB\n");
  671. if (remain_length == req->length) {
  672. dev_dbg(dbc->dev, "Spurious stall event, keep req\n");
  673. req->status = -COMP_STALL_ERROR;
  674. req->actual = 0;
  675. return;
  676. }
  677. dev_dbg(dbc->dev, "Give back stalled req, but turn TRB to No-op\n");
  678. trb_to_noop(req->trb);
  679. }
  680. break;
  681. default:
  682. dev_err(dbc->dev, "unknown tx error %d\n", comp_code);
  683. status = -comp_code;
  684. break;
  685. }
  686. ring->num_trbs_free++;
  687. req->actual = req->length - remain_length;
  688. xhci_dbc_giveback(req, status);
  689. }
  690. static void inc_evt_deq(struct xhci_ring *ring)
  691. {
  692. /* If on the last TRB of the segment go back to the beginning */
  693. if (ring->dequeue == &ring->deq_seg->trbs[TRBS_PER_SEGMENT - 1]) {
  694. ring->cycle_state ^= 1;
  695. ring->dequeue = ring->deq_seg->trbs;
  696. return;
  697. }
  698. ring->dequeue++;
  699. }
  700. static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
  701. {
  702. dma_addr_t deq;
  703. union xhci_trb *evt;
  704. enum evtreturn ret = EVT_DONE;
  705. u32 ctrl, portsc;
  706. bool update_erdp = false;
  707. /* DbC state machine: */
  708. switch (dbc->state) {
  709. case DS_DISABLED:
  710. case DS_INITIALIZED:
  711. return EVT_ERR;
  712. case DS_ENABLED:
  713. portsc = readl(&dbc->regs->portsc);
  714. if (portsc & DBC_PORTSC_CONN_STATUS) {
  715. dbc->state = DS_CONNECTED;
  716. dev_info(dbc->dev, "DbC connected\n");
  717. }
  718. return EVT_DONE;
  719. case DS_CONNECTED:
  720. ctrl = readl(&dbc->regs->control);
  721. if (ctrl & DBC_CTRL_DBC_RUN) {
  722. dbc->state = DS_CONFIGURED;
  723. dev_info(dbc->dev, "DbC configured\n");
  724. portsc = readl(&dbc->regs->portsc);
  725. writel(portsc, &dbc->regs->portsc);
  726. ret = EVT_GSER;
  727. break;
  728. }
  729. return EVT_DONE;
  730. case DS_CONFIGURED:
  731. /* Handle cable unplug event: */
  732. portsc = readl(&dbc->regs->portsc);
  733. if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
  734. !(portsc & DBC_PORTSC_CONN_STATUS)) {
  735. dev_info(dbc->dev, "DbC cable unplugged\n");
  736. dbc->state = DS_ENABLED;
  737. xhci_dbc_flush_requests(dbc);
  738. xhci_dbc_reinit_ep_rings(dbc);
  739. return EVT_DISC;
  740. }
  741. /* Handle debug port reset event: */
  742. if (portsc & DBC_PORTSC_RESET_CHANGE) {
  743. dev_info(dbc->dev, "DbC port reset\n");
  744. writel(portsc, &dbc->regs->portsc);
  745. dbc->state = DS_ENABLED;
  746. xhci_dbc_flush_requests(dbc);
  747. xhci_dbc_reinit_ep_rings(dbc);
  748. return EVT_DISC;
  749. }
  750. /* Check and handle changes in endpoint halt status */
  751. ctrl = readl(&dbc->regs->control);
  752. handle_ep_halt_changes(dbc, get_in_ep(dbc), ctrl & DBC_CTRL_HALT_IN_TR);
  753. handle_ep_halt_changes(dbc, get_out_ep(dbc), ctrl & DBC_CTRL_HALT_OUT_TR);
  754. /* Clear DbC run change bit: */
  755. if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
  756. writel(ctrl, &dbc->regs->control);
  757. ctrl = readl(&dbc->regs->control);
  758. }
  759. break;
  760. default:
  761. dev_err(dbc->dev, "Unknown DbC state %d\n", dbc->state);
  762. break;
  763. }
  764. /* Handle the events in the event ring: */
  765. evt = dbc->ring_evt->dequeue;
  766. while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
  767. dbc->ring_evt->cycle_state) {
  768. /*
  769. * Add a barrier between reading the cycle flag and any
  770. * reads of the event's flags/data below:
  771. */
  772. rmb();
  773. trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
  774. switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
  775. case TRB_TYPE(TRB_PORT_STATUS):
  776. dbc_handle_port_status(dbc, evt);
  777. break;
  778. case TRB_TYPE(TRB_TRANSFER):
  779. dbc_handle_xfer_event(dbc, evt);
  780. if (ret != EVT_GSER)
  781. ret = EVT_XFER_DONE;
  782. break;
  783. default:
  784. break;
  785. }
  786. inc_evt_deq(dbc->ring_evt);
  787. evt = dbc->ring_evt->dequeue;
  788. update_erdp = true;
  789. }
  790. /* Update event ring dequeue pointer: */
  791. if (update_erdp) {
  792. deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
  793. dbc->ring_evt->dequeue);
  794. lo_hi_writeq(deq, &dbc->regs->erdp);
  795. }
  796. return ret;
  797. }
  798. static void xhci_dbc_handle_events(struct work_struct *work)
  799. {
  800. enum evtreturn evtr;
  801. struct xhci_dbc *dbc;
  802. unsigned long flags;
  803. unsigned int poll_interval;
  804. unsigned long busypoll_timelimit;
  805. dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
  806. poll_interval = dbc->poll_interval;
  807. spin_lock_irqsave(&dbc->lock, flags);
  808. evtr = xhci_dbc_do_handle_events(dbc);
  809. spin_unlock_irqrestore(&dbc->lock, flags);
  810. switch (evtr) {
  811. case EVT_GSER:
  812. if (dbc->driver->configure)
  813. dbc->driver->configure(dbc);
  814. break;
  815. case EVT_DISC:
  816. if (dbc->driver->disconnect)
  817. dbc->driver->disconnect(dbc);
  818. break;
  819. case EVT_DONE:
  820. /*
  821. * Set fast poll rate if there are pending out transfers, or
  822. * a transfer was recently processed
  823. */
  824. busypoll_timelimit = dbc->xfer_timestamp +
  825. msecs_to_jiffies(DBC_XFER_INACTIVITY_TIMEOUT);
  826. if (!list_empty(&dbc->eps[BULK_OUT].list_pending) ||
  827. time_is_after_jiffies(busypoll_timelimit))
  828. poll_interval = 0;
  829. break;
  830. case EVT_XFER_DONE:
  831. dbc->xfer_timestamp = jiffies;
  832. poll_interval = 0;
  833. break;
  834. default:
  835. dev_info(dbc->dev, "stop handling dbc events\n");
  836. return;
  837. }
  838. mod_delayed_work(system_wq, &dbc->event_work,
  839. msecs_to_jiffies(poll_interval));
  840. }
  841. static const char * const dbc_state_strings[DS_MAX] = {
  842. [DS_DISABLED] = "disabled",
  843. [DS_INITIALIZED] = "initialized",
  844. [DS_ENABLED] = "enabled",
  845. [DS_CONNECTED] = "connected",
  846. [DS_CONFIGURED] = "configured",
  847. };
  848. static ssize_t dbc_show(struct device *dev,
  849. struct device_attribute *attr,
  850. char *buf)
  851. {
  852. struct xhci_dbc *dbc;
  853. struct xhci_hcd *xhci;
  854. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  855. dbc = xhci->dbc;
  856. if (dbc->state >= ARRAY_SIZE(dbc_state_strings))
  857. return sysfs_emit(buf, "unknown\n");
  858. return sysfs_emit(buf, "%s\n", dbc_state_strings[dbc->state]);
  859. }
  860. static ssize_t dbc_store(struct device *dev,
  861. struct device_attribute *attr,
  862. const char *buf, size_t count)
  863. {
  864. struct xhci_hcd *xhci;
  865. struct xhci_dbc *dbc;
  866. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  867. dbc = xhci->dbc;
  868. if (sysfs_streq(buf, "enable"))
  869. xhci_dbc_start(dbc);
  870. else if (sysfs_streq(buf, "disable"))
  871. xhci_dbc_stop(dbc);
  872. else
  873. return -EINVAL;
  874. return count;
  875. }
  876. static ssize_t dbc_idVendor_show(struct device *dev,
  877. struct device_attribute *attr,
  878. char *buf)
  879. {
  880. struct xhci_dbc *dbc;
  881. struct xhci_hcd *xhci;
  882. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  883. dbc = xhci->dbc;
  884. return sysfs_emit(buf, "%04x\n", dbc->idVendor);
  885. }
  886. static ssize_t dbc_idVendor_store(struct device *dev,
  887. struct device_attribute *attr,
  888. const char *buf, size_t size)
  889. {
  890. struct xhci_dbc *dbc;
  891. struct xhci_hcd *xhci;
  892. void __iomem *ptr;
  893. u16 value;
  894. u32 dev_info;
  895. int ret;
  896. ret = kstrtou16(buf, 0, &value);
  897. if (ret)
  898. return ret;
  899. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  900. dbc = xhci->dbc;
  901. if (dbc->state != DS_DISABLED)
  902. return -EBUSY;
  903. dbc->idVendor = value;
  904. ptr = &dbc->regs->devinfo1;
  905. dev_info = readl(ptr);
  906. dev_info = (dev_info & ~(0xffffu << 16)) | (value << 16);
  907. writel(dev_info, ptr);
  908. return size;
  909. }
  910. static ssize_t dbc_idProduct_show(struct device *dev,
  911. struct device_attribute *attr,
  912. char *buf)
  913. {
  914. struct xhci_dbc *dbc;
  915. struct xhci_hcd *xhci;
  916. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  917. dbc = xhci->dbc;
  918. return sysfs_emit(buf, "%04x\n", dbc->idProduct);
  919. }
  920. static ssize_t dbc_idProduct_store(struct device *dev,
  921. struct device_attribute *attr,
  922. const char *buf, size_t size)
  923. {
  924. struct xhci_dbc *dbc;
  925. struct xhci_hcd *xhci;
  926. void __iomem *ptr;
  927. u32 dev_info;
  928. u16 value;
  929. int ret;
  930. ret = kstrtou16(buf, 0, &value);
  931. if (ret)
  932. return ret;
  933. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  934. dbc = xhci->dbc;
  935. if (dbc->state != DS_DISABLED)
  936. return -EBUSY;
  937. dbc->idProduct = value;
  938. ptr = &dbc->regs->devinfo2;
  939. dev_info = readl(ptr);
  940. dev_info = (dev_info & ~(0xffffu)) | value;
  941. writel(dev_info, ptr);
  942. return size;
  943. }
  944. static ssize_t dbc_bcdDevice_show(struct device *dev,
  945. struct device_attribute *attr,
  946. char *buf)
  947. {
  948. struct xhci_dbc *dbc;
  949. struct xhci_hcd *xhci;
  950. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  951. dbc = xhci->dbc;
  952. return sysfs_emit(buf, "%04x\n", dbc->bcdDevice);
  953. }
  954. static ssize_t dbc_bcdDevice_store(struct device *dev,
  955. struct device_attribute *attr,
  956. const char *buf, size_t size)
  957. {
  958. struct xhci_dbc *dbc;
  959. struct xhci_hcd *xhci;
  960. void __iomem *ptr;
  961. u32 dev_info;
  962. u16 value;
  963. int ret;
  964. ret = kstrtou16(buf, 0, &value);
  965. if (ret)
  966. return ret;
  967. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  968. dbc = xhci->dbc;
  969. if (dbc->state != DS_DISABLED)
  970. return -EBUSY;
  971. dbc->bcdDevice = value;
  972. ptr = &dbc->regs->devinfo2;
  973. dev_info = readl(ptr);
  974. dev_info = (dev_info & ~(0xffffu << 16)) | (value << 16);
  975. writel(dev_info, ptr);
  976. return size;
  977. }
  978. static ssize_t dbc_bInterfaceProtocol_show(struct device *dev,
  979. struct device_attribute *attr,
  980. char *buf)
  981. {
  982. struct xhci_dbc *dbc;
  983. struct xhci_hcd *xhci;
  984. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  985. dbc = xhci->dbc;
  986. return sysfs_emit(buf, "%02x\n", dbc->bInterfaceProtocol);
  987. }
  988. static ssize_t dbc_bInterfaceProtocol_store(struct device *dev,
  989. struct device_attribute *attr,
  990. const char *buf, size_t size)
  991. {
  992. struct xhci_dbc *dbc;
  993. struct xhci_hcd *xhci;
  994. void __iomem *ptr;
  995. u32 dev_info;
  996. u8 value;
  997. int ret;
  998. /* bInterfaceProtocol is 8 bit, but... */
  999. ret = kstrtou8(buf, 0, &value);
  1000. if (ret)
  1001. return ret;
  1002. /* ...xhci only supports values 0 and 1 */
  1003. if (value > 1)
  1004. return -EINVAL;
  1005. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  1006. dbc = xhci->dbc;
  1007. if (dbc->state != DS_DISABLED)
  1008. return -EBUSY;
  1009. dbc->bInterfaceProtocol = value;
  1010. ptr = &dbc->regs->devinfo1;
  1011. dev_info = readl(ptr);
  1012. dev_info = (dev_info & ~(0xffu)) | value;
  1013. writel(dev_info, ptr);
  1014. return size;
  1015. }
  1016. static ssize_t dbc_poll_interval_ms_show(struct device *dev,
  1017. struct device_attribute *attr,
  1018. char *buf)
  1019. {
  1020. struct xhci_dbc *dbc;
  1021. struct xhci_hcd *xhci;
  1022. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  1023. dbc = xhci->dbc;
  1024. return sysfs_emit(buf, "%u\n", dbc->poll_interval);
  1025. }
  1026. static ssize_t dbc_poll_interval_ms_store(struct device *dev,
  1027. struct device_attribute *attr,
  1028. const char *buf, size_t size)
  1029. {
  1030. struct xhci_dbc *dbc;
  1031. struct xhci_hcd *xhci;
  1032. u32 value;
  1033. int ret;
  1034. ret = kstrtou32(buf, 0, &value);
  1035. if (ret || value > DBC_POLL_INTERVAL_MAX)
  1036. return -EINVAL;
  1037. xhci = hcd_to_xhci(dev_get_drvdata(dev));
  1038. dbc = xhci->dbc;
  1039. dbc->poll_interval = value;
  1040. mod_delayed_work(system_wq, &dbc->event_work, 0);
  1041. return size;
  1042. }
  1043. static DEVICE_ATTR_RW(dbc);
  1044. static DEVICE_ATTR_RW(dbc_idVendor);
  1045. static DEVICE_ATTR_RW(dbc_idProduct);
  1046. static DEVICE_ATTR_RW(dbc_bcdDevice);
  1047. static DEVICE_ATTR_RW(dbc_bInterfaceProtocol);
  1048. static DEVICE_ATTR_RW(dbc_poll_interval_ms);
  1049. static struct attribute *dbc_dev_attrs[] = {
  1050. &dev_attr_dbc.attr,
  1051. &dev_attr_dbc_idVendor.attr,
  1052. &dev_attr_dbc_idProduct.attr,
  1053. &dev_attr_dbc_bcdDevice.attr,
  1054. &dev_attr_dbc_bInterfaceProtocol.attr,
  1055. &dev_attr_dbc_poll_interval_ms.attr,
  1056. NULL
  1057. };
  1058. ATTRIBUTE_GROUPS(dbc_dev);
  1059. struct xhci_dbc *
  1060. xhci_alloc_dbc(struct device *dev, void __iomem *base, const struct dbc_driver *driver)
  1061. {
  1062. struct xhci_dbc *dbc;
  1063. int ret;
  1064. dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
  1065. if (!dbc)
  1066. return NULL;
  1067. dbc->regs = base;
  1068. dbc->dev = dev;
  1069. dbc->driver = driver;
  1070. dbc->idProduct = DBC_PRODUCT_ID;
  1071. dbc->idVendor = DBC_VENDOR_ID;
  1072. dbc->bcdDevice = DBC_DEVICE_REV;
  1073. dbc->bInterfaceProtocol = DBC_PROTOCOL;
  1074. dbc->poll_interval = DBC_POLL_INTERVAL_DEFAULT;
  1075. if (readl(&dbc->regs->control) & DBC_CTRL_DBC_ENABLE)
  1076. goto err;
  1077. INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
  1078. spin_lock_init(&dbc->lock);
  1079. ret = sysfs_create_groups(&dev->kobj, dbc_dev_groups);
  1080. if (ret)
  1081. goto err;
  1082. return dbc;
  1083. err:
  1084. kfree(dbc);
  1085. return NULL;
  1086. }
  1087. /* undo what xhci_alloc_dbc() did */
  1088. void xhci_dbc_remove(struct xhci_dbc *dbc)
  1089. {
  1090. if (!dbc)
  1091. return;
  1092. /* stop hw, stop wq and call dbc->ops->stop() */
  1093. xhci_dbc_stop(dbc);
  1094. /* remove sysfs files */
  1095. sysfs_remove_groups(&dbc->dev->kobj, dbc_dev_groups);
  1096. kfree(dbc);
  1097. }
  1098. int xhci_create_dbc_dev(struct xhci_hcd *xhci)
  1099. {
  1100. struct device *dev;
  1101. void __iomem *base;
  1102. int ret;
  1103. int dbc_cap_offs;
  1104. /* create all parameters needed resembling a dbc device */
  1105. dev = xhci_to_hcd(xhci)->self.controller;
  1106. base = &xhci->cap_regs->hc_capbase;
  1107. dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
  1108. if (!dbc_cap_offs)
  1109. return -ENODEV;
  1110. /* already allocated and in use */
  1111. if (xhci->dbc)
  1112. return -EBUSY;
  1113. ret = xhci_dbc_tty_probe(dev, base + dbc_cap_offs, xhci);
  1114. return ret;
  1115. }
  1116. void xhci_remove_dbc_dev(struct xhci_hcd *xhci)
  1117. {
  1118. unsigned long flags;
  1119. if (!xhci->dbc)
  1120. return;
  1121. xhci_dbc_tty_remove(xhci->dbc);
  1122. spin_lock_irqsave(&xhci->lock, flags);
  1123. xhci->dbc = NULL;
  1124. spin_unlock_irqrestore(&xhci->lock, flags);
  1125. }
  1126. #ifdef CONFIG_PM
  1127. int xhci_dbc_suspend(struct xhci_hcd *xhci)
  1128. {
  1129. struct xhci_dbc *dbc = xhci->dbc;
  1130. if (!dbc)
  1131. return 0;
  1132. switch (dbc->state) {
  1133. case DS_ENABLED:
  1134. case DS_CONNECTED:
  1135. case DS_CONFIGURED:
  1136. dbc->resume_required = 1;
  1137. break;
  1138. default:
  1139. break;
  1140. }
  1141. xhci_dbc_stop(dbc);
  1142. return 0;
  1143. }
  1144. int xhci_dbc_resume(struct xhci_hcd *xhci)
  1145. {
  1146. int ret = 0;
  1147. struct xhci_dbc *dbc = xhci->dbc;
  1148. if (!dbc)
  1149. return 0;
  1150. if (dbc->resume_required) {
  1151. dbc->resume_required = 0;
  1152. xhci_dbc_start(dbc);
  1153. }
  1154. return ret;
  1155. }
  1156. #endif /* CONFIG_PM */
  1157. int xhci_dbc_init(void)
  1158. {
  1159. return dbc_tty_init();
  1160. }
  1161. void xhci_dbc_exit(void)
  1162. {
  1163. dbc_tty_exit();
  1164. }