| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172 |
- /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
- /*
- * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
- * Author: Huqiang Qin <huqiang.qin@amlogic.com>
- */
- #ifndef _DT_BINDINGS_AMLOGIC_C3_GPIO_H
- #define _DT_BINDINGS_AMLOGIC_C3_GPIO_H
- #define GPIOE_0 0
- #define GPIOE_1 1
- #define GPIOE_2 2
- #define GPIOE_3 3
- #define GPIOE_4 4
- #define GPIOB_0 5
- #define GPIOB_1 6
- #define GPIOB_2 7
- #define GPIOB_3 8
- #define GPIOB_4 9
- #define GPIOB_5 10
- #define GPIOB_6 11
- #define GPIOB_7 12
- #define GPIOB_8 13
- #define GPIOB_9 14
- #define GPIOB_10 15
- #define GPIOB_11 16
- #define GPIOB_12 17
- #define GPIOB_13 18
- #define GPIOB_14 19
- #define GPIOC_0 20
- #define GPIOC_1 21
- #define GPIOC_2 22
- #define GPIOC_3 23
- #define GPIOC_4 24
- #define GPIOC_5 25
- #define GPIOC_6 26
- #define GPIOX_0 27
- #define GPIOX_1 28
- #define GPIOX_2 29
- #define GPIOX_3 30
- #define GPIOX_4 31
- #define GPIOX_5 32
- #define GPIOX_6 33
- #define GPIOX_7 34
- #define GPIOX_8 35
- #define GPIOX_9 36
- #define GPIOX_10 37
- #define GPIOX_11 38
- #define GPIOX_12 39
- #define GPIOX_13 40
- #define GPIOD_0 41
- #define GPIOD_1 42
- #define GPIOD_2 43
- #define GPIOD_3 44
- #define GPIOD_4 45
- #define GPIOD_5 46
- #define GPIOD_6 47
- #define GPIOA_0 48
- #define GPIOA_1 49
- #define GPIOA_2 50
- #define GPIOA_3 51
- #define GPIOA_4 52
- #define GPIOA_5 53
- #define GPIO_TEST_N 54
- #endif /* _DT_BINDINGS_AMLOGIC_C3_GPIO_H */
|