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- /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
- #ifndef _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
- #define _DT_BINDINGS_MEDIATEK_MT6357_AUXADC_H
- /* ADC Channel Index */
- #define MT6357_AUXADC_BATADC 0
- #define MT6357_AUXADC_ISENSE 1
- #define MT6357_AUXADC_VCDT 2
- #define MT6357_AUXADC_BAT_TEMP 3
- #define MT6357_AUXADC_CHIP_TEMP 4
- #define MT6357_AUXADC_ACCDET 5
- #define MT6357_AUXADC_VDCXO 6
- #define MT6357_AUXADC_TSX_TEMP 7
- #define MT6357_AUXADC_HPOFS_CAL 8
- #define MT6357_AUXADC_DCXO_TEMP 9
- #define MT6357_AUXADC_VCORE_TEMP 10
- #define MT6357_AUXADC_VPROC_TEMP 11
- #define MT6357_AUXADC_VBAT 12
- #endif
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