mediatek,mt8188-gce.h 44 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967
  1. /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
  2. /*
  3. * Copyright (c) 2022 MediaTek Inc.
  4. *
  5. */
  6. #ifndef _DT_BINDINGS_GCE_MT8188_H
  7. #define _DT_BINDINGS_GCE_MT8188_H
  8. #define CMDQ_THR_PRIO_LOWEST 0
  9. #define CMDQ_THR_PRIO_1 1
  10. #define CMDQ_THR_PRIO_2 2
  11. #define CMDQ_THR_PRIO_3 3
  12. #define CMDQ_THR_PRIO_4 4
  13. #define CMDQ_THR_PRIO_5 5
  14. #define CMDQ_THR_PRIO_6 6
  15. #define CMDQ_THR_PRIO_HIGHEST 7
  16. #define SUBSYS_1400XXXX 0
  17. #define SUBSYS_1401XXXX 1
  18. #define SUBSYS_1402XXXX 2
  19. #define SUBSYS_1c00XXXX 3
  20. #define SUBSYS_1c01XXXX 4
  21. #define SUBSYS_1c02XXXX 5
  22. #define SUBSYS_1c10XXXX 6
  23. #define SUBSYS_1c11XXXX 7
  24. #define SUBSYS_1c12XXXX 8
  25. #define SUBSYS_14f0XXXX 9
  26. #define SUBSYS_14f1XXXX 10
  27. #define SUBSYS_14f2XXXX 11
  28. #define SUBSYS_1800XXXX 12
  29. #define SUBSYS_1801XXXX 13
  30. #define SUBSYS_1802XXXX 14
  31. #define SUBSYS_1803XXXX 15
  32. #define SUBSYS_1032XXXX 16
  33. #define SUBSYS_1033XXXX 17
  34. #define SUBSYS_1600XXXX 18
  35. #define SUBSYS_1601XXXX 19
  36. #define SUBSYS_14e0XXXX 20
  37. #define SUBSYS_1c20XXXX 21
  38. #define SUBSYS_1c30XXXX 22
  39. #define SUBSYS_1c40XXXX 23
  40. #define SUBSYS_1c50XXXX 24
  41. #define SUBSYS_1c60XXXX 25
  42. #define SUBSYS_NO_SUPPORT 99
  43. #define CMDQ_EVENT_IMG_SOF 0
  44. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_0 1
  45. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_1 2
  46. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_2 3
  47. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_3 4
  48. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_4 5
  49. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_5 6
  50. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_6 7
  51. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_7 8
  52. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_8 9
  53. #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_9 10
  54. #define CMDQ_EVENT_IMG_TRAW0_DMA_ERROR_INT 11
  55. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_0 12
  56. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_1 13
  57. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_2 14
  58. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_3 15
  59. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_4 16
  60. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_5 17
  61. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_6 18
  62. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_7 19
  63. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_8 20
  64. #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_9 21
  65. #define CMDQ_EVENT_IMG_TRAW1_DMA_ERROR_INT 22
  66. #define CMDQ_EVENT_IMG_ADL_RESERVED 23
  67. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_0 24
  68. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_1 25
  69. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_2 26
  70. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_3 27
  71. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_4 28
  72. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_5 29
  73. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_6 30
  74. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_7 31
  75. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_8 32
  76. #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_9 33
  77. #define CMDQ_EVENT_IMG_DIP_DMA_ERR 34
  78. #define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR 35
  79. #define CMDQ_EVENT_DIP_DUMMY_0 36
  80. #define CMDQ_EVENT_DIP_DUMMY_1 37
  81. #define CMDQ_EVENT_DIP_DUMMY_2 38
  82. #define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 39
  83. #define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 40
  84. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_0 41
  85. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_1 42
  86. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_2 43
  87. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_3 44
  88. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_4 45
  89. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_5 46
  90. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_6 47
  91. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_7 48
  92. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_8 49
  93. #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_9 50
  94. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_0 51
  95. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_1 52
  96. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_2 53
  97. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_3 54
  98. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_4 55
  99. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_5 56
  100. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_6 57
  101. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_7 58
  102. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_8 59
  103. #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_9 60
  104. #define CMDQ_EVENT_IMG_PQDIP_A_DMA_ERR 61
  105. #define CMDQ_EVENT_WPE0_DUMMY_0 62
  106. #define CMDQ_EVENT_WPE0_DUMMY_1 63
  107. #define CMDQ_EVENT_WPE0_DUMMY_2 64
  108. #define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 65
  109. #define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 66
  110. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_0 67
  111. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_1 68
  112. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_2 69
  113. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_3 70
  114. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_4 71
  115. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_5 72
  116. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_6 73
  117. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_7 74
  118. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_8 75
  119. #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_9 76
  120. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_0 77
  121. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_1 78
  122. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_2 79
  123. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_3 80
  124. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_4 81
  125. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_5 82
  126. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_6 83
  127. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_7 84
  128. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_8 85
  129. #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_9 86
  130. #define CMDQ_EVENT_IMG_PQDIP_B_DMA_ERR 87
  131. #define CMDQ_EVENT_WPE1_DUMMY_0 88
  132. #define CMDQ_EVENT_WPE1_DUMMY_1 89
  133. #define CMDQ_EVENT_WPE1_DUMMY_2 90
  134. #define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 91
  135. #define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 92
  136. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_0 93
  137. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_1 94
  138. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_2 95
  139. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_3 96
  140. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_4 97
  141. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_5 98
  142. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_6 99
  143. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_7 100
  144. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_8 101
  145. #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_9 102
  146. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_0 103
  147. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_1 104
  148. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_2 105
  149. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_3 106
  150. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_4 107
  151. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_5 108
  152. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_6 109
  153. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_7 110
  154. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_8 111
  155. #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_9 112
  156. #define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT 113
  157. #define CMDQ_EVENT_WPE2_DUMMY_0 114
  158. #define CMDQ_EVENT_WPE2_DUMMY_1 115
  159. #define CMDQ_EVENT_WPE2_DUMMY_2 116
  160. #define CMDQ_EVENT_IMG_IMGSYS_IPE_DUMMY 117
  161. #define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT_DONE 118
  162. #define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 119
  163. #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE 120
  164. #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE 121
  165. #define CMDQ_EVENT_FDVT1_RESERVED 122
  166. #define CMDQ_EVENT_IMG_ENG_EVENT 123
  167. #define CMDQ_EVENT_CAMSUBA_SW_PASS1_DONE 129
  168. #define CMDQ_EVENT_CAMSUBB_SW_PASS1_DONE 130
  169. #define CMDQ_EVENT_CAMSUBC_SW_PASS1_DONE 131
  170. #define CMDQ_EVENT_GCAMSV_A_1_SW_PASS1_DONE 132
  171. #define CMDQ_EVENT_GCAMSV_A_2_SW_PASS1_DONE 133
  172. #define CMDQ_EVENT_GCAMSV_B_1_SW_PASS1_DONE 134
  173. #define CMDQ_EVENT_GCAMSV_B_2_SW_PASS1_DONE 135
  174. #define CMDQ_EVENT_GCAMSV_C_1_SW_PASS1_DONE 136
  175. #define CMDQ_EVENT_GCAMSV_C_2_SW_PASS1_DONE 137
  176. #define CMDQ_EVENT_GCAMSV_D_1_SW_PASS1_DONE 138
  177. #define CMDQ_EVENT_GCAMSV_D_2_SW_PASS1_DONE 139
  178. #define CMDQ_EVENT_GCAMSV_E_1_SW_PASS1_DONE 140
  179. #define CMDQ_EVENT_GCAMSV_E_2_SW_PASS1_DONE 141
  180. #define CMDQ_EVENT_GCAMSV_F_1_SW_PASS1_DONE 142
  181. #define CMDQ_EVENT_GCAMSV_F_2_SW_PASS1_DONE 143
  182. #define CMDQ_EVENT_GCAMSV_G_1_SW_PASS1_DONE 144
  183. #define CMDQ_EVENT_GCAMSV_G_2_SW_PASS1_DONE 145
  184. #define CMDQ_EVENT_GCAMSV_H_1_SW_PASS1_DONE 146
  185. #define CMDQ_EVENT_GCAMSV_H_2_SW_PASS1_DONE 147
  186. #define CMDQ_EVENT_GCAMSV_I_1_SW_PASS1_DONE 148
  187. #define CMDQ_EVENT_GCAMSV_I_2_SW_PASS1_DONE 149
  188. #define CMDQ_EVENT_GCAMSV_J_1_SW_PASS1_DONE 150
  189. #define CMDQ_EVENT_GCAMSV_J_2_SW_PASS1_DONE 151
  190. #define CMDQ_EVENT_MRAW_0_SW_PASS1_DONE 152
  191. #define CMDQ_EVENT_MRAW_1_SW_PASS1_DONE 153
  192. #define CMDQ_EVENT_MRAW_2_SW_PASS1_DONE 154
  193. #define CMDQ_EVENT_MRAW_3_SW_PASS1_DONE 155
  194. #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 156
  195. #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 157
  196. #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 158
  197. #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 159
  198. #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 160
  199. #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 161
  200. #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 162
  201. #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 163
  202. #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 164
  203. #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 165
  204. #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 166
  205. #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 167
  206. #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 168
  207. #define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL 169
  208. #define CMDQ_EVENT_SENINF_CAM14_FIFO_FULL 170
  209. #define CMDQ_EVENT_SENINF_CAM15_FIFO_FULL 171
  210. #define CMDQ_EVENT_SENINF_CAM16_FIFO_FULL 172
  211. #define CMDQ_EVENT_SENINF_CAM17_FIFO_FULL 173
  212. #define CMDQ_EVENT_SENINF_CAM18_FIFO_FULL 174
  213. #define CMDQ_EVENT_SENINF_CAM19_FIFO_FULL 175
  214. #define CMDQ_EVENT_SENINF_CAM20_FIFO_FULL 176
  215. #define CMDQ_EVENT_SENINF_CAM21_FIFO_FULL 177
  216. #define CMDQ_EVENT_SENINF_CAM22_FIFO_FULL 178
  217. #define CMDQ_EVENT_SENINF_CAM23_FIFO_FULL 179
  218. #define CMDQ_EVENT_SENINF_CAM24_FIFO_FULL 180
  219. #define CMDQ_EVENT_SENINF_CAM25_FIFO_FULL 181
  220. #define CMDQ_EVENT_SENINF_CAM26_FIFO_FULL 182
  221. #define CMDQ_EVENT_TG_OVRUN_MRAW0_INT 183
  222. #define CMDQ_EVENT_TG_OVRUN_MRAW1_INT 184
  223. #define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 185
  224. #define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 186
  225. #define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 187
  226. #define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 188
  227. #define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 189
  228. #define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 190
  229. #define CMDQ_EVENT_PDA0_IRQO_EVENT_DONE_D1 191
  230. #define CMDQ_EVENT_PDA1_IRQO_EVENT_DONE_D1 192
  231. #define CMDQ_EVENT_CAM_SUBA_TG_INT1 193
  232. #define CMDQ_EVENT_CAM_SUBA_TG_INT2 194
  233. #define CMDQ_EVENT_CAM_SUBA_TG_INT3 195
  234. #define CMDQ_EVENT_CAM_SUBA_TG_INT4 196
  235. #define CMDQ_EVENT_CAM_SUBB_TG_INT1 197
  236. #define CMDQ_EVENT_CAM_SUBB_TG_INT2 198
  237. #define CMDQ_EVENT_CAM_SUBB_TG_INT3 199
  238. #define CMDQ_EVENT_CAM_SUBB_TG_INT4 200
  239. #define CMDQ_EVENT_CAM_SUBC_TG_INT1 201
  240. #define CMDQ_EVENT_CAM_SUBC_TG_INT2 202
  241. #define CMDQ_EVENT_CAM_SUBC_TG_INT3 203
  242. #define CMDQ_EVENT_CAM_SUBC_TG_INT4 204
  243. #define CMDQ_EVENT_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 205
  244. #define CMDQ_EVENT_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 206
  245. #define CMDQ_EVENT_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 207
  246. #define CMDQ_EVENT_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 208
  247. #define CMDQ_EVENT_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 209
  248. #define CMDQ_EVENT_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 210
  249. #define CMDQ_EVENT_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 211
  250. #define CMDQ_EVENT_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 212
  251. #define CMDQ_EVENT_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 213
  252. #define CMDQ_EVENT_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 214
  253. #define CMDQ_EVENT_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 215
  254. #define CMDQ_EVENT_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 216
  255. #define CMDQ_EVENT_RAW_SEL_SOF_SUBA 217
  256. #define CMDQ_EVENT_RAW_SEL_SOF_SUBB 218
  257. #define CMDQ_EVENT_RAW_SEL_SOF_SUBC 219
  258. #define CMDQ_EVENT_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 220
  259. #define CMDQ_EVENT_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 221
  260. #define CMDQ_EVENT_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 222
  261. #define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256
  262. #define CMDQ_EVENT_VPP0_MDP_FG_SOF 257
  263. #define CMDQ_EVENT_VPP0_STITCH_SOF 258
  264. #define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259
  265. #define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260
  266. #define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261
  267. #define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262
  268. #define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263
  269. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264
  270. #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265
  271. #define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266
  272. #define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267
  273. #define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269
  274. #define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270
  275. #define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271
  276. #define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272
  277. #define CMDQ_EVENT_VPP0_DISP_RDMA_SOF 273
  278. #define CMDQ_EVENT_VPP0_DISP_WDMA_SOF 274
  279. #define CMDQ_EVENT_VPP0_MDP_HMS_SOF 275
  280. #define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288
  281. #define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289
  282. #define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290
  283. #define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291
  284. #define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292
  285. #define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293
  286. #define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294
  287. #define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295
  288. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296
  289. #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297
  290. #define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298
  291. #define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299
  292. #define CMDQ_EVENT_VPP0_DISP_RDMA_FRAME_DONE 305
  293. #define CMDQ_EVENT_VPP0_DISP_WDMA_FRAME_DONE 306
  294. #define CMDQ_EVENT_VPP0_MDP_HMS_FRAME_DONE 307
  295. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_0 320
  296. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_1 321
  297. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_2 322
  298. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_3 323
  299. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_4 324
  300. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_5 325
  301. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_6 326
  302. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_7 327
  303. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_8 328
  304. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_9 329
  305. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_10 330
  306. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_11 331
  307. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_12 332
  308. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_13 333
  309. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_14 334
  310. #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_15 335
  311. #define CMDQ_EVENT_VPP0_DISP_RDMA_0_UNDERRUN 336
  312. #define CMDQ_EVENT_VPP0_DISP_RDMA_1_UNDERRUN 337
  313. #define CMDQ_EVENT_VPP0_U_MERGE4_UNDERRUN 338
  314. #define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_0_OVERFLOW 339
  315. #define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_1_OVERFLOW 340
  316. #define CMDQ_EVENT_VPP0_DSI_0_UNDERRUN 341
  317. #define CMDQ_EVENT_VPP0_DSI_1_UNDERRUN 342
  318. #define CMDQ_EVENT_VPP0_DP_INTF_0 343
  319. #define CMDQ_EVENT_VPP0_DP_INTF_1 344
  320. #define CMDQ_EVENT_VPP0_DPI_0 345
  321. #define CMDQ_EVENT_VPP0_DPI_1 346
  322. #define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352
  323. #define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID_EVENT 353
  324. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354
  325. #define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355
  326. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_0 356
  327. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_1 357
  328. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_2 358
  329. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_3 359
  330. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_4 360
  331. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_5 361
  332. #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_6 362
  333. #define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_VALID_EVENT 363
  334. #define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_TARGET_LINE_EVENT 364
  335. #define CMDQ_EVENT_VPP0_DISP_WDMA_SW_RST_DONE 365
  336. #define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_VALID_EVENT 366
  337. #define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_TARGET_LINE_EVENT 367
  338. #define CMDQ_EVENT_VPP1_HDMI_META_SOF 384
  339. #define CMDQ_EVENT_VPP1_DGI_SOF 385
  340. #define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386
  341. #define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387
  342. #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388
  343. #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389
  344. #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390
  345. #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391
  346. #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392
  347. #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393
  348. #define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394
  349. #define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395
  350. #define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396
  351. #define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397
  352. #define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398
  353. #define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399
  354. #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400
  355. #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401
  356. #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402
  357. #define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_SOF 403
  358. #define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_SOF 404
  359. #define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_SOF 405
  360. #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406
  361. #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407
  362. #define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408
  363. #define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409
  364. #define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410
  365. #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411
  366. #define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412
  367. #define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413
  368. #define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414
  369. #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415
  370. #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416
  371. #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417
  372. #define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418
  373. #define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419
  374. #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420
  375. #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421
  376. #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422
  377. #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423
  378. #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424
  379. #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425
  380. #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426
  381. #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427
  382. #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428
  383. #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429
  384. #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430
  385. #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431
  386. #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432
  387. #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433
  388. #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 434
  389. #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 435
  390. #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 436
  391. #define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_FRAME_DONE 437
  392. #define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_FRAME_DONE 438
  393. #define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_FRAME_DONE 439
  394. #define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_FRAME_DONE 440
  395. #define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_FRAME_DONE 441
  396. #define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_FRAME_DONE 442
  397. #define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_FRAME_DONE 443
  398. #define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_FRAME_DONE 444
  399. #define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_FRAME_DONE 445
  400. #define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_FRAME_DONE 446
  401. #define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_FRAME_DONE 447
  402. #define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_FRAME_DONE 448
  403. #define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_FRAME_DONE 449
  404. #define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_FRAME_DONE 450
  405. #define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_FRAME_DONE 451
  406. #define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_FRAME_DONE 452
  407. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_0 456
  408. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_1 457
  409. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_2 458
  410. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_3 459
  411. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_4 460
  412. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_5 461
  413. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_6 462
  414. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_7 463
  415. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_8 464
  416. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_9 465
  417. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_10 466
  418. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_11 467
  419. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_12 468
  420. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_13 469
  421. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_14 470
  422. #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_15 471
  423. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_0 472
  424. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_1 473
  425. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_2 474
  426. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_3 475
  427. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_4 476
  428. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_5 477
  429. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_6 478
  430. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_7 479
  431. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_8 480
  432. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_9 481
  433. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_10 482
  434. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_11 483
  435. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_12 484
  436. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_13 485
  437. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_14 486
  438. #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_15 487
  439. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_0 488
  440. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_1 489
  441. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_2 490
  442. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_3 491
  443. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_4 492
  444. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_5 493
  445. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_6 494
  446. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_7 495
  447. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_8 496
  448. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_9 497
  449. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_10 498
  450. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_11 499
  451. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_12 500
  452. #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_13 501
  453. #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_GCE_EVENT 502
  454. #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_GCE_EVENT 503
  455. #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_GCE_EVENT 504
  456. #define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI_GCE_EVENT 505
  457. #define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI_GCE_EVENT 506
  458. #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE_GCE_EVENT 507
  459. #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE_GCE_EVENT 508
  460. #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE_GCE_EVENT 509
  461. #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_0 510
  462. #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_1 511
  463. #define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512
  464. #define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513
  465. #define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514
  466. #define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515
  467. #define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516
  468. #define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517
  469. #define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518
  470. #define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519
  471. #define CMDQ_EVENT_VDO0_DSI0_SOF 520
  472. #define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521
  473. #define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522
  474. #define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523
  475. #define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524
  476. #define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525
  477. #define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526
  478. #define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527
  479. #define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528
  480. #define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529
  481. #define CMDQ_EVENT_VDO0_DSI1_SOF 530
  482. #define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531
  483. #define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532
  484. #define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533
  485. #define CMDQ_EVENT_VDO0_DISP_DPI0_SOF 534
  486. #define CMDQ_EVENT_VDO0_DISP_DPI1_SOF 535
  487. #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_SOF 536
  488. #define CMDQ_EVENT_VDO0_MDP_WROT0_SOF 537
  489. #define CMDQ_EVENT_VDO0_DISP_RSZ0_SOF 538
  490. #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 539
  491. #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 540
  492. #define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 541
  493. #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 542
  494. #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 543
  495. #define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 544
  496. #define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 545
  497. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_DONE 546
  498. #define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 547
  499. #define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 548
  500. #define CMDQ_EVENT_VDO0_DISP_COLOR0_O_FRAME_DONE 549
  501. #define CMDQ_EVENT_VDO0_DISP_CCORR0_O_FRAME_DONE 550
  502. #define CMDQ_EVENT_VDO0_DISP_AAL0_O_FRAME_DONE 551
  503. #define CMDQ_EVENT_VDO0_DISP_GAMMA0_O_FRAME_DONE 552
  504. #define CMDQ_EVENT_VDO0_DISP_DITHER0_O_FRAME_DONE 553
  505. #define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 554
  506. #define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_0 555
  507. #define CMDQ_EVENT_VDO0_DISP_OVL1_O_FRAME_DONE 556
  508. #define CMDQ_EVENT_VDO0_DISP_WDMA1_O_FRAME_DONE 557
  509. #define CMDQ_EVENT_VDO0_DISP_RDMA1_O_FRAME_DONE 558
  510. #define CMDQ_EVENT_VDO0_DISP_COLOR1_O_FRAME_DONE 559
  511. #define CMDQ_EVENT_VDO0_DISP_CCORR1_O_FRAME_DONE 560
  512. #define CMDQ_EVENT_VDO0_DISP_AAL1_O_FRAME_DONE 561
  513. #define CMDQ_EVENT_VDO0_DISP_GAMMA1_O_FRAME_DONE 562
  514. #define CMDQ_EVENT_VDO0_DISP_DITHER1_O_FRAME_DONE 563
  515. #define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 564
  516. #define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_1 565
  517. #define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 567
  518. #define CMDQ_EVENT_VDO0_DISP_DPI0_O_FRAME_DONE 568
  519. #define CMDQ_EVENT_VDO0_DISP_DPI1_O_FRAME_DONE 569
  520. #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_DONE 570
  521. #define CMDQ_EVENT_VDO0_MDP_WROT0_O_FRAME_DONE 571
  522. #define CMDQ_EVENT_VDO0_DISP_RSZ0_O_FRAME_DONE 572
  523. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 574
  524. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 575
  525. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 576
  526. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 577
  527. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 578
  528. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 579
  529. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 580
  530. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 581
  531. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 582
  532. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 583
  533. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 584
  534. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 585
  535. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 586
  536. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 587
  537. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 588
  538. #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 589
  539. #define CMDQ_EVENT_VDO0_DISP_RDMA_0_UNDERRUN 590
  540. #define CMDQ_EVENT_VDO0_DISP_RDMA_1_UNDERRUN 591
  541. #define CMDQ_EVENT_VDO0_U_MERGE4_UNDERRUN 592
  542. #define CMDQ_EVENT_VDO0_DSI_0_UNDERRUN 595
  543. #define CMDQ_EVENT_VDO0_DSI_1_UNDERRUN 596
  544. #define CMDQ_EVENT_VDO0_DP_INTF_0 597
  545. #define CMDQ_EVENT_VDO0_DP_INTF_1 598
  546. #define CMDQ_EVENT_VDO0_DPI_0 599
  547. #define CMDQ_EVENT_VDO0_DPI_1 600
  548. #define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG_EVENT 606
  549. #define CMDQ_EVENT_VDO0_DSI0_O_DSI_IRQ_EVENT_MM 607
  550. #define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 608
  551. #define CMDQ_EVENT_VDO0_DSI0_O_DSI_DONE_EVENT_MM 609
  552. #define CMDQ_EVENT_VDO0_DSI0_O_DSI_VACTL_EVENT_MM 610
  553. #define CMDQ_EVENT_VDO0_DSI1_O_DSI_IRQ_EVENT_MM 611
  554. #define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 612
  555. #define CMDQ_EVENT_VDO0_DSI1_O_DSI_DONE_EVENT_MM 613
  556. #define CMDQ_EVENT_VDO0_DSI1_O_DSI_VACTL_EVENT_MM 614
  557. #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_START_EVENT_MM 615
  558. #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_END_EVENT_MM 616
  559. #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_START_EVENT_MM 617
  560. #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_END_EVENT_MM 618
  561. #define CMDQ_EVENT_VDO0_DP_INTF0_O_VACT_TARGET_LINE_EVENT_MM 619
  562. #define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_SAFE_BLANK_EVENT_MM 620
  563. #define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_LINE_EVENT_MM 621
  564. #define CMDQ_EVENT_VDO0_DP_INTF0_O_TRIGGER_LOOP_CLEAR_EVENT_MM 622
  565. #define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_0_EVENT_MM 623
  566. #define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_1_EVENT_MM 624
  567. #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_RESET_DONE_PULSE 625
  568. #define CMDQ_EVENT_VDO0_VPP_MERGE0_O_VPP_MERGE_EVENT 626
  569. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_RESET_DONE_PULSE 627
  570. #define CMDQ_EVENT_VDO0_DISP_RDMA0_O_DISP_RDMA_TARGET_LINE_EVENT 628
  571. #define CMDQ_EVENT_VDO0_DISP_WDMA0_O_WDMA_TARGET_LINE_EVENT 629
  572. #define CMDQ_EVENT_VDO0_DISP_WDMA0_O_SW_RST_DONE 630
  573. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_0 631
  574. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_1 632
  575. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_2 633
  576. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_3 634
  577. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_4 635
  578. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_5 636
  579. #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_6 637
  580. #define CMDQ_EVENT_VDO0_MDP_WROT0_O_SW_RST_DONE 638
  581. #define CMDQ_EVENT_VDO0_RESERVED 639
  582. #define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640
  583. #define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641
  584. #define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642
  585. #define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643
  586. #define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644
  587. #define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645
  588. #define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646
  589. #define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647
  590. #define CMDQ_EVENT_VDO1_DISP_PADDING0_SOF 648
  591. #define CMDQ_EVENT_VDO1_DISP_PADDING1_SOF 649
  592. #define CMDQ_EVENT_VDO1_DISP_PADDING2_SOF 650
  593. #define CMDQ_EVENT_VDO1_DISP_PADDING3_SOF 651
  594. #define CMDQ_EVENT_VDO1_DISP_PADDING4_SOF 652
  595. #define CMDQ_EVENT_VDO1_DISP_PADDING5_SOF 653
  596. #define CMDQ_EVENT_VDO1_DISP_PADDING6_SOF 654
  597. #define CMDQ_EVENT_VDO1_DISP_PADDING7_SOF 655
  598. #define CMDQ_EVENT_VDO1_DISP_RSZ0_SOF 656
  599. #define CMDQ_EVENT_VDO1_DISP_RSZ1_SOF 657
  600. #define CMDQ_EVENT_VDO1_DISP_RSZ2_SOF 658
  601. #define CMDQ_EVENT_VDO1_DISP_RSZ3_SOF 659
  602. #define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 660
  603. #define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 661
  604. #define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 662
  605. #define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 663
  606. #define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 664
  607. #define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 665
  608. #define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 666
  609. #define CMDQ_EVENT_VDO0_DSC_DL_ASYNC_SOF 667
  610. #define CMDQ_EVENT_VDO0_MERGE_DL_ASYNC_SOF 668
  611. #define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 669
  612. #define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 670
  613. #define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 671
  614. #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 672
  615. #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 673
  616. #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 674
  617. #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 675
  618. #define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 676
  619. #define CMDQ_EVENT_VDO1_DPI0_EXT_SOF 677
  620. #define CMDQ_EVENT_VDO1_DPI1_EXT_SOF 678
  621. #define CMDQ_EVENT_VDO1_DP_INTF_EXT_EXT_SOF 679
  622. #define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 680
  623. #define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 681
  624. #define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 682
  625. #define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 683
  626. #define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 684
  627. #define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 685
  628. #define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 686
  629. #define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 687
  630. #define CMDQ_EVENT_VDO1_DISP_PADDING0_FRAME_DONE 688
  631. #define CMDQ_EVENT_VDO1_DISP_PADDING1_FRAME_DONE 689
  632. #define CMDQ_EVENT_VDO1_DISP_PADDING2_FRAME_DONE 690
  633. #define CMDQ_EVENT_VDO1_DISP_PADDING3_FRAME_DONE 691
  634. #define CMDQ_EVENT_VDO1_DISP_PADDING4_FRAME_DONE 692
  635. #define CMDQ_EVENT_VDO1_DISP_PADDING5_FRAME_DONE 693
  636. #define CMDQ_EVENT_VDO1_DISP_PADDING6_FRAME_DONE 694
  637. #define CMDQ_EVENT_VDO1_DISP_PADDING7_FRAME_DONE 695
  638. #define CMDQ_EVENT_VDO1_DISP_RSZ0_FRAME_DONE 696
  639. #define CMDQ_EVENT_VDO1_DISP_RSZ1_FRAME_DONE 697
  640. #define CMDQ_EVENT_VDO1_DISP_RSZ2_FRAME_DONE 698
  641. #define CMDQ_EVENT_VDO1_DISP_RSZ3_FRAME_DONE 699
  642. #define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 700
  643. #define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 701
  644. #define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 702
  645. #define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 703
  646. #define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 704
  647. #define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 705
  648. #define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 706
  649. #define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 707
  650. #define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 708
  651. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 709
  652. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 710
  653. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 711
  654. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 712
  655. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 713
  656. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 714
  657. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 715
  658. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 716
  659. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 717
  660. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 718
  661. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 719
  662. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 720
  663. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 721
  664. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 722
  665. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 723
  666. #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 724
  667. #define CMDQ_EVENT_VDO1_DISP_RDMA_0_UNDERRUN 725
  668. #define CMDQ_EVENT_VDO1_DISP_RDMA_1_UNDERRUN 726
  669. #define CMDQ_EVENT_VDO1_U_MERGE4_UNDERRUN 727
  670. #define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_0_OVERFLOW 728
  671. #define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_1_OVERFLOW 729
  672. #define CMDQ_EVENT_VDO1_DSI_0_UNDERRUN 730
  673. #define CMDQ_EVENT_VDO1_DSI_1_UNDERRUN 731
  674. #define CMDQ_EVENT_VDO1_DP_INTF_0 732
  675. #define CMDQ_EVENT_VDO1_DP_INTF_1 733
  676. #define CMDQ_EVENT_VDO1_DPI_0 734
  677. #define CMDQ_EVENT_VDO1_DPI_1 735
  678. #define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 741
  679. #define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 742
  680. #define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 743
  681. #define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 744
  682. #define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 745
  683. #define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 746
  684. #define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 747
  685. #define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 748
  686. #define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 749
  687. #define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 750
  688. #define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 751
  689. #define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 752
  690. #define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 753
  691. #define CMDQ_EVENT_VDO1_VPP_MERGE0_EVENT 754
  692. #define CMDQ_EVENT_VDO1_VPP_MERGE1_EVENT 755
  693. #define CMDQ_EVENT_VDO1_VPP_MERGE2_EVENT 756
  694. #define CMDQ_EVENT_VDO1_VPP_MERGE3_EVENT 757
  695. #define CMDQ_EVENT_VDO1_VPP_MERGE4_EVENT 758
  696. #define CMDQ_EVENT_VDO1_HDMITX_EVENT 759
  697. #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 760
  698. #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 761
  699. #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 762
  700. #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 763
  701. #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 764
  702. #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 765
  703. #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 766
  704. #define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_1_EVENT_MM 767
  705. #define CMDQ_EVENT_HANDSHAKE_0 768
  706. #define CMDQ_EVENT_HANDSHAKE_1 769
  707. #define CMDQ_EVENT_HANDSHAKE_2 770
  708. #define CMDQ_EVENT_HANDSHAKE_3 771
  709. #define CMDQ_EVENT_HANDSHAKE_4 772
  710. #define CMDQ_EVENT_HANDSHAKE_5 773
  711. #define CMDQ_EVENT_HANDSHAKE_6 774
  712. #define CMDQ_EVENT_HANDSHAKE_7 775
  713. #define CMDQ_EVENT_HANDSHAKE_8 776
  714. #define CMDQ_EVENT_HANDSHAKE_9 777
  715. #define CMDQ_EVENT_HANDSHAKE_10 778
  716. #define CMDQ_EVENT_HANDSHAKE_11 779
  717. #define CMDQ_EVENT_HANDSHAKE_12 780
  718. #define CMDQ_EVENT_HANDSHAKE_13 781
  719. #define CMDQ_EVENT_HANDSHAKE_14 782
  720. #define CMDQ_EVENT_HANDSHAKE_15 783
  721. #define CMDQ_EVENT_VDEC_SOC_EVENT_0 800
  722. #define CMDQ_EVENT_VDEC_SOC_EVENT_1 801
  723. #define CMDQ_EVENT_VDEC_SOC_EVENT_2 802
  724. #define CMDQ_EVENT_VDEC_SOC_EVENT_3 803
  725. #define CMDQ_EVENT_VDEC_SOC_EVENT_4 804
  726. #define CMDQ_EVENT_VDEC_SOC_EVENT_5 805
  727. #define CMDQ_EVENT_VDEC_SOC_EVENT_6 806
  728. #define CMDQ_EVENT_VDEC_SOC_EVENT_7 807
  729. #define CMDQ_EVENT_VDEC_SOC_EVENT_8 808
  730. #define CMDQ_EVENT_VDEC_SOC_EVENT_9 809
  731. #define CMDQ_EVENT_VDEC_SOC_EVENT_10 810
  732. #define CMDQ_EVENT_VDEC_SOC_EVENT_11 811
  733. #define CMDQ_EVENT_VDEC_SOC_EVENT_12 812
  734. #define CMDQ_EVENT_VDEC_SOC_EVENT_13 813
  735. #define CMDQ_EVENT_VDEC_SOC_EVENT_14 814
  736. #define CMDQ_EVENT_VDEC_SOC_EVENT_15 815
  737. #define CMDQ_EVENT_VDEC_CORE0_EVENT_0 832
  738. #define CMDQ_EVENT_VDEC_CORE0_EVENT_1 833
  739. #define CMDQ_EVENT_VDEC_CORE0_EVENT_2 834
  740. #define CMDQ_EVENT_VDEC_CORE0_EVENT_3 835
  741. #define CMDQ_EVENT_VDEC_CORE0_EVENT_4 836
  742. #define CMDQ_EVENT_VDEC_CORE0_EVENT_5 837
  743. #define CMDQ_EVENT_VDEC_CORE0_EVENT_6 838
  744. #define CMDQ_EVENT_VDEC_CORE0_EVENT_7 839
  745. #define CMDQ_EVENT_VDEC_CORE0_EVENT_8 840
  746. #define CMDQ_EVENT_VDEC_CORE0_EVENT_9 841
  747. #define CMDQ_EVENT_VDEC_CORE0_EVENT_10 842
  748. #define CMDQ_EVENT_VDEC_CORE0_EVENT_11 843
  749. #define CMDQ_EVENT_VDEC_CORE0_EVENT_12 844
  750. #define CMDQ_EVENT_VDEC_CORE0_EVENT_13 845
  751. #define CMDQ_EVENT_VDEC_CORE0_EVENT_14 846
  752. #define CMDQ_EVENT_VDEC_CORE0_EVENT_15 847
  753. #define CMDQ_EVENT_VENC_TOP_VENC_FRAME_DONE 865
  754. #define CMDQ_EVENT_VENC_TOP_VENC_PAUSE_DONE 866
  755. #define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 867
  756. #define CMDQ_EVENT_VENC_TOP_VENC_MB_DONE 868
  757. #define CMDQ_EVENT_VENC_TOP_VENC_128BYTE_DONE 869
  758. #define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 870
  759. #define CMDQ_EVENT_VENC_TOP_VENC_SLICE_DONE 871
  760. #define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 872
  761. #define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 874
  762. #define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 875
  763. #define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 876
  764. #define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 877
  765. #define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 878
  766. #define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 882
  767. #define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 883
  768. #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_2 896
  769. #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_3 897
  770. #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_4 898
  771. #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_5 899
  772. #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_6 900
  773. #define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_0_EVENT_MM 928
  774. #define CMDQ_EVENT_VDO1_DPI0_TRIGGER_LOOP_CLEAR_EVENT_MM 929
  775. #define CMDQ_EVENT_VDO1_DPI0_LAST_LINE_EVENT_MM 930
  776. #define CMDQ_EVENT_VDO1_DPI0_LAST_SAFE_BLANK_EVENT_MM 931
  777. #define CMDQ_EVENT_VDO1_DPI0_VSYNC_START_EVENT_MM 932
  778. #define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_1_EVENT_MM 933
  779. #define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_0_EVENT_MM 934
  780. #define CMDQ_EVENT_VDO1_DPI1_TRIGGER_LOOP_CLEAR_EVENT_MM 935
  781. #define CMDQ_EVENT_VDO1_DPI1_LAST_LINE_EVENT_MM 936
  782. #define CMDQ_EVENT_VDO1_DPI1_LAST_SAFE_BLANK_EVENT_MM 937
  783. #define CMDQ_EVENT_VDO1_DPI1_VSYNC_START_EVENT_MM 938
  784. #define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_1_EVENT_MM 939
  785. #define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_0_EVENT_MM 940
  786. #define CMDQ_EVENT_VDO1_DP_INTF_TRIGGER_LOOP_CLEAR_EVENT_MM 941
  787. #define CMDQ_EVENT_VDO1_DP_INTF_LAST_LINE_EVENT_MM 942
  788. #define CMDQ_EVENT_VDO1_DP_INTF_LAST_SAFE_BLANK_EVENT_MM 943
  789. #define CMDQ_EVENT_VBLANK_FALLING 946
  790. #define CMDQ_EVENT_VSC_FINISH 947
  791. #define CMDQ_EVENT_TPR_0 962
  792. #define CMDQ_EVENT_TPR_1 963
  793. #define CMDQ_EVENT_TPR_2 964
  794. #define CMDQ_EVENT_TPR_3 965
  795. #define CMDQ_EVENT_TPR_4 966
  796. #define CMDQ_EVENT_TPR_5 967
  797. #define CMDQ_EVENT_TPR_6 968
  798. #define CMDQ_EVENT_TPR_7 969
  799. #define CMDQ_EVENT_TPR_8 970
  800. #define CMDQ_EVENT_TPR_9 971
  801. #define CMDQ_EVENT_TPR_10 972
  802. #define CMDQ_EVENT_TPR_11 973
  803. #define CMDQ_EVENT_TPR_12 974
  804. #define CMDQ_EVENT_TPR_13 975
  805. #define CMDQ_EVENT_TPR_14 976
  806. #define CMDQ_EVENT_TPR_15 977
  807. #define CMDQ_EVENT_TPR_16 978
  808. #define CMDQ_EVENT_TPR_17 979
  809. #define CMDQ_EVENT_TPR_18 980
  810. #define CMDQ_EVENT_TPR_19 981
  811. #define CMDQ_EVENT_TPR_20 982
  812. #define CMDQ_EVENT_TPR_21 983
  813. #define CMDQ_EVENT_TPR_22 984
  814. #define CMDQ_EVENT_TPR_23 985
  815. #define CMDQ_EVENT_TPR_24 986
  816. #define CMDQ_EVENT_TPR_25 987
  817. #define CMDQ_EVENT_TPR_26 988
  818. #define CMDQ_EVENT_TPR_27 989
  819. #define CMDQ_EVENT_TPR_28 990
  820. #define CMDQ_EVENT_TPR_29 991
  821. #define CMDQ_EVENT_TPR_30 992
  822. #define CMDQ_EVENT_TPR_31 993
  823. #define CMDQ_EVENT_TPR_TIMEOUT_0 994
  824. #define CMDQ_EVENT_TPR_TIMEOUT_1 995
  825. #define CMDQ_EVENT_TPR_TIMEOUT_2 996
  826. #define CMDQ_EVENT_TPR_TIMEOUT_3 997
  827. #define CMDQ_EVENT_TPR_TIMEOUT_4 998
  828. #define CMDQ_EVENT_TPR_TIMEOUT_5 999
  829. #define CMDQ_EVENT_TPR_TIMEOUT_6 1000
  830. #define CMDQ_EVENT_TPR_TIMEOUT_7 1001
  831. #define CMDQ_EVENT_TPR_TIMEOUT_8 1002
  832. #define CMDQ_EVENT_TPR_TIMEOUT_9 1003
  833. #define CMDQ_EVENT_TPR_TIMEOUT_10 1004
  834. #define CMDQ_EVENT_TPR_TIMEOUT_11 1005
  835. #define CMDQ_EVENT_TPR_TIMEOUT_12 1006
  836. #define CMDQ_EVENT_TPR_TIMEOUT_13 1007
  837. #define CMDQ_EVENT_TPR_TIMEOUT_14 1008
  838. #define CMDQ_EVENT_TPR_TIMEOUT_15 1009
  839. #define CMDQ_EVENT_OUTPIN_0 1018
  840. #define CMDQ_EVENT_OUTPIN_1 1019
  841. #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 124
  842. #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 125
  843. #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 126
  844. #define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 127
  845. #define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 128
  846. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_1 223
  847. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_2 224
  848. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_3 225
  849. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_4 226
  850. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_5 227
  851. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_6 228
  852. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_7 229
  853. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_8 230
  854. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_9 231
  855. #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_10 232
  856. #define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 233
  857. #define CMDQ_SYNC_TOKEN_IMGSYS_DIP 234
  858. #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 235
  859. #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 236
  860. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 237
  861. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 238
  862. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 239
  863. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 240
  864. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 241
  865. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 242
  866. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 243
  867. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 244
  868. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 245
  869. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 246
  870. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 247
  871. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 248
  872. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 249
  873. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 250
  874. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 251
  875. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 252
  876. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 253
  877. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 254
  878. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 255
  879. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 276
  880. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 277
  881. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 278
  882. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 279
  883. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 280
  884. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 281
  885. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 282
  886. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 283
  887. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 284
  888. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 285
  889. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 286
  890. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 287
  891. #define CMDQ_SYNC_TOKEN_IPESYS_ME 300
  892. #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 301
  893. #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 302
  894. #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 303
  895. #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 304
  896. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 308
  897. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 309
  898. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 310
  899. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 311
  900. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 312
  901. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 313
  902. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 314
  903. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 315
  904. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 316
  905. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 370
  906. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 371
  907. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 372
  908. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 373
  909. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 374
  910. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 375
  911. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 376
  912. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 377
  913. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 378
  914. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 379
  915. #define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 380
  916. #define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 381
  917. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 790
  918. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 791
  919. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 792
  920. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 793
  921. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 794
  922. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 795
  923. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 796
  924. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 797
  925. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 798
  926. #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 799
  927. #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_WAIT 816
  928. #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_SET 817
  929. #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 818
  930. #define CMDQ_SYNC_TOKEN_PREBUILT_MML_WAIT 819
  931. #define CMDQ_SYNC_TOKEN_PREBUILT_MML_SET 820
  932. #define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 821
  933. #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_WAIT 822
  934. #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_SET 823
  935. #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 824
  936. #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_WAIT 825
  937. #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_SET 826
  938. #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 827
  939. #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 848
  940. #define CMDQ_SYNC_TOKEN_STREAM_EOF 849
  941. #define CMDQ_SYNC_TOKEN_ESD_EOF 850
  942. #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 851
  943. #define CMDQ_SYNC_TOKEN_CABC_EOF 852
  944. #define CMDQ_SYNC_TOKEN_VENC_INPUT_READY 853
  945. #define CMDQ_SYNC_TOKEN_VENC_EOF 854
  946. #define CMDQ_SYNC_TOKEN_SECURE_THR_EOF 855
  947. #define CMDQ_SYNC_TOKEN_USER_0 856
  948. #define CMDQ_SYNC_TOKEN_USER_1 857
  949. #define CMDQ_SYNC_TOKEN_POLL_MONITOR 858
  950. #define CMDQ_TOKEN_TPR_LOCK 859
  951. #define CMDQ_SYNC_TOKEN_MSS 860
  952. #define CMDQ_SYNC_TOKEN_MSF 861
  953. #define CMDQ_SYNC_TOKEN_GPR_SET_0 884
  954. #define CMDQ_SYNC_TOKEN_GPR_SET_1 885
  955. #define CMDQ_SYNC_TOKEN_GPR_SET_2 886
  956. #define CMDQ_SYNC_TOKEN_GPR_SET_3 887
  957. #define CMDQ_SYNC_TOKEN_GPR_SET_4 888
  958. #define CMDQ_SYNC_RESOURCE_WROT0 889
  959. #define CMDQ_SYNC_RESOURCE_WROT1 890
  960. #define CMDQ_SYNC_TOKEN_DISP_VA_START 1012
  961. #define CMDQ_SYNC_TOKEN_DISP_VA_END 1013
  962. #endif