vg_chip_offset_byte.h 20 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * AMD ACP 5.x Register Documentation
  4. *
  5. * Copyright 2021 Advanced Micro Devices, Inc.
  6. */
  7. #ifndef _acp_ip_OFFSET_HEADER
  8. #define _acp_ip_OFFSET_HEADER
  9. /* Registers from ACP_DMA block */
  10. #define ACP_DMA_CNTL_0 0x1240000
  11. #define ACP_DMA_CNTL_1 0x1240004
  12. #define ACP_DMA_CNTL_2 0x1240008
  13. #define ACP_DMA_CNTL_3 0x124000C
  14. #define ACP_DMA_CNTL_4 0x1240010
  15. #define ACP_DMA_CNTL_5 0x1240014
  16. #define ACP_DMA_CNTL_6 0x1240018
  17. #define ACP_DMA_CNTL_7 0x124001C
  18. #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020
  19. #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024
  20. #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028
  21. #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C
  22. #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030
  23. #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034
  24. #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038
  25. #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C
  26. #define ACP_DMA_DSCR_CNT_0 0x1240040
  27. #define ACP_DMA_DSCR_CNT_1 0x1240044
  28. #define ACP_DMA_DSCR_CNT_2 0x1240048
  29. #define ACP_DMA_DSCR_CNT_3 0x124004C
  30. #define ACP_DMA_DSCR_CNT_4 0x1240050
  31. #define ACP_DMA_DSCR_CNT_5 0x1240054
  32. #define ACP_DMA_DSCR_CNT_6 0x1240058
  33. #define ACP_DMA_DSCR_CNT_7 0x124005C
  34. #define ACP_DMA_PRIO_0 0x1240060
  35. #define ACP_DMA_PRIO_1 0x1240064
  36. #define ACP_DMA_PRIO_2 0x1240068
  37. #define ACP_DMA_PRIO_3 0x124006C
  38. #define ACP_DMA_PRIO_4 0x1240070
  39. #define ACP_DMA_PRIO_5 0x1240074
  40. #define ACP_DMA_PRIO_6 0x1240078
  41. #define ACP_DMA_PRIO_7 0x124007C
  42. #define ACP_DMA_CUR_DSCR_0 0x1240080
  43. #define ACP_DMA_CUR_DSCR_1 0x1240084
  44. #define ACP_DMA_CUR_DSCR_2 0x1240088
  45. #define ACP_DMA_CUR_DSCR_3 0x124008C
  46. #define ACP_DMA_CUR_DSCR_4 0x1240090
  47. #define ACP_DMA_CUR_DSCR_5 0x1240094
  48. #define ACP_DMA_CUR_DSCR_6 0x1240098
  49. #define ACP_DMA_CUR_DSCR_7 0x124009C
  50. #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0
  51. #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4
  52. #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8
  53. #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC
  54. #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0
  55. #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4
  56. #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8
  57. #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC
  58. #define ACP_DMA_ERR_STS_0 0x12400C0
  59. #define ACP_DMA_ERR_STS_1 0x12400C4
  60. #define ACP_DMA_ERR_STS_2 0x12400C8
  61. #define ACP_DMA_ERR_STS_3 0x12400CC
  62. #define ACP_DMA_ERR_STS_4 0x12400D0
  63. #define ACP_DMA_ERR_STS_5 0x12400D4
  64. #define ACP_DMA_ERR_STS_6 0x12400D8
  65. #define ACP_DMA_ERR_STS_7 0x12400DC
  66. #define ACP_DMA_DESC_BASE_ADDR 0x12400E0
  67. #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4
  68. #define ACP_DMA_CH_STS 0x12400E8
  69. #define ACP_DMA_CH_GROUP 0x12400EC
  70. #define ACP_DMA_CH_RST_STS 0x12400F0
  71. /* Registers from ACP_AXI2AXIATU block */
  72. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00
  73. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04
  74. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08
  75. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C
  76. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10
  77. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14
  78. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18
  79. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C
  80. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20
  81. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24
  82. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28
  83. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C
  84. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30
  85. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34
  86. #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38
  87. #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C
  88. #define ACPAXI2AXI_ATU_CTRL 0x1240C40
  89. /* Registers from ACP_CLKRST block */
  90. #define ACP_SOFT_RESET 0x1241000
  91. #define ACP_CONTROL 0x1241004
  92. #define ACP_STATUS 0x1241008
  93. #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010
  94. /* Registers from ACP_MISC block */
  95. #define ACP_EXTERNAL_INTR_ENB 0x1241800
  96. #define ACP_EXTERNAL_INTR_CNTL 0x1241804
  97. #define ACP_EXTERNAL_INTR_STAT 0x1241808
  98. #define ACP_ERROR_STATUS 0x12418C4
  99. #define ACP_SW_I2S_ERROR_REASON 0x12418C8
  100. #define ACP_MEM_PG_STS 0x12418CC
  101. #define ACP_PGMEM_DEEP_SLEEP_CTRL 0x12418D0
  102. #define ACP_PGMEM_SHUT_DOWN_CTRL 0x12418D4
  103. /* Registers from ACP_PGFSM block */
  104. #define ACP_PIN_CONFIG 0x1241400
  105. #define ACP_PAD_PULLUP_CTRL 0x1241404
  106. #define ACP_PAD_PULLDOWN_CTRL 0x1241408
  107. #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124140C
  108. #define ACP_PAD_SCHMEN_CTRL 0x1241410
  109. #define ACP_SW_PAD_KEEPER_EN 0x1241414
  110. #define ACP_SW_WAKE_EN 0x1241418
  111. #define ACP_I2S_WAKE_EN 0x124141C
  112. #define ACP_PME_EN 0x1241420
  113. #define ACP_PGFSM_CONTROL 0x1241424
  114. #define ACP_PGFSM_STATUS 0x1241428
  115. #define ACP_CLKMUX_SEL 0x124142C
  116. #define ACP_DEVICE_STATE 0x1241430
  117. #define AZ_DEVICE_STATE 0x1241434
  118. #define ACP_INTR_URGENCY_TIMER 0x1241438
  119. #define AZ_INTR_URGENCY_TIMER 0x124143C
  120. #define ACP_AON_SW_INTR_TRIG 0x1241440
  121. /* Registers from ACP_SCRATCH block */
  122. #define ACP_SCRATCH_REG_0 0x1250000
  123. #define ACP_SCRATCH_REG_1 0x1250004
  124. #define ACP_SCRATCH_REG_2 0x1250008
  125. #define ACP_SCRATCH_REG_3 0x125000C
  126. #define ACP_SCRATCH_REG_4 0x1250010
  127. #define ACP_SCRATCH_REG_5 0x1250014
  128. #define ACP_SCRATCH_REG_6 0x1250018
  129. #define ACP_SCRATCH_REG_7 0x125001C
  130. #define ACP_SCRATCH_REG_8 0x1250020
  131. #define ACP_SCRATCH_REG_9 0x1250024
  132. #define ACP_SCRATCH_REG_10 0x1250028
  133. #define ACP_SCRATCH_REG_11 0x125002C
  134. #define ACP_SCRATCH_REG_12 0x1250030
  135. #define ACP_SCRATCH_REG_13 0x1250034
  136. #define ACP_SCRATCH_REG_14 0x1250038
  137. #define ACP_SCRATCH_REG_15 0x125003C
  138. #define ACP_SCRATCH_REG_16 0x1250040
  139. #define ACP_SCRATCH_REG_17 0x1250044
  140. #define ACP_SCRATCH_REG_18 0x1250048
  141. #define ACP_SCRATCH_REG_19 0x125004C
  142. #define ACP_SCRATCH_REG_20 0x1250050
  143. #define ACP_SCRATCH_REG_21 0x1250054
  144. #define ACP_SCRATCH_REG_22 0x1250058
  145. #define ACP_SCRATCH_REG_23 0x125005C
  146. #define ACP_SCRATCH_REG_24 0x1250060
  147. #define ACP_SCRATCH_REG_25 0x1250064
  148. #define ACP_SCRATCH_REG_26 0x1250068
  149. #define ACP_SCRATCH_REG_27 0x125006C
  150. #define ACP_SCRATCH_REG_28 0x1250070
  151. #define ACP_SCRATCH_REG_29 0x1250074
  152. #define ACP_SCRATCH_REG_30 0x1250078
  153. #define ACP_SCRATCH_REG_31 0x125007C
  154. #define ACP_SCRATCH_REG_32 0x1250080
  155. #define ACP_SCRATCH_REG_33 0x1250084
  156. #define ACP_SCRATCH_REG_34 0x1250088
  157. #define ACP_SCRATCH_REG_35 0x125008C
  158. #define ACP_SCRATCH_REG_36 0x1250090
  159. #define ACP_SCRATCH_REG_37 0x1250094
  160. #define ACP_SCRATCH_REG_38 0x1250098
  161. #define ACP_SCRATCH_REG_39 0x125009C
  162. #define ACP_SCRATCH_REG_40 0x12500A0
  163. #define ACP_SCRATCH_REG_41 0x12500A4
  164. #define ACP_SCRATCH_REG_42 0x12500A8
  165. #define ACP_SCRATCH_REG_43 0x12500AC
  166. #define ACP_SCRATCH_REG_44 0x12500B0
  167. #define ACP_SCRATCH_REG_45 0x12500B4
  168. #define ACP_SCRATCH_REG_46 0x12500B8
  169. #define ACP_SCRATCH_REG_47 0x12500BC
  170. #define ACP_SCRATCH_REG_48 0x12500C0
  171. #define ACP_SCRATCH_REG_49 0x12500C4
  172. #define ACP_SCRATCH_REG_50 0x12500C8
  173. #define ACP_SCRATCH_REG_51 0x12500CC
  174. #define ACP_SCRATCH_REG_52 0x12500D0
  175. #define ACP_SCRATCH_REG_53 0x12500D4
  176. #define ACP_SCRATCH_REG_54 0x12500D8
  177. #define ACP_SCRATCH_REG_55 0x12500DC
  178. #define ACP_SCRATCH_REG_56 0x12500E0
  179. #define ACP_SCRATCH_REG_57 0x12500E4
  180. #define ACP_SCRATCH_REG_58 0x12500E8
  181. #define ACP_SCRATCH_REG_59 0x12500EC
  182. #define ACP_SCRATCH_REG_60 0x12500F0
  183. #define ACP_SCRATCH_REG_61 0x12500F4
  184. #define ACP_SCRATCH_REG_62 0x12500F8
  185. #define ACP_SCRATCH_REG_63 0x12500FC
  186. #define ACP_SCRATCH_REG_64 0x1250100
  187. #define ACP_SCRATCH_REG_65 0x1250104
  188. #define ACP_SCRATCH_REG_66 0x1250108
  189. #define ACP_SCRATCH_REG_67 0x125010C
  190. #define ACP_SCRATCH_REG_68 0x1250110
  191. #define ACP_SCRATCH_REG_69 0x1250114
  192. #define ACP_SCRATCH_REG_70 0x1250118
  193. #define ACP_SCRATCH_REG_71 0x125011C
  194. #define ACP_SCRATCH_REG_72 0x1250120
  195. #define ACP_SCRATCH_REG_73 0x1250124
  196. #define ACP_SCRATCH_REG_74 0x1250128
  197. #define ACP_SCRATCH_REG_75 0x125012C
  198. #define ACP_SCRATCH_REG_76 0x1250130
  199. #define ACP_SCRATCH_REG_77 0x1250134
  200. #define ACP_SCRATCH_REG_78 0x1250138
  201. #define ACP_SCRATCH_REG_79 0x125013C
  202. #define ACP_SCRATCH_REG_80 0x1250140
  203. #define ACP_SCRATCH_REG_81 0x1250144
  204. #define ACP_SCRATCH_REG_82 0x1250148
  205. #define ACP_SCRATCH_REG_83 0x125014C
  206. #define ACP_SCRATCH_REG_84 0x1250150
  207. #define ACP_SCRATCH_REG_85 0x1250154
  208. #define ACP_SCRATCH_REG_86 0x1250158
  209. #define ACP_SCRATCH_REG_87 0x125015C
  210. #define ACP_SCRATCH_REG_88 0x1250160
  211. #define ACP_SCRATCH_REG_89 0x1250164
  212. #define ACP_SCRATCH_REG_90 0x1250168
  213. #define ACP_SCRATCH_REG_91 0x125016C
  214. #define ACP_SCRATCH_REG_92 0x1250170
  215. #define ACP_SCRATCH_REG_93 0x1250174
  216. #define ACP_SCRATCH_REG_94 0x1250178
  217. #define ACP_SCRATCH_REG_95 0x125017C
  218. #define ACP_SCRATCH_REG_96 0x1250180
  219. #define ACP_SCRATCH_REG_97 0x1250184
  220. #define ACP_SCRATCH_REG_98 0x1250188
  221. #define ACP_SCRATCH_REG_99 0x125018C
  222. #define ACP_SCRATCH_REG_100 0x1250190
  223. #define ACP_SCRATCH_REG_101 0x1250194
  224. #define ACP_SCRATCH_REG_102 0x1250198
  225. #define ACP_SCRATCH_REG_103 0x125019C
  226. #define ACP_SCRATCH_REG_104 0x12501A0
  227. #define ACP_SCRATCH_REG_105 0x12501A4
  228. #define ACP_SCRATCH_REG_106 0x12501A8
  229. #define ACP_SCRATCH_REG_107 0x12501AC
  230. #define ACP_SCRATCH_REG_108 0x12501B0
  231. #define ACP_SCRATCH_REG_109 0x12501B4
  232. #define ACP_SCRATCH_REG_110 0x12501B8
  233. #define ACP_SCRATCH_REG_111 0x12501BC
  234. #define ACP_SCRATCH_REG_112 0x12501C0
  235. #define ACP_SCRATCH_REG_113 0x12501C4
  236. #define ACP_SCRATCH_REG_114 0x12501C8
  237. #define ACP_SCRATCH_REG_115 0x12501CC
  238. #define ACP_SCRATCH_REG_116 0x12501D0
  239. #define ACP_SCRATCH_REG_117 0x12501D4
  240. #define ACP_SCRATCH_REG_118 0x12501D8
  241. #define ACP_SCRATCH_REG_119 0x12501DC
  242. #define ACP_SCRATCH_REG_120 0x12501E0
  243. #define ACP_SCRATCH_REG_121 0x12501E4
  244. #define ACP_SCRATCH_REG_122 0x12501E8
  245. #define ACP_SCRATCH_REG_123 0x12501EC
  246. #define ACP_SCRATCH_REG_124 0x12501F0
  247. #define ACP_SCRATCH_REG_125 0x12501F4
  248. #define ACP_SCRATCH_REG_126 0x12501F8
  249. #define ACP_SCRATCH_REG_127 0x12501FC
  250. #define ACP_SCRATCH_REG_128 0x1250200
  251. /* Registers from ACP_AUDIO_BUFFERS block */
  252. #define ACP_I2S_RX_RINGBUFADDR 0x1242000
  253. #define ACP_I2S_RX_RINGBUFSIZE 0x1242004
  254. #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008
  255. #define ACP_I2S_RX_FIFOADDR 0x124200C
  256. #define ACP_I2S_RX_FIFOSIZE 0x1242010
  257. #define ACP_I2S_RX_DMA_SIZE 0x1242014
  258. #define ACP_I2S_RX_LINEARPOSCNTR_HIGH 0x1242018
  259. #define ACP_I2S_RX_LINEARPOSCNTR_LOW 0x124201C
  260. #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020
  261. #define ACP_I2S_TX_RINGBUFADDR 0x1242024
  262. #define ACP_I2S_TX_RINGBUFSIZE 0x1242028
  263. #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C
  264. #define ACP_I2S_TX_FIFOADDR 0x1242030
  265. #define ACP_I2S_TX_FIFOSIZE 0x1242034
  266. #define ACP_I2S_TX_DMA_SIZE 0x1242038
  267. #define ACP_I2S_TX_LINEARPOSCNTR_HIGH 0x124203C
  268. #define ACP_I2S_TX_LINEARPOSCNTR_LOW 0x1242040
  269. #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044
  270. #define ACP_BT_RX_RINGBUFADDR 0x1242048
  271. #define ACP_BT_RX_RINGBUFSIZE 0x124204C
  272. #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050
  273. #define ACP_BT_RX_FIFOADDR 0x1242054
  274. #define ACP_BT_RX_FIFOSIZE 0x1242058
  275. #define ACP_BT_RX_DMA_SIZE 0x124205C
  276. #define ACP_BT_RX_LINEARPOSCNTR_HIGH 0x1242060
  277. #define ACP_BT_RX_LINEARPOSCNTR_LOW 0x1242064
  278. #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068
  279. #define ACP_BT_TX_RINGBUFADDR 0x124206C
  280. #define ACP_BT_TX_RINGBUFSIZE 0x1242070
  281. #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074
  282. #define ACP_BT_TX_FIFOADDR 0x1242078
  283. #define ACP_BT_TX_FIFOSIZE 0x124207C
  284. #define ACP_BT_TX_DMA_SIZE 0x1242080
  285. #define ACP_BT_TX_LINEARPOSCNTR_HIGH 0x1242084
  286. #define ACP_BT_TX_LINEARPOSCNTR_LOW 0x1242088
  287. #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C
  288. #define ACP_HS_RX_RINGBUFADDR 0x1242090
  289. #define ACP_HS_RX_RINGBUFSIZE 0x1242094
  290. #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098
  291. #define ACP_HS_RX_FIFOADDR 0x124209C
  292. #define ACP_HS_RX_FIFOSIZE 0x12420A0
  293. #define ACP_HS_RX_DMA_SIZE 0x12420A4
  294. #define ACP_HS_RX_LINEARPOSCNTR_HIGH 0x12420A8
  295. #define ACP_HS_RX_LINEARPOSCNTR_LOW 0x12420AC
  296. #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0
  297. #define ACP_HS_TX_RINGBUFADDR 0x12420B4
  298. #define ACP_HS_TX_RINGBUFSIZE 0x12420B8
  299. #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC
  300. #define ACP_HS_TX_FIFOADDR 0x12420C0
  301. #define ACP_HS_TX_FIFOSIZE 0x12420C4
  302. #define ACP_HS_TX_DMA_SIZE 0x12420C8
  303. #define ACP_HS_TX_LINEARPOSCNTR_HIGH 0x12420CC
  304. #define ACP_HS_TX_LINEARPOSCNTR_LOW 0x12420D0
  305. #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4
  306. /* Registers from ACP_I2S_TDM block */
  307. #define ACP_I2STDM_IER 0x1242400
  308. #define ACP_I2STDM_IRER 0x1242404
  309. #define ACP_I2STDM_RXFRMT 0x1242408
  310. #define ACP_I2STDM_ITER 0x124240C
  311. #define ACP_I2STDM_TXFRMT 0x1242410
  312. #define ACP_I2STDM0_MSTRCLKGEN 0x1242414
  313. #define ACP_I2STDM1_MSTRCLKGEN 0x1242418
  314. #define ACP_I2STDM2_MSTRCLKGEN 0x124241C
  315. #define ACP_I2STDM_REFCLKGEN 0x1242420
  316. /* Registers from ACP_BT_TDM block */
  317. #define ACP_BTTDM_IER 0x1242800
  318. #define ACP_BTTDM_IRER 0x1242804
  319. #define ACP_BTTDM_RXFRMT 0x1242808
  320. #define ACP_BTTDM_ITER 0x124280C
  321. #define ACP_BTTDM_TXFRMT 0x1242810
  322. #define ACP_HSTDM_IER 0x1242814
  323. #define ACP_HSTDM_IRER 0x1242818
  324. #define ACP_HSTDM_RXFRMT 0x124281C
  325. #define ACP_HSTDM_ITER 0x1242820
  326. #define ACP_HSTDM_TXFRMT 0x1242824
  327. #endif