atmel-classd.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* Atmel ALSA SoC Audio Class D Amplifier (CLASSD) driver
  3. *
  4. * Copyright (C) 2015 Atmel
  5. *
  6. * Author: Songjun Wu <songjun.wu@atmel.com>
  7. */
  8. #include <linux/of.h>
  9. #include <linux/clk.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include <sound/core.h>
  14. #include <sound/dmaengine_pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/tlv.h>
  17. #include "atmel-classd.h"
  18. struct atmel_classd_pdata {
  19. bool non_overlap_enable;
  20. int non_overlap_time;
  21. int pwm_type;
  22. const char *card_name;
  23. };
  24. struct atmel_classd {
  25. dma_addr_t phy_base;
  26. struct regmap *regmap;
  27. struct clk *pclk;
  28. struct clk *gclk;
  29. struct device *dev;
  30. int irq;
  31. const struct atmel_classd_pdata *pdata;
  32. };
  33. #ifdef CONFIG_OF
  34. static const struct of_device_id atmel_classd_of_match[] = {
  35. {
  36. .compatible = "atmel,sama5d2-classd",
  37. }, {
  38. /* sentinel */
  39. }
  40. };
  41. MODULE_DEVICE_TABLE(of, atmel_classd_of_match);
  42. static struct atmel_classd_pdata *atmel_classd_dt_init(struct device *dev)
  43. {
  44. struct device_node *np = dev->of_node;
  45. struct atmel_classd_pdata *pdata;
  46. const char *pwm_type_s;
  47. int ret;
  48. if (!np) {
  49. dev_err(dev, "device node not found\n");
  50. return ERR_PTR(-EINVAL);
  51. }
  52. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  53. if (!pdata)
  54. return ERR_PTR(-ENOMEM);
  55. ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s);
  56. if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0))
  57. pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;
  58. else
  59. pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;
  60. ret = of_property_read_u32(np,
  61. "atmel,non-overlap-time", &pdata->non_overlap_time);
  62. if (ret)
  63. pdata->non_overlap_enable = false;
  64. else
  65. pdata->non_overlap_enable = true;
  66. ret = of_property_read_string(np, "atmel,model", &pdata->card_name);
  67. if (ret)
  68. pdata->card_name = "CLASSD";
  69. return pdata;
  70. }
  71. #else
  72. static inline struct atmel_classd_pdata *
  73. atmel_classd_dt_init(struct device *dev)
  74. {
  75. return ERR_PTR(-EINVAL);
  76. }
  77. #endif
  78. #define ATMEL_CLASSD_RATES (SNDRV_PCM_RATE_8000 \
  79. | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 \
  80. | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 \
  81. | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 \
  82. | SNDRV_PCM_RATE_96000)
  83. static const struct snd_pcm_hardware atmel_classd_hw = {
  84. .info = SNDRV_PCM_INFO_MMAP
  85. | SNDRV_PCM_INFO_MMAP_VALID
  86. | SNDRV_PCM_INFO_INTERLEAVED
  87. | SNDRV_PCM_INFO_RESUME
  88. | SNDRV_PCM_INFO_PAUSE,
  89. .formats = (SNDRV_PCM_FMTBIT_S16_LE),
  90. .rates = ATMEL_CLASSD_RATES,
  91. .rate_min = 8000,
  92. .rate_max = 96000,
  93. .channels_min = 1,
  94. .channels_max = 2,
  95. .buffer_bytes_max = 64 * 1024,
  96. .period_bytes_min = 256,
  97. .period_bytes_max = 32 * 1024,
  98. .periods_min = 2,
  99. .periods_max = 256,
  100. };
  101. #define ATMEL_CLASSD_PREALLOC_BUF_SIZE (64 * 1024)
  102. /* cpu dai component */
  103. static int atmel_classd_cpu_dai_startup(struct snd_pcm_substream *substream,
  104. struct snd_soc_dai *cpu_dai)
  105. {
  106. struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  107. struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
  108. int err;
  109. regmap_write(dd->regmap, CLASSD_THR, 0x0);
  110. err = clk_prepare_enable(dd->pclk);
  111. if (err)
  112. return err;
  113. err = clk_prepare_enable(dd->gclk);
  114. if (err) {
  115. clk_disable_unprepare(dd->pclk);
  116. return err;
  117. }
  118. return 0;
  119. }
  120. /* platform */
  121. static int
  122. atmel_classd_platform_configure_dma(struct snd_pcm_substream *substream,
  123. struct snd_pcm_hw_params *params,
  124. struct dma_slave_config *slave_config)
  125. {
  126. struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  127. struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
  128. if (params_physical_width(params) != 16) {
  129. dev_err(dd->dev,
  130. "only supports 16-bit audio data\n");
  131. return -EINVAL;
  132. }
  133. if (params_channels(params) == 1)
  134. slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  135. else
  136. slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  137. slave_config->direction = DMA_MEM_TO_DEV;
  138. slave_config->dst_addr = dd->phy_base + CLASSD_THR;
  139. slave_config->dst_maxburst = 1;
  140. slave_config->src_maxburst = 1;
  141. slave_config->device_fc = false;
  142. return 0;
  143. }
  144. static const struct snd_dmaengine_pcm_config
  145. atmel_classd_dmaengine_pcm_config = {
  146. .prepare_slave_config = atmel_classd_platform_configure_dma,
  147. .pcm_hardware = &atmel_classd_hw,
  148. .prealloc_buffer_size = ATMEL_CLASSD_PREALLOC_BUF_SIZE,
  149. };
  150. /* codec */
  151. static const char * const mono_mode_text[] = {
  152. "mix", "sat", "left", "right"
  153. };
  154. static SOC_ENUM_SINGLE_DECL(classd_mono_mode_enum,
  155. CLASSD_INTPMR, CLASSD_INTPMR_MONO_MODE_SHIFT,
  156. mono_mode_text);
  157. static const char * const eqcfg_text[] = {
  158. "Treble-12dB", "Treble-6dB",
  159. "Medium-8dB", "Medium-3dB",
  160. "Bass-12dB", "Bass-6dB",
  161. "0 dB",
  162. "Bass+6dB", "Bass+12dB",
  163. "Medium+3dB", "Medium+8dB",
  164. "Treble+6dB", "Treble+12dB",
  165. };
  166. static const unsigned int eqcfg_value[] = {
  167. CLASSD_INTPMR_EQCFG_T_CUT_12, CLASSD_INTPMR_EQCFG_T_CUT_6,
  168. CLASSD_INTPMR_EQCFG_M_CUT_8, CLASSD_INTPMR_EQCFG_M_CUT_3,
  169. CLASSD_INTPMR_EQCFG_B_CUT_12, CLASSD_INTPMR_EQCFG_B_CUT_6,
  170. CLASSD_INTPMR_EQCFG_FLAT,
  171. CLASSD_INTPMR_EQCFG_B_BOOST_6, CLASSD_INTPMR_EQCFG_B_BOOST_12,
  172. CLASSD_INTPMR_EQCFG_M_BOOST_3, CLASSD_INTPMR_EQCFG_M_BOOST_8,
  173. CLASSD_INTPMR_EQCFG_T_BOOST_6, CLASSD_INTPMR_EQCFG_T_BOOST_12,
  174. };
  175. static SOC_VALUE_ENUM_SINGLE_DECL(classd_eqcfg_enum,
  176. CLASSD_INTPMR, CLASSD_INTPMR_EQCFG_SHIFT, 0xf,
  177. eqcfg_text, eqcfg_value);
  178. static const DECLARE_TLV_DB_SCALE(classd_digital_tlv, -7800, 100, 1);
  179. static const struct snd_kcontrol_new atmel_classd_snd_controls[] = {
  180. SOC_DOUBLE_TLV("Playback Volume", CLASSD_INTPMR,
  181. CLASSD_INTPMR_ATTL_SHIFT, CLASSD_INTPMR_ATTR_SHIFT,
  182. 78, 1, classd_digital_tlv),
  183. SOC_SINGLE("Deemphasis Switch", CLASSD_INTPMR,
  184. CLASSD_INTPMR_DEEMP_SHIFT, 1, 0),
  185. SOC_SINGLE("Mono Switch", CLASSD_INTPMR, CLASSD_INTPMR_MONO_SHIFT, 1, 0),
  186. SOC_SINGLE("Swap Switch", CLASSD_INTPMR, CLASSD_INTPMR_SWAP_SHIFT, 1, 0),
  187. SOC_ENUM("Mono Mode", classd_mono_mode_enum),
  188. SOC_ENUM("EQ", classd_eqcfg_enum),
  189. };
  190. static const char * const pwm_type[] = {
  191. "Single ended", "Differential"
  192. };
  193. static int atmel_classd_component_probe(struct snd_soc_component *component)
  194. {
  195. struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
  196. struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
  197. const struct atmel_classd_pdata *pdata = dd->pdata;
  198. u32 mask, val;
  199. mask = CLASSD_MR_PWMTYP_MASK;
  200. val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT;
  201. mask |= CLASSD_MR_NON_OVERLAP_MASK;
  202. if (pdata->non_overlap_enable) {
  203. val |= (CLASSD_MR_NON_OVERLAP_EN
  204. << CLASSD_MR_NON_OVERLAP_SHIFT);
  205. mask |= CLASSD_MR_NOVR_VAL_MASK;
  206. switch (pdata->non_overlap_time) {
  207. case 5:
  208. val |= (CLASSD_MR_NOVR_VAL_5NS
  209. << CLASSD_MR_NOVR_VAL_SHIFT);
  210. break;
  211. case 10:
  212. val |= (CLASSD_MR_NOVR_VAL_10NS
  213. << CLASSD_MR_NOVR_VAL_SHIFT);
  214. break;
  215. case 15:
  216. val |= (CLASSD_MR_NOVR_VAL_15NS
  217. << CLASSD_MR_NOVR_VAL_SHIFT);
  218. break;
  219. case 20:
  220. val |= (CLASSD_MR_NOVR_VAL_20NS
  221. << CLASSD_MR_NOVR_VAL_SHIFT);
  222. break;
  223. default:
  224. val |= (CLASSD_MR_NOVR_VAL_10NS
  225. << CLASSD_MR_NOVR_VAL_SHIFT);
  226. dev_warn(component->dev,
  227. "non-overlapping value %d is invalid, the default value 10 is specified\n",
  228. pdata->non_overlap_time);
  229. break;
  230. }
  231. }
  232. snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
  233. dev_info(component->dev,
  234. "PWM modulation type is %s, non-overlapping is %s\n",
  235. pwm_type[pdata->pwm_type],
  236. pdata->non_overlap_enable?"enabled":"disabled");
  237. return 0;
  238. }
  239. static int atmel_classd_component_resume(struct snd_soc_component *component)
  240. {
  241. struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
  242. struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
  243. return regcache_sync(dd->regmap);
  244. }
  245. static int atmel_classd_cpu_dai_mute_stream(struct snd_soc_dai *cpu_dai,
  246. int mute, int direction)
  247. {
  248. struct snd_soc_component *component = cpu_dai->component;
  249. u32 mask, val;
  250. mask = CLASSD_MR_LMUTE_MASK | CLASSD_MR_RMUTE_MASK;
  251. if (mute)
  252. val = mask;
  253. else
  254. val = 0;
  255. snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
  256. return 0;
  257. }
  258. #define CLASSD_GCLK_RATE_11M2896_MPY_8 (112896 * 100 * 8)
  259. #define CLASSD_GCLK_RATE_12M288_MPY_8 (12288 * 1000 * 8)
  260. static struct {
  261. int rate;
  262. int sample_rate;
  263. int dsp_clk;
  264. unsigned long gclk_rate;
  265. } const sample_rates[] = {
  266. { 8000, CLASSD_INTPMR_FRAME_8K,
  267. CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
  268. { 16000, CLASSD_INTPMR_FRAME_16K,
  269. CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
  270. { 32000, CLASSD_INTPMR_FRAME_32K,
  271. CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
  272. { 48000, CLASSD_INTPMR_FRAME_48K,
  273. CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
  274. { 96000, CLASSD_INTPMR_FRAME_96K,
  275. CLASSD_INTPMR_DSP_CLK_FREQ_12M288, CLASSD_GCLK_RATE_12M288_MPY_8 },
  276. { 22050, CLASSD_INTPMR_FRAME_22K,
  277. CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
  278. { 44100, CLASSD_INTPMR_FRAME_44K,
  279. CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
  280. { 88200, CLASSD_INTPMR_FRAME_88K,
  281. CLASSD_INTPMR_DSP_CLK_FREQ_11M2896, CLASSD_GCLK_RATE_11M2896_MPY_8 },
  282. };
  283. static int
  284. atmel_classd_cpu_dai_hw_params(struct snd_pcm_substream *substream,
  285. struct snd_pcm_hw_params *params,
  286. struct snd_soc_dai *cpu_dai)
  287. {
  288. struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  289. struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
  290. struct snd_soc_component *component = cpu_dai->component;
  291. int fs;
  292. int i, best, best_val, cur_val, ret;
  293. u32 mask, val;
  294. fs = params_rate(params);
  295. best = 0;
  296. best_val = abs(fs - sample_rates[0].rate);
  297. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  298. /* Closest match */
  299. cur_val = abs(fs - sample_rates[i].rate);
  300. if (cur_val < best_val) {
  301. best = i;
  302. best_val = cur_val;
  303. }
  304. }
  305. dev_dbg(component->dev,
  306. "Selected SAMPLE_RATE of %dHz, GCLK_RATE of %ldHz\n",
  307. sample_rates[best].rate, sample_rates[best].gclk_rate);
  308. clk_disable_unprepare(dd->gclk);
  309. ret = clk_set_rate(dd->gclk, sample_rates[best].gclk_rate);
  310. if (ret)
  311. return ret;
  312. mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK;
  313. val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT)
  314. | (sample_rates[best].sample_rate << CLASSD_INTPMR_FRAME_SHIFT);
  315. snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val);
  316. return clk_prepare_enable(dd->gclk);
  317. }
  318. static void
  319. atmel_classd_cpu_dai_shutdown(struct snd_pcm_substream *substream,
  320. struct snd_soc_dai *cpu_dai)
  321. {
  322. struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
  323. struct atmel_classd *dd = snd_soc_card_get_drvdata(rtd->card);
  324. clk_disable_unprepare(dd->gclk);
  325. }
  326. static int atmel_classd_cpu_dai_prepare(struct snd_pcm_substream *substream,
  327. struct snd_soc_dai *cpu_dai)
  328. {
  329. struct snd_soc_component *component = cpu_dai->component;
  330. snd_soc_component_update_bits(component, CLASSD_MR,
  331. CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK,
  332. (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
  333. |(CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT));
  334. return 0;
  335. }
  336. static int atmel_classd_cpu_dai_trigger(struct snd_pcm_substream *substream,
  337. int cmd, struct snd_soc_dai *cpu_dai)
  338. {
  339. struct snd_soc_component *component = cpu_dai->component;
  340. u32 mask, val;
  341. mask = CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK;
  342. switch (cmd) {
  343. case SNDRV_PCM_TRIGGER_START:
  344. case SNDRV_PCM_TRIGGER_RESUME:
  345. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  346. val = mask;
  347. break;
  348. case SNDRV_PCM_TRIGGER_STOP:
  349. case SNDRV_PCM_TRIGGER_SUSPEND:
  350. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  351. val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
  352. | (CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT);
  353. break;
  354. default:
  355. return -EINVAL;
  356. }
  357. snd_soc_component_update_bits(component, CLASSD_MR, mask, val);
  358. return 0;
  359. }
  360. static const struct snd_soc_dai_ops atmel_classd_cpu_dai_ops = {
  361. .startup = atmel_classd_cpu_dai_startup,
  362. .shutdown = atmel_classd_cpu_dai_shutdown,
  363. .mute_stream = atmel_classd_cpu_dai_mute_stream,
  364. .hw_params = atmel_classd_cpu_dai_hw_params,
  365. .prepare = atmel_classd_cpu_dai_prepare,
  366. .trigger = atmel_classd_cpu_dai_trigger,
  367. .no_capture_mute = 1,
  368. };
  369. static struct snd_soc_dai_driver atmel_classd_cpu_dai = {
  370. .playback = {
  371. .stream_name = "Playback",
  372. .channels_min = 1,
  373. .channels_max = 2,
  374. .rates = ATMEL_CLASSD_RATES,
  375. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  376. },
  377. .ops = &atmel_classd_cpu_dai_ops,
  378. };
  379. static const struct snd_soc_component_driver atmel_classd_cpu_dai_component = {
  380. .name = "atmel-classd",
  381. .probe = atmel_classd_component_probe,
  382. .resume = atmel_classd_component_resume,
  383. .controls = atmel_classd_snd_controls,
  384. .num_controls = ARRAY_SIZE(atmel_classd_snd_controls),
  385. .idle_bias_on = 1,
  386. .use_pmdown_time = 1,
  387. .legacy_dai_naming = 1,
  388. };
  389. /* ASoC sound card */
  390. static int atmel_classd_asoc_card_init(struct device *dev,
  391. struct snd_soc_card *card)
  392. {
  393. struct snd_soc_dai_link *dai_link;
  394. struct atmel_classd *dd = snd_soc_card_get_drvdata(card);
  395. struct snd_soc_dai_link_component *comp;
  396. dai_link = devm_kzalloc(dev, sizeof(*dai_link), GFP_KERNEL);
  397. if (!dai_link)
  398. return -ENOMEM;
  399. comp = devm_kzalloc(dev, 2 * sizeof(*comp), GFP_KERNEL);
  400. if (!comp)
  401. return -ENOMEM;
  402. dai_link->cpus = &comp[0];
  403. dai_link->codecs = &snd_soc_dummy_dlc;
  404. dai_link->platforms = &comp[1];
  405. dai_link->num_cpus = 1;
  406. dai_link->num_codecs = 1;
  407. dai_link->num_platforms = 1;
  408. dai_link->name = "CLASSD";
  409. dai_link->stream_name = "CLASSD PCM";
  410. dai_link->cpus->dai_name = dev_name(dev);
  411. dai_link->platforms->name = dev_name(dev);
  412. card->dai_link = dai_link;
  413. card->num_links = 1;
  414. card->name = dd->pdata->card_name;
  415. card->dev = dev;
  416. return 0;
  417. };
  418. /* regmap configuration */
  419. static const struct reg_default atmel_classd_reg_defaults[] = {
  420. { CLASSD_INTPMR, 0x00301212 },
  421. };
  422. #define ATMEL_CLASSD_REG_MAX 0xE4
  423. static const struct regmap_config atmel_classd_regmap_config = {
  424. .reg_bits = 32,
  425. .reg_stride = 4,
  426. .val_bits = 32,
  427. .max_register = ATMEL_CLASSD_REG_MAX,
  428. .cache_type = REGCACHE_FLAT,
  429. .reg_defaults = atmel_classd_reg_defaults,
  430. .num_reg_defaults = ARRAY_SIZE(atmel_classd_reg_defaults),
  431. };
  432. static int atmel_classd_probe(struct platform_device *pdev)
  433. {
  434. struct device *dev = &pdev->dev;
  435. struct atmel_classd *dd;
  436. struct resource *res;
  437. void __iomem *io_base;
  438. const struct atmel_classd_pdata *pdata;
  439. struct snd_soc_card *card;
  440. int ret;
  441. pdata = dev_get_platdata(dev);
  442. if (!pdata) {
  443. pdata = atmel_classd_dt_init(dev);
  444. if (IS_ERR(pdata))
  445. return PTR_ERR(pdata);
  446. }
  447. dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
  448. if (!dd)
  449. return -ENOMEM;
  450. dd->pdata = pdata;
  451. dd->irq = platform_get_irq(pdev, 0);
  452. if (dd->irq < 0)
  453. return dd->irq;
  454. dd->pclk = devm_clk_get(dev, "pclk");
  455. if (IS_ERR(dd->pclk)) {
  456. ret = PTR_ERR(dd->pclk);
  457. dev_err(dev, "failed to get peripheral clock: %d\n", ret);
  458. return ret;
  459. }
  460. dd->gclk = devm_clk_get(dev, "gclk");
  461. if (IS_ERR(dd->gclk)) {
  462. ret = PTR_ERR(dd->gclk);
  463. dev_err(dev, "failed to get GCK clock: %d\n", ret);
  464. return ret;
  465. }
  466. io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
  467. if (IS_ERR(io_base))
  468. return PTR_ERR(io_base);
  469. dd->phy_base = res->start;
  470. dd->dev = dev;
  471. dd->regmap = devm_regmap_init_mmio(dev, io_base,
  472. &atmel_classd_regmap_config);
  473. if (IS_ERR(dd->regmap)) {
  474. ret = PTR_ERR(dd->regmap);
  475. dev_err(dev, "failed to init register map: %d\n", ret);
  476. return ret;
  477. }
  478. ret = devm_snd_soc_register_component(dev,
  479. &atmel_classd_cpu_dai_component,
  480. &atmel_classd_cpu_dai, 1);
  481. if (ret) {
  482. dev_err(dev, "could not register CPU DAI: %d\n", ret);
  483. return ret;
  484. }
  485. ret = devm_snd_dmaengine_pcm_register(dev,
  486. &atmel_classd_dmaengine_pcm_config,
  487. 0);
  488. if (ret) {
  489. dev_err(dev, "could not register platform: %d\n", ret);
  490. return ret;
  491. }
  492. /* register sound card */
  493. card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
  494. if (!card) {
  495. ret = -ENOMEM;
  496. goto unregister_codec;
  497. }
  498. snd_soc_card_set_drvdata(card, dd);
  499. ret = atmel_classd_asoc_card_init(dev, card);
  500. if (ret) {
  501. dev_err(dev, "failed to init sound card\n");
  502. goto unregister_codec;
  503. }
  504. ret = devm_snd_soc_register_card(dev, card);
  505. if (ret) {
  506. dev_err(dev, "failed to register sound card: %d\n", ret);
  507. goto unregister_codec;
  508. }
  509. return 0;
  510. unregister_codec:
  511. return ret;
  512. }
  513. static struct platform_driver atmel_classd_driver = {
  514. .driver = {
  515. .name = "atmel-classd",
  516. .of_match_table = of_match_ptr(atmel_classd_of_match),
  517. .pm = &snd_soc_pm_ops,
  518. },
  519. .probe = atmel_classd_probe,
  520. };
  521. module_platform_driver(atmel_classd_driver);
  522. MODULE_DESCRIPTION("Atmel ClassD driver under ALSA SoC architecture");
  523. MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
  524. MODULE_LICENSE("GPL");