skl.c 3.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. //
  3. // This file is provided under a dual BSD/GPLv2 license. When using or
  4. // redistributing this file, you may do so under either license.
  5. //
  6. // Copyright(c) 2018-2022 Intel Corporation
  7. //
  8. /*
  9. * Hardware interface for audio DSP on Skylake and Kabylake.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/firmware.h>
  15. #include <linux/fs.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/slab.h>
  19. #include <linux/pci.h>
  20. #include <sound/hdaudio_ext.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/sof.h>
  23. #include <sound/sof/ext_manifest4.h>
  24. #include "../sof-priv.h"
  25. #include "../ipc4-priv.h"
  26. #include "../ops.h"
  27. #include "hda.h"
  28. #include "../sof-audio.h"
  29. #define SRAM_MEMORY_WINDOW_BASE 0x8000
  30. static const __maybe_unused struct snd_sof_debugfs_map skl_dsp_debugfs[] = {
  31. {"hda", HDA_DSP_HDA_BAR, 0, 0x4000},
  32. {"pp", HDA_DSP_PP_BAR, 0, 0x1000},
  33. {"dsp", HDA_DSP_BAR, 0, 0x10000},
  34. };
  35. static int skl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id)
  36. {
  37. return SRAM_MEMORY_WINDOW_BASE + (0x2000 * id);
  38. }
  39. static int skl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
  40. {
  41. return SRAM_MEMORY_WINDOW_BASE + 0x1000;
  42. }
  43. /* skylake ops */
  44. struct snd_sof_dsp_ops sof_skl_ops;
  45. EXPORT_SYMBOL_NS(sof_skl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
  46. int sof_skl_ops_init(struct snd_sof_dev *sdev)
  47. {
  48. struct sof_ipc4_fw_data *ipc4_data;
  49. /* common defaults */
  50. memcpy(&sof_skl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
  51. /* probe/remove/shutdown */
  52. sof_skl_ops.shutdown = hda_dsp_shutdown;
  53. sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL);
  54. if (!sdev->private)
  55. return -ENOMEM;
  56. ipc4_data = sdev->private;
  57. ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5;
  58. ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_1_5;
  59. sof_skl_ops.get_window_offset = skl_dsp_ipc_get_window_offset;
  60. sof_skl_ops.get_mailbox_offset = skl_dsp_ipc_get_mailbox_offset;
  61. /* doorbell */
  62. sof_skl_ops.irq_thread = hda_dsp_ipc4_irq_thread;
  63. /* ipc */
  64. sof_skl_ops.send_msg = hda_dsp_ipc4_send_msg;
  65. /* set DAI driver ops */
  66. hda_set_dai_drv_ops(sdev, &sof_skl_ops);
  67. /* debug */
  68. sof_skl_ops.debug_map = skl_dsp_debugfs;
  69. sof_skl_ops.debug_map_count = ARRAY_SIZE(skl_dsp_debugfs);
  70. sof_skl_ops.ipc_dump = hda_ipc4_dump;
  71. /* firmware run */
  72. sof_skl_ops.run = hda_dsp_cl_boot_firmware_skl;
  73. /* pre/post fw run */
  74. sof_skl_ops.post_fw_run = hda_dsp_post_fw_run;
  75. return 0;
  76. };
  77. EXPORT_SYMBOL_NS(sof_skl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
  78. const struct sof_intel_dsp_desc skl_chip_info = {
  79. .cores_num = 2,
  80. .init_core_mask = 1,
  81. .host_managed_cores_mask = GENMASK(1, 0),
  82. .ipc_req = HDA_DSP_REG_HIPCI,
  83. .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
  84. .ipc_ack = HDA_DSP_REG_HIPCIE,
  85. .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
  86. .ipc_ctl = HDA_DSP_REG_HIPCCTL,
  87. .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS_SKL,
  88. .rom_init_timeout = 300,
  89. .check_ipc_irq = hda_dsp_check_ipc_irq,
  90. .power_down_dsp = hda_power_down_dsp,
  91. .disable_interrupts = hda_dsp_disable_interrupts,
  92. .hw_ip_version = SOF_INTEL_CAVS_1_5,
  93. };
  94. EXPORT_SYMBOL_NS(skl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);