ipc3.c 30 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. //
  3. // This file is provided under a dual BSD/GPLv2 license. When using or
  4. // redistributing this file, you may do so under either license.
  5. //
  6. // Copyright(c) 2021 Intel Corporation
  7. //
  8. //
  9. #include <sound/sof/stream.h>
  10. #include <sound/sof/control.h>
  11. #include <trace/events/sof.h>
  12. #include "sof-priv.h"
  13. #include "sof-audio.h"
  14. #include "ipc3-priv.h"
  15. #include "ops.h"
  16. typedef void (*ipc3_rx_callback)(struct snd_sof_dev *sdev, void *msg_buf);
  17. #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
  18. static void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
  19. {
  20. u8 *str;
  21. u8 *str2 = NULL;
  22. u32 glb;
  23. u32 type;
  24. bool is_sof_ipc_stream_position = false;
  25. glb = cmd & SOF_GLB_TYPE_MASK;
  26. type = cmd & SOF_CMD_TYPE_MASK;
  27. switch (glb) {
  28. case SOF_IPC_GLB_REPLY:
  29. str = "GLB_REPLY"; break;
  30. case SOF_IPC_GLB_COMPOUND:
  31. str = "GLB_COMPOUND"; break;
  32. case SOF_IPC_GLB_TPLG_MSG:
  33. str = "GLB_TPLG_MSG";
  34. switch (type) {
  35. case SOF_IPC_TPLG_COMP_NEW:
  36. str2 = "COMP_NEW"; break;
  37. case SOF_IPC_TPLG_COMP_FREE:
  38. str2 = "COMP_FREE"; break;
  39. case SOF_IPC_TPLG_COMP_CONNECT:
  40. str2 = "COMP_CONNECT"; break;
  41. case SOF_IPC_TPLG_PIPE_NEW:
  42. str2 = "PIPE_NEW"; break;
  43. case SOF_IPC_TPLG_PIPE_FREE:
  44. str2 = "PIPE_FREE"; break;
  45. case SOF_IPC_TPLG_PIPE_CONNECT:
  46. str2 = "PIPE_CONNECT"; break;
  47. case SOF_IPC_TPLG_PIPE_COMPLETE:
  48. str2 = "PIPE_COMPLETE"; break;
  49. case SOF_IPC_TPLG_BUFFER_NEW:
  50. str2 = "BUFFER_NEW"; break;
  51. case SOF_IPC_TPLG_BUFFER_FREE:
  52. str2 = "BUFFER_FREE"; break;
  53. default:
  54. str2 = "unknown type"; break;
  55. }
  56. break;
  57. case SOF_IPC_GLB_PM_MSG:
  58. str = "GLB_PM_MSG";
  59. switch (type) {
  60. case SOF_IPC_PM_CTX_SAVE:
  61. str2 = "CTX_SAVE"; break;
  62. case SOF_IPC_PM_CTX_RESTORE:
  63. str2 = "CTX_RESTORE"; break;
  64. case SOF_IPC_PM_CTX_SIZE:
  65. str2 = "CTX_SIZE"; break;
  66. case SOF_IPC_PM_CLK_SET:
  67. str2 = "CLK_SET"; break;
  68. case SOF_IPC_PM_CLK_GET:
  69. str2 = "CLK_GET"; break;
  70. case SOF_IPC_PM_CLK_REQ:
  71. str2 = "CLK_REQ"; break;
  72. case SOF_IPC_PM_CORE_ENABLE:
  73. str2 = "CORE_ENABLE"; break;
  74. case SOF_IPC_PM_GATE:
  75. str2 = "GATE"; break;
  76. default:
  77. str2 = "unknown type"; break;
  78. }
  79. break;
  80. case SOF_IPC_GLB_COMP_MSG:
  81. str = "GLB_COMP_MSG";
  82. switch (type) {
  83. case SOF_IPC_COMP_SET_VALUE:
  84. str2 = "SET_VALUE"; break;
  85. case SOF_IPC_COMP_GET_VALUE:
  86. str2 = "GET_VALUE"; break;
  87. case SOF_IPC_COMP_SET_DATA:
  88. str2 = "SET_DATA"; break;
  89. case SOF_IPC_COMP_GET_DATA:
  90. str2 = "GET_DATA"; break;
  91. default:
  92. str2 = "unknown type"; break;
  93. }
  94. break;
  95. case SOF_IPC_GLB_STREAM_MSG:
  96. str = "GLB_STREAM_MSG";
  97. switch (type) {
  98. case SOF_IPC_STREAM_PCM_PARAMS:
  99. str2 = "PCM_PARAMS"; break;
  100. case SOF_IPC_STREAM_PCM_PARAMS_REPLY:
  101. str2 = "PCM_REPLY"; break;
  102. case SOF_IPC_STREAM_PCM_FREE:
  103. str2 = "PCM_FREE"; break;
  104. case SOF_IPC_STREAM_TRIG_START:
  105. str2 = "TRIG_START"; break;
  106. case SOF_IPC_STREAM_TRIG_STOP:
  107. str2 = "TRIG_STOP"; break;
  108. case SOF_IPC_STREAM_TRIG_PAUSE:
  109. str2 = "TRIG_PAUSE"; break;
  110. case SOF_IPC_STREAM_TRIG_RELEASE:
  111. str2 = "TRIG_RELEASE"; break;
  112. case SOF_IPC_STREAM_TRIG_DRAIN:
  113. str2 = "TRIG_DRAIN"; break;
  114. case SOF_IPC_STREAM_TRIG_XRUN:
  115. str2 = "TRIG_XRUN"; break;
  116. case SOF_IPC_STREAM_POSITION:
  117. is_sof_ipc_stream_position = true;
  118. str2 = "POSITION"; break;
  119. case SOF_IPC_STREAM_VORBIS_PARAMS:
  120. str2 = "VORBIS_PARAMS"; break;
  121. case SOF_IPC_STREAM_VORBIS_FREE:
  122. str2 = "VORBIS_FREE"; break;
  123. default:
  124. str2 = "unknown type"; break;
  125. }
  126. break;
  127. case SOF_IPC_FW_READY:
  128. str = "FW_READY"; break;
  129. case SOF_IPC_GLB_DAI_MSG:
  130. str = "GLB_DAI_MSG";
  131. switch (type) {
  132. case SOF_IPC_DAI_CONFIG:
  133. str2 = "CONFIG"; break;
  134. case SOF_IPC_DAI_LOOPBACK:
  135. str2 = "LOOPBACK"; break;
  136. default:
  137. str2 = "unknown type"; break;
  138. }
  139. break;
  140. case SOF_IPC_GLB_TRACE_MSG:
  141. str = "GLB_TRACE_MSG";
  142. switch (type) {
  143. case SOF_IPC_TRACE_DMA_PARAMS:
  144. str2 = "DMA_PARAMS"; break;
  145. case SOF_IPC_TRACE_DMA_POSITION:
  146. if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
  147. return;
  148. str2 = "DMA_POSITION"; break;
  149. case SOF_IPC_TRACE_DMA_PARAMS_EXT:
  150. str2 = "DMA_PARAMS_EXT"; break;
  151. case SOF_IPC_TRACE_FILTER_UPDATE:
  152. str2 = "FILTER_UPDATE"; break;
  153. case SOF_IPC_TRACE_DMA_FREE:
  154. str2 = "DMA_FREE"; break;
  155. default:
  156. str2 = "unknown type"; break;
  157. }
  158. break;
  159. case SOF_IPC_GLB_TEST_MSG:
  160. str = "GLB_TEST_MSG";
  161. switch (type) {
  162. case SOF_IPC_TEST_IPC_FLOOD:
  163. str2 = "IPC_FLOOD"; break;
  164. default:
  165. str2 = "unknown type"; break;
  166. }
  167. break;
  168. case SOF_IPC_GLB_DEBUG:
  169. str = "GLB_DEBUG";
  170. switch (type) {
  171. case SOF_IPC_DEBUG_MEM_USAGE:
  172. str2 = "MEM_USAGE"; break;
  173. default:
  174. str2 = "unknown type"; break;
  175. }
  176. break;
  177. case SOF_IPC_GLB_PROBE:
  178. str = "GLB_PROBE";
  179. switch (type) {
  180. case SOF_IPC_PROBE_INIT:
  181. str2 = "INIT"; break;
  182. case SOF_IPC_PROBE_DEINIT:
  183. str2 = "DEINIT"; break;
  184. case SOF_IPC_PROBE_DMA_ADD:
  185. str2 = "DMA_ADD"; break;
  186. case SOF_IPC_PROBE_DMA_INFO:
  187. str2 = "DMA_INFO"; break;
  188. case SOF_IPC_PROBE_DMA_REMOVE:
  189. str2 = "DMA_REMOVE"; break;
  190. case SOF_IPC_PROBE_POINT_ADD:
  191. str2 = "POINT_ADD"; break;
  192. case SOF_IPC_PROBE_POINT_INFO:
  193. str2 = "POINT_INFO"; break;
  194. case SOF_IPC_PROBE_POINT_REMOVE:
  195. str2 = "POINT_REMOVE"; break;
  196. default:
  197. str2 = "unknown type"; break;
  198. }
  199. break;
  200. default:
  201. str = "unknown GLB command"; break;
  202. }
  203. if (str2) {
  204. if (is_sof_ipc_stream_position)
  205. trace_sof_stream_position_ipc_rx(dev);
  206. else
  207. dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
  208. } else {
  209. dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str);
  210. }
  211. }
  212. #else
  213. static inline void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
  214. {
  215. if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG)
  216. dev_dbg(dev, "%s: 0x%x\n", text, cmd);
  217. }
  218. #endif
  219. static void sof_ipc3_dump_payload(struct snd_sof_dev *sdev,
  220. void *ipc_data, size_t size)
  221. {
  222. printk(KERN_DEBUG "Size of payload following the header: %zu\n", size);
  223. print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
  224. 16, 4, ipc_data, size, false);
  225. }
  226. static int sof_ipc3_get_reply(struct snd_sof_dev *sdev)
  227. {
  228. struct snd_sof_ipc_msg *msg = sdev->msg;
  229. struct sof_ipc_reply *reply;
  230. int ret = 0;
  231. /* get the generic reply */
  232. reply = msg->reply_data;
  233. snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, reply, sizeof(*reply));
  234. if (reply->error < 0)
  235. return reply->error;
  236. if (!reply->hdr.size) {
  237. /* Reply should always be >= sizeof(struct sof_ipc_reply) */
  238. if (msg->reply_size)
  239. dev_err(sdev->dev,
  240. "empty reply received, expected %zu bytes\n",
  241. msg->reply_size);
  242. else
  243. dev_err(sdev->dev, "empty reply received\n");
  244. return -EINVAL;
  245. }
  246. if (msg->reply_size > 0) {
  247. if (reply->hdr.size == msg->reply_size) {
  248. ret = 0;
  249. } else if (reply->hdr.size < msg->reply_size) {
  250. dev_dbg(sdev->dev,
  251. "reply size (%u) is less than expected (%zu)\n",
  252. reply->hdr.size, msg->reply_size);
  253. msg->reply_size = reply->hdr.size;
  254. ret = 0;
  255. } else {
  256. dev_err(sdev->dev,
  257. "reply size (%u) exceeds the buffer size (%zu)\n",
  258. reply->hdr.size, msg->reply_size);
  259. ret = -EINVAL;
  260. }
  261. /*
  262. * get the full message if reply->hdr.size <= msg->reply_size
  263. * and the reply->hdr.size > sizeof(struct sof_ipc_reply)
  264. */
  265. if (!ret && msg->reply_size > sizeof(*reply))
  266. snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset,
  267. msg->reply_data, msg->reply_size);
  268. }
  269. return ret;
  270. }
  271. /* wait for IPC message reply */
  272. static int ipc3_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
  273. {
  274. struct snd_sof_ipc_msg *msg = &ipc->msg;
  275. struct sof_ipc_cmd_hdr *hdr = msg->msg_data;
  276. struct snd_sof_dev *sdev = ipc->sdev;
  277. int ret;
  278. /* wait for DSP IPC completion */
  279. ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
  280. msecs_to_jiffies(sdev->ipc_timeout));
  281. if (ret == 0) {
  282. dev_err(sdev->dev,
  283. "ipc tx timed out for %#x (msg/reply size: %d/%zu)\n",
  284. hdr->cmd, hdr->size, msg->reply_size);
  285. snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
  286. ret = -ETIMEDOUT;
  287. } else {
  288. ret = msg->reply_error;
  289. if (ret < 0) {
  290. dev_err(sdev->dev,
  291. "ipc tx error for %#x (msg/reply size: %d/%zu): %d\n",
  292. hdr->cmd, hdr->size, msg->reply_size, ret);
  293. } else {
  294. if (sof_debug_check_flag(SOF_DBG_PRINT_IPC_SUCCESS_LOGS))
  295. ipc3_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd);
  296. if (reply_data && msg->reply_size)
  297. /* copy the data returned from DSP */
  298. memcpy(reply_data, msg->reply_data,
  299. msg->reply_size);
  300. }
  301. /* re-enable dumps after successful IPC tx */
  302. if (sdev->ipc_dump_printed) {
  303. sdev->dbg_dump_printed = false;
  304. sdev->ipc_dump_printed = false;
  305. }
  306. }
  307. return ret;
  308. }
  309. /* send IPC message from host to DSP */
  310. static int ipc3_tx_msg_unlocked(struct snd_sof_ipc *ipc,
  311. void *msg_data, size_t msg_bytes,
  312. void *reply_data, size_t reply_bytes)
  313. {
  314. struct sof_ipc_cmd_hdr *hdr = msg_data;
  315. struct snd_sof_dev *sdev = ipc->sdev;
  316. int ret;
  317. ipc3_log_header(sdev->dev, "ipc tx", hdr->cmd);
  318. ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
  319. if (ret) {
  320. dev_err_ratelimited(sdev->dev,
  321. "%s: ipc message send for %#x failed: %d\n",
  322. __func__, hdr->cmd, ret);
  323. return ret;
  324. }
  325. /* now wait for completion */
  326. return ipc3_wait_tx_done(ipc, reply_data);
  327. }
  328. static int sof_ipc3_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
  329. void *reply_data, size_t reply_bytes, bool no_pm)
  330. {
  331. struct snd_sof_ipc *ipc = sdev->ipc;
  332. int ret;
  333. if (!msg_data || msg_bytes < sizeof(struct sof_ipc_cmd_hdr)) {
  334. dev_err_ratelimited(sdev->dev, "No IPC message to send\n");
  335. return -EINVAL;
  336. }
  337. if (!no_pm) {
  338. const struct sof_dsp_power_state target_state = {
  339. .state = SOF_DSP_PM_D0,
  340. };
  341. /* ensure the DSP is in D0 before sending a new IPC */
  342. ret = snd_sof_dsp_set_power_state(sdev, &target_state);
  343. if (ret < 0) {
  344. dev_err(sdev->dev, "%s: resuming DSP failed: %d\n",
  345. __func__, ret);
  346. return ret;
  347. }
  348. }
  349. /* Serialise IPC TX */
  350. mutex_lock(&ipc->tx_mutex);
  351. ret = ipc3_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
  352. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
  353. size_t payload_bytes, header_bytes;
  354. char *payload = NULL;
  355. /* payload is indicated by non zero msg/reply_bytes */
  356. if (msg_bytes > sizeof(struct sof_ipc_cmd_hdr)) {
  357. payload = msg_data;
  358. header_bytes = sizeof(struct sof_ipc_cmd_hdr);
  359. payload_bytes = msg_bytes - header_bytes;
  360. } else if (reply_bytes > sizeof(struct sof_ipc_reply)) {
  361. payload = reply_data;
  362. header_bytes = sizeof(struct sof_ipc_reply);
  363. payload_bytes = reply_bytes - header_bytes;
  364. }
  365. if (payload) {
  366. payload += header_bytes;
  367. sof_ipc3_dump_payload(sdev, payload, payload_bytes);
  368. }
  369. }
  370. mutex_unlock(&ipc->tx_mutex);
  371. return ret;
  372. }
  373. static int sof_ipc3_set_get_data(struct snd_sof_dev *sdev, void *data, size_t data_bytes,
  374. bool set)
  375. {
  376. size_t msg_bytes, hdr_bytes, payload_size, send_bytes;
  377. struct sof_ipc_ctrl_data *cdata = data;
  378. struct sof_ipc_ctrl_data *cdata_chunk;
  379. struct snd_sof_ipc *ipc = sdev->ipc;
  380. size_t offset = 0;
  381. u8 *src, *dst;
  382. u32 num_msg;
  383. int ret = 0;
  384. int i;
  385. if (!cdata || data_bytes < sizeof(*cdata))
  386. return -EINVAL;
  387. if ((cdata->rhdr.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_COMP_MSG) {
  388. dev_err(sdev->dev, "%s: Not supported message type of %#x\n",
  389. __func__, cdata->rhdr.hdr.cmd);
  390. return -EINVAL;
  391. }
  392. /* send normal size ipc in one part */
  393. if (cdata->rhdr.hdr.size <= ipc->max_payload_size)
  394. return sof_ipc3_tx_msg(sdev, cdata, cdata->rhdr.hdr.size,
  395. cdata, cdata->rhdr.hdr.size, false);
  396. cdata_chunk = kzalloc(ipc->max_payload_size, GFP_KERNEL);
  397. if (!cdata_chunk)
  398. return -ENOMEM;
  399. switch (cdata->type) {
  400. case SOF_CTRL_TYPE_VALUE_CHAN_GET:
  401. case SOF_CTRL_TYPE_VALUE_CHAN_SET:
  402. hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
  403. if (set) {
  404. src = (u8 *)cdata->chanv;
  405. dst = (u8 *)cdata_chunk->chanv;
  406. } else {
  407. src = (u8 *)cdata_chunk->chanv;
  408. dst = (u8 *)cdata->chanv;
  409. }
  410. break;
  411. case SOF_CTRL_TYPE_DATA_GET:
  412. case SOF_CTRL_TYPE_DATA_SET:
  413. hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + sizeof(struct sof_abi_hdr);
  414. if (set) {
  415. src = (u8 *)cdata->data->data;
  416. dst = (u8 *)cdata_chunk->data->data;
  417. } else {
  418. src = (u8 *)cdata_chunk->data->data;
  419. dst = (u8 *)cdata->data->data;
  420. }
  421. break;
  422. default:
  423. kfree(cdata_chunk);
  424. return -EINVAL;
  425. }
  426. msg_bytes = cdata->rhdr.hdr.size - hdr_bytes;
  427. payload_size = ipc->max_payload_size - hdr_bytes;
  428. num_msg = DIV_ROUND_UP(msg_bytes, payload_size);
  429. /* copy the header data */
  430. memcpy(cdata_chunk, cdata, hdr_bytes);
  431. /* Serialise IPC TX */
  432. mutex_lock(&sdev->ipc->tx_mutex);
  433. /* copy the payload data in a loop */
  434. for (i = 0; i < num_msg; i++) {
  435. send_bytes = min(msg_bytes, payload_size);
  436. cdata_chunk->num_elems = send_bytes;
  437. cdata_chunk->rhdr.hdr.size = hdr_bytes + send_bytes;
  438. cdata_chunk->msg_index = i;
  439. msg_bytes -= send_bytes;
  440. cdata_chunk->elems_remaining = msg_bytes;
  441. if (set)
  442. memcpy(dst, src + offset, send_bytes);
  443. ret = ipc3_tx_msg_unlocked(sdev->ipc,
  444. cdata_chunk, cdata_chunk->rhdr.hdr.size,
  445. cdata_chunk, cdata_chunk->rhdr.hdr.size);
  446. if (ret < 0)
  447. break;
  448. if (!set)
  449. memcpy(dst + offset, src, send_bytes);
  450. offset += payload_size;
  451. }
  452. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
  453. size_t header_bytes = sizeof(struct sof_ipc_reply);
  454. char *payload = (char *)cdata;
  455. payload += header_bytes;
  456. sof_ipc3_dump_payload(sdev, payload, data_bytes - header_bytes);
  457. }
  458. mutex_unlock(&sdev->ipc->tx_mutex);
  459. kfree(cdata_chunk);
  460. return ret;
  461. }
  462. int sof_ipc3_get_ext_windows(struct snd_sof_dev *sdev,
  463. const struct sof_ipc_ext_data_hdr *ext_hdr)
  464. {
  465. const struct sof_ipc_window *w =
  466. container_of(ext_hdr, struct sof_ipc_window, ext_hdr);
  467. if (w->num_windows == 0 || w->num_windows > SOF_IPC_MAX_ELEMS)
  468. return -EINVAL;
  469. if (sdev->info_window) {
  470. if (memcmp(sdev->info_window, w, ext_hdr->hdr.size)) {
  471. dev_err(sdev->dev, "mismatch between window descriptor from extended manifest and mailbox");
  472. return -EINVAL;
  473. }
  474. return 0;
  475. }
  476. /* keep a local copy of the data */
  477. sdev->info_window = devm_kmemdup(sdev->dev, w, ext_hdr->hdr.size, GFP_KERNEL);
  478. if (!sdev->info_window)
  479. return -ENOMEM;
  480. return 0;
  481. }
  482. int sof_ipc3_get_cc_info(struct snd_sof_dev *sdev,
  483. const struct sof_ipc_ext_data_hdr *ext_hdr)
  484. {
  485. int ret;
  486. const struct sof_ipc_cc_version *cc =
  487. container_of(ext_hdr, struct sof_ipc_cc_version, ext_hdr);
  488. if (sdev->cc_version) {
  489. if (memcmp(sdev->cc_version, cc, cc->ext_hdr.hdr.size)) {
  490. dev_err(sdev->dev,
  491. "Receive diverged cc_version descriptions");
  492. return -EINVAL;
  493. }
  494. return 0;
  495. }
  496. dev_dbg(sdev->dev,
  497. "Firmware info: used compiler %s %d:%d:%d%s used optimization flags %s\n",
  498. cc->name, cc->major, cc->minor, cc->micro, cc->desc, cc->optim);
  499. /* create read-only cc_version debugfs to store compiler version info */
  500. /* use local copy of the cc_version to prevent data corruption */
  501. if (sdev->first_boot) {
  502. sdev->cc_version = devm_kmemdup(sdev->dev, cc, cc->ext_hdr.hdr.size, GFP_KERNEL);
  503. if (!sdev->cc_version)
  504. return -ENOMEM;
  505. ret = snd_sof_debugfs_buf_item(sdev, sdev->cc_version,
  506. cc->ext_hdr.hdr.size,
  507. "cc_version", 0444);
  508. /* errors are only due to memory allocation, not debugfs */
  509. if (ret < 0) {
  510. dev_err(sdev->dev, "snd_sof_debugfs_buf_item failed\n");
  511. return ret;
  512. }
  513. }
  514. return 0;
  515. }
  516. /* parse the extended FW boot data structures from FW boot message */
  517. static int ipc3_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 offset)
  518. {
  519. struct sof_ipc_ext_data_hdr *ext_hdr;
  520. void *ext_data;
  521. int ret = 0;
  522. ext_data = kzalloc(PAGE_SIZE, GFP_KERNEL);
  523. if (!ext_data)
  524. return -ENOMEM;
  525. /* get first header */
  526. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
  527. sizeof(*ext_hdr));
  528. ext_hdr = ext_data;
  529. while (ext_hdr->hdr.cmd == SOF_IPC_FW_READY) {
  530. /* read in ext structure */
  531. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM,
  532. offset + sizeof(*ext_hdr),
  533. (void *)((u8 *)ext_data + sizeof(*ext_hdr)),
  534. ext_hdr->hdr.size - sizeof(*ext_hdr));
  535. dev_dbg(sdev->dev, "found ext header type %d size 0x%x\n",
  536. ext_hdr->type, ext_hdr->hdr.size);
  537. /* process structure data */
  538. switch (ext_hdr->type) {
  539. case SOF_IPC_EXT_WINDOW:
  540. ret = sof_ipc3_get_ext_windows(sdev, ext_hdr);
  541. break;
  542. case SOF_IPC_EXT_CC_INFO:
  543. ret = sof_ipc3_get_cc_info(sdev, ext_hdr);
  544. break;
  545. case SOF_IPC_EXT_UNUSED:
  546. case SOF_IPC_EXT_PROBE_INFO:
  547. case SOF_IPC_EXT_USER_ABI_INFO:
  548. /* They are supported but we don't do anything here */
  549. break;
  550. default:
  551. dev_info(sdev->dev, "unknown ext header type %d size 0x%x\n",
  552. ext_hdr->type, ext_hdr->hdr.size);
  553. ret = 0;
  554. break;
  555. }
  556. if (ret < 0) {
  557. dev_err(sdev->dev, "Failed to parse ext data type %d\n",
  558. ext_hdr->type);
  559. break;
  560. }
  561. /* move to next header */
  562. offset += ext_hdr->hdr.size;
  563. snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
  564. sizeof(*ext_hdr));
  565. ext_hdr = ext_data;
  566. }
  567. kfree(ext_data);
  568. return ret;
  569. }
  570. static void ipc3_get_windows(struct snd_sof_dev *sdev)
  571. {
  572. struct sof_ipc_window_elem *elem;
  573. u32 outbox_offset = 0;
  574. u32 stream_offset = 0;
  575. u32 inbox_offset = 0;
  576. u32 outbox_size = 0;
  577. u32 stream_size = 0;
  578. u32 inbox_size = 0;
  579. u32 debug_size = 0;
  580. u32 debug_offset = 0;
  581. int window_offset;
  582. int i;
  583. if (!sdev->info_window) {
  584. dev_err(sdev->dev, "%s: No window info present\n", __func__);
  585. return;
  586. }
  587. for (i = 0; i < sdev->info_window->num_windows; i++) {
  588. elem = &sdev->info_window->window[i];
  589. window_offset = snd_sof_dsp_get_window_offset(sdev, elem->id);
  590. if (window_offset < 0) {
  591. dev_warn(sdev->dev, "No offset for window %d\n", elem->id);
  592. continue;
  593. }
  594. switch (elem->type) {
  595. case SOF_IPC_REGION_UPBOX:
  596. inbox_offset = window_offset + elem->offset;
  597. inbox_size = elem->size;
  598. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  599. inbox_offset,
  600. elem->size, "inbox",
  601. SOF_DEBUGFS_ACCESS_D0_ONLY);
  602. break;
  603. case SOF_IPC_REGION_DOWNBOX:
  604. outbox_offset = window_offset + elem->offset;
  605. outbox_size = elem->size;
  606. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  607. outbox_offset,
  608. elem->size, "outbox",
  609. SOF_DEBUGFS_ACCESS_D0_ONLY);
  610. break;
  611. case SOF_IPC_REGION_TRACE:
  612. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  613. window_offset + elem->offset,
  614. elem->size, "etrace",
  615. SOF_DEBUGFS_ACCESS_D0_ONLY);
  616. break;
  617. case SOF_IPC_REGION_DEBUG:
  618. debug_offset = window_offset + elem->offset;
  619. debug_size = elem->size;
  620. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  621. window_offset + elem->offset,
  622. elem->size, "debug",
  623. SOF_DEBUGFS_ACCESS_D0_ONLY);
  624. break;
  625. case SOF_IPC_REGION_STREAM:
  626. stream_offset = window_offset + elem->offset;
  627. stream_size = elem->size;
  628. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  629. stream_offset,
  630. elem->size, "stream",
  631. SOF_DEBUGFS_ACCESS_D0_ONLY);
  632. break;
  633. case SOF_IPC_REGION_REGS:
  634. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  635. window_offset + elem->offset,
  636. elem->size, "regs",
  637. SOF_DEBUGFS_ACCESS_D0_ONLY);
  638. break;
  639. case SOF_IPC_REGION_EXCEPTION:
  640. sdev->dsp_oops_offset = window_offset + elem->offset;
  641. snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
  642. window_offset + elem->offset,
  643. elem->size, "exception",
  644. SOF_DEBUGFS_ACCESS_D0_ONLY);
  645. break;
  646. default:
  647. dev_err(sdev->dev, "%s: Illegal window info: %u\n",
  648. __func__, elem->type);
  649. return;
  650. }
  651. }
  652. if (outbox_size == 0 || inbox_size == 0) {
  653. dev_err(sdev->dev, "%s: Illegal mailbox window\n", __func__);
  654. return;
  655. }
  656. sdev->dsp_box.offset = inbox_offset;
  657. sdev->dsp_box.size = inbox_size;
  658. sdev->host_box.offset = outbox_offset;
  659. sdev->host_box.size = outbox_size;
  660. sdev->stream_box.offset = stream_offset;
  661. sdev->stream_box.size = stream_size;
  662. sdev->debug_box.offset = debug_offset;
  663. sdev->debug_box.size = debug_size;
  664. dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
  665. inbox_offset, inbox_size);
  666. dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
  667. outbox_offset, outbox_size);
  668. dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
  669. stream_offset, stream_size);
  670. dev_dbg(sdev->dev, " debug region 0x%x - size 0x%x\n",
  671. debug_offset, debug_size);
  672. }
  673. static int ipc3_init_reply_data_buffer(struct snd_sof_dev *sdev)
  674. {
  675. struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
  676. msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
  677. if (!msg->reply_data)
  678. return -ENOMEM;
  679. sdev->ipc->max_payload_size = SOF_IPC_MSG_MAX_SIZE;
  680. return 0;
  681. }
  682. int sof_ipc3_validate_fw_version(struct snd_sof_dev *sdev)
  683. {
  684. struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
  685. struct sof_ipc_fw_version *v = &ready->version;
  686. dev_info(sdev->dev,
  687. "Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
  688. v->micro, v->tag);
  689. dev_info(sdev->dev,
  690. "Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
  691. SOF_ABI_VERSION_MAJOR(v->abi_version),
  692. SOF_ABI_VERSION_MINOR(v->abi_version),
  693. SOF_ABI_VERSION_PATCH(v->abi_version),
  694. SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
  695. if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
  696. dev_err(sdev->dev, "incompatible FW ABI version\n");
  697. return -EINVAL;
  698. }
  699. if (IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS) &&
  700. SOF_ABI_VERSION_MINOR(v->abi_version) > SOF_ABI_MINOR) {
  701. dev_err(sdev->dev, "FW ABI is more recent than kernel\n");
  702. return -EINVAL;
  703. }
  704. if (ready->flags & SOF_IPC_INFO_BUILD) {
  705. dev_info(sdev->dev,
  706. "Firmware debug build %d on %s-%s - options:\n"
  707. " GDB: %s\n"
  708. " lock debug: %s\n"
  709. " lock vdebug: %s\n",
  710. v->build, v->date, v->time,
  711. (ready->flags & SOF_IPC_INFO_GDB) ?
  712. "enabled" : "disabled",
  713. (ready->flags & SOF_IPC_INFO_LOCKS) ?
  714. "enabled" : "disabled",
  715. (ready->flags & SOF_IPC_INFO_LOCKSV) ?
  716. "enabled" : "disabled");
  717. }
  718. /* copy the fw_version into debugfs at first boot */
  719. memcpy(&sdev->fw_version, v, sizeof(*v));
  720. return 0;
  721. }
  722. static int ipc3_fw_ready(struct snd_sof_dev *sdev, u32 cmd)
  723. {
  724. struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
  725. int offset;
  726. int ret;
  727. /* mailbox must be on 4k boundary */
  728. offset = snd_sof_dsp_get_mailbox_offset(sdev);
  729. if (offset < 0) {
  730. dev_err(sdev->dev, "%s: no mailbox offset\n", __func__);
  731. return offset;
  732. }
  733. dev_dbg(sdev->dev, "DSP is ready 0x%8.8x offset 0x%x\n", cmd, offset);
  734. /* no need to re-check version/ABI for subsequent boots */
  735. if (!sdev->first_boot)
  736. return 0;
  737. /*
  738. * copy data from the DSP FW ready offset
  739. * Subsequent error handling is not needed for BLK_TYPE_SRAM
  740. */
  741. ret = snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, fw_ready,
  742. sizeof(*fw_ready));
  743. if (ret) {
  744. dev_err(sdev->dev,
  745. "Unable to read fw_ready, read from TYPE_SRAM failed\n");
  746. return ret;
  747. }
  748. /* make sure ABI version is compatible */
  749. ret = sof_ipc3_validate_fw_version(sdev);
  750. if (ret < 0)
  751. return ret;
  752. /* now check for extended data */
  753. ipc3_fw_parse_ext_data(sdev, offset + sizeof(struct sof_ipc_fw_ready));
  754. ipc3_get_windows(sdev);
  755. return ipc3_init_reply_data_buffer(sdev);
  756. }
  757. /* IPC stream position. */
  758. static void ipc3_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id)
  759. {
  760. struct snd_soc_component *scomp = sdev->component;
  761. struct snd_sof_pcm_stream *stream;
  762. struct sof_ipc_stream_posn posn;
  763. struct snd_sof_pcm *spcm;
  764. int direction, ret;
  765. spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
  766. if (!spcm) {
  767. dev_err(sdev->dev, "period elapsed for unknown stream, msg_id %d\n",
  768. msg_id);
  769. return;
  770. }
  771. stream = &spcm->stream[direction];
  772. ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
  773. if (ret < 0) {
  774. dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
  775. return;
  776. }
  777. trace_sof_ipc3_period_elapsed_position(sdev, &posn);
  778. memcpy(&stream->posn, &posn, sizeof(posn));
  779. if (spcm->pcm.compress)
  780. snd_sof_compr_fragment_elapsed(stream->cstream);
  781. else if (stream->substream->runtime &&
  782. !stream->substream->runtime->no_period_wakeup)
  783. /* only inform ALSA for period_wakeup mode */
  784. snd_sof_pcm_period_elapsed(stream->substream);
  785. }
  786. /* DSP notifies host of an XRUN within FW */
  787. static void ipc3_xrun(struct snd_sof_dev *sdev, u32 msg_id)
  788. {
  789. struct snd_soc_component *scomp = sdev->component;
  790. struct snd_sof_pcm_stream *stream;
  791. struct sof_ipc_stream_posn posn;
  792. struct snd_sof_pcm *spcm;
  793. int direction, ret;
  794. spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
  795. if (!spcm) {
  796. dev_err(sdev->dev, "XRUN for unknown stream, msg_id %d\n",
  797. msg_id);
  798. return;
  799. }
  800. stream = &spcm->stream[direction];
  801. ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
  802. if (ret < 0) {
  803. dev_warn(sdev->dev, "failed to read overrun position: %d\n", ret);
  804. return;
  805. }
  806. dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n",
  807. posn.host_posn, posn.xrun_comp_id, posn.xrun_size);
  808. #if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP)
  809. /* stop PCM on XRUN - used for pipeline debug */
  810. memcpy(&stream->posn, &posn, sizeof(posn));
  811. snd_pcm_stop_xrun(stream->substream);
  812. #endif
  813. }
  814. /* stream notifications from firmware */
  815. static void ipc3_stream_message(struct snd_sof_dev *sdev, void *msg_buf)
  816. {
  817. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  818. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  819. u32 msg_id = SOF_IPC_MESSAGE_ID(hdr->cmd);
  820. switch (msg_type) {
  821. case SOF_IPC_STREAM_POSITION:
  822. ipc3_period_elapsed(sdev, msg_id);
  823. break;
  824. case SOF_IPC_STREAM_TRIG_XRUN:
  825. ipc3_xrun(sdev, msg_id);
  826. break;
  827. default:
  828. dev_err(sdev->dev, "unhandled stream message %#x\n",
  829. msg_id);
  830. break;
  831. }
  832. }
  833. /* component notifications from firmware */
  834. static void ipc3_comp_notification(struct snd_sof_dev *sdev, void *msg_buf)
  835. {
  836. const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg;
  837. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  838. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  839. switch (msg_type) {
  840. case SOF_IPC_COMP_GET_VALUE:
  841. case SOF_IPC_COMP_GET_DATA:
  842. break;
  843. default:
  844. dev_err(sdev->dev, "unhandled component message %#x\n", msg_type);
  845. return;
  846. }
  847. if (tplg_ops->control->update)
  848. tplg_ops->control->update(sdev, msg_buf);
  849. }
  850. static void ipc3_trace_message(struct snd_sof_dev *sdev, void *msg_buf)
  851. {
  852. struct sof_ipc_cmd_hdr *hdr = msg_buf;
  853. u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
  854. switch (msg_type) {
  855. case SOF_IPC_TRACE_DMA_POSITION:
  856. ipc3_dtrace_posn_update(sdev, msg_buf);
  857. break;
  858. default:
  859. dev_err(sdev->dev, "unhandled trace message %#x\n", msg_type);
  860. break;
  861. }
  862. }
  863. void sof_ipc3_do_rx_work(struct snd_sof_dev *sdev, struct sof_ipc_cmd_hdr *hdr, void *msg_buf)
  864. {
  865. ipc3_rx_callback rx_callback = NULL;
  866. u32 cmd;
  867. int err;
  868. ipc3_log_header(sdev->dev, "ipc rx", hdr->cmd);
  869. if (hdr->size < sizeof(*hdr) || hdr->size > SOF_IPC_MSG_MAX_SIZE) {
  870. dev_err(sdev->dev, "The received message size is invalid: %u\n",
  871. hdr->size);
  872. return;
  873. }
  874. cmd = hdr->cmd & SOF_GLB_TYPE_MASK;
  875. /* check message type */
  876. switch (cmd) {
  877. case SOF_IPC_GLB_REPLY:
  878. dev_err(sdev->dev, "ipc reply unknown\n");
  879. break;
  880. case SOF_IPC_FW_READY:
  881. /* check for FW boot completion */
  882. if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
  883. err = ipc3_fw_ready(sdev, cmd);
  884. if (err < 0)
  885. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
  886. else
  887. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
  888. /* wake up firmware loader */
  889. wake_up(&sdev->boot_wait);
  890. }
  891. break;
  892. case SOF_IPC_GLB_COMPOUND:
  893. case SOF_IPC_GLB_TPLG_MSG:
  894. case SOF_IPC_GLB_PM_MSG:
  895. break;
  896. case SOF_IPC_GLB_COMP_MSG:
  897. rx_callback = ipc3_comp_notification;
  898. break;
  899. case SOF_IPC_GLB_STREAM_MSG:
  900. rx_callback = ipc3_stream_message;
  901. break;
  902. case SOF_IPC_GLB_TRACE_MSG:
  903. rx_callback = ipc3_trace_message;
  904. break;
  905. default:
  906. dev_err(sdev->dev, "%s: Unknown DSP message: 0x%x\n", __func__, cmd);
  907. break;
  908. }
  909. /* Call local handler for the message */
  910. if (rx_callback)
  911. rx_callback(sdev, msg_buf);
  912. /* Notify registered clients */
  913. sof_client_ipc_rx_dispatcher(sdev, msg_buf);
  914. ipc3_log_header(sdev->dev, "ipc rx done", hdr->cmd);
  915. }
  916. EXPORT_SYMBOL(sof_ipc3_do_rx_work);
  917. /* DSP firmware has sent host a message */
  918. static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev)
  919. {
  920. struct sof_ipc_cmd_hdr hdr;
  921. void *msg_buf;
  922. int err;
  923. /* read back header */
  924. err = snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr));
  925. if (err < 0) {
  926. dev_warn(sdev->dev, "failed to read IPC header: %d\n", err);
  927. return;
  928. }
  929. if (hdr.size < sizeof(hdr) || hdr.size > SOF_IPC_MSG_MAX_SIZE) {
  930. dev_err(sdev->dev, "The received message size is invalid\n");
  931. return;
  932. }
  933. /* read the full message */
  934. msg_buf = kmalloc(hdr.size, GFP_KERNEL);
  935. if (!msg_buf)
  936. return;
  937. err = snd_sof_ipc_msg_data(sdev, NULL, msg_buf, hdr.size);
  938. if (err < 0) {
  939. dev_err(sdev->dev, "%s: Failed to read message: %d\n", __func__, err);
  940. kfree(msg_buf);
  941. return;
  942. }
  943. sof_ipc3_do_rx_work(sdev, &hdr, msg_buf);
  944. kfree(msg_buf);
  945. }
  946. static int sof_ipc3_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
  947. {
  948. struct sof_ipc_pm_core_config core_cfg = {
  949. .hdr.size = sizeof(core_cfg),
  950. .hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
  951. };
  952. if (on)
  953. core_cfg.enable_mask = sdev->enabled_cores_mask | BIT(core_idx);
  954. else
  955. core_cfg.enable_mask = sdev->enabled_cores_mask & ~BIT(core_idx);
  956. return sof_ipc3_tx_msg(sdev, &core_cfg, sizeof(core_cfg), NULL, 0, false);
  957. }
  958. static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd)
  959. {
  960. struct sof_ipc_pm_ctx pm_ctx = {
  961. .hdr.size = sizeof(pm_ctx),
  962. .hdr.cmd = SOF_IPC_GLB_PM_MSG | cmd,
  963. };
  964. /* send ctx save ipc to dsp */
  965. return sof_ipc3_tx_msg(sdev, &pm_ctx, sizeof(pm_ctx), NULL, 0, false);
  966. }
  967. static int sof_ipc3_ctx_save(struct snd_sof_dev *sdev)
  968. {
  969. return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_SAVE);
  970. }
  971. static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev)
  972. {
  973. return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_RESTORE);
  974. }
  975. static int sof_ipc3_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
  976. {
  977. struct sof_ipc_pm_gate pm_gate;
  978. memset(&pm_gate, 0, sizeof(pm_gate));
  979. /* configure pm_gate ipc message */
  980. pm_gate.hdr.size = sizeof(pm_gate);
  981. pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
  982. pm_gate.flags = flags;
  983. /* send pm_gate ipc to dsp */
  984. return sof_ipc_tx_message_no_pm_no_reply(sdev->ipc, &pm_gate, sizeof(pm_gate));
  985. }
  986. static const struct sof_ipc_pm_ops ipc3_pm_ops = {
  987. .ctx_save = sof_ipc3_ctx_save,
  988. .ctx_restore = sof_ipc3_ctx_restore,
  989. .set_core_state = sof_ipc3_set_core_state,
  990. .set_pm_gate = sof_ipc3_set_pm_gate,
  991. };
  992. const struct sof_ipc_ops ipc3_ops = {
  993. .tplg = &ipc3_tplg_ops,
  994. .pm = &ipc3_pm_ops,
  995. .pcm = &ipc3_pcm_ops,
  996. .fw_loader = &ipc3_loader_ops,
  997. .fw_tracing = &ipc3_dtrace_ops,
  998. .tx_msg = sof_ipc3_tx_msg,
  999. .rx_msg = sof_ipc3_rx_msg,
  1000. .set_get_data = sof_ipc3_set_get_data,
  1001. .get_reply = sof_ipc3_get_reply,
  1002. };