ipc4.c 25 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. //
  3. // This file is provided under a dual BSD/GPLv2 license. When using or
  4. // redistributing this file, you may do so under either license.
  5. //
  6. // Copyright(c) 2022 Intel Corporation
  7. //
  8. // Authors: Rander Wang <rander.wang@linux.intel.com>
  9. // Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
  10. //
  11. #include <linux/firmware.h>
  12. #include <sound/sof/header.h>
  13. #include <sound/sof/ipc4/header.h>
  14. #include "sof-priv.h"
  15. #include "sof-audio.h"
  16. #include "ipc4-fw-reg.h"
  17. #include "ipc4-priv.h"
  18. #include "ipc4-telemetry.h"
  19. #include "ops.h"
  20. static const struct sof_ipc4_fw_status {
  21. int status;
  22. char *msg;
  23. } ipc4_status[] = {
  24. {0, "The operation was successful"},
  25. {1, "Invalid parameter specified"},
  26. {2, "Unknown message type specified"},
  27. {3, "Not enough space in the IPC reply buffer to complete the request"},
  28. {4, "The system or resource is busy"},
  29. {5, "Replaced ADSP IPC PENDING (unused)"},
  30. {6, "Unknown error while processing the request"},
  31. {7, "Unsupported operation requested"},
  32. {8, "Reserved (ADSP_STAGE_UNINITIALIZED removed)"},
  33. {9, "Specified resource not found"},
  34. {10, "A resource's ID requested to be created is already assigned"},
  35. {11, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"},
  36. {12, "Required resource is in invalid state"},
  37. {13, "Requested power transition failed to complete"},
  38. {14, "Manifest of the library being loaded is invalid"},
  39. {15, "Requested service or data is unavailable on the target platform"},
  40. {42, "Library target address is out of storage memory range"},
  41. {43, "Reserved"},
  42. {44, "Image verification by CSE failed"},
  43. {100, "General module management error"},
  44. {101, "Module loading failed"},
  45. {102, "Integrity check of the loaded module content failed"},
  46. {103, "Attempt to unload code of the module in use"},
  47. {104, "Other failure of module instance initialization request"},
  48. {105, "Reserved (ADSP_IPC_OUT_OF_MIPS removed)"},
  49. {106, "Reserved (ADSP_IPC_CONFIG_GET_ERROR removed)"},
  50. {107, "Reserved (ADSP_IPC_CONFIG_SET_ERROR removed)"},
  51. {108, "Reserved (ADSP_IPC_LARGE_CONFIG_GET_ERROR removed)"},
  52. {109, "Reserved (ADSP_IPC_LARGE_CONFIG_SET_ERROR removed)"},
  53. {110, "Invalid (out of range) module ID provided"},
  54. {111, "Invalid module instance ID provided"},
  55. {112, "Invalid queue (pin) ID provided"},
  56. {113, "Invalid destination queue (pin) ID provided"},
  57. {114, "Reserved (ADSP_IPC_BIND_UNBIND_DST_SINK_UNSUPPORTED removed)"},
  58. {115, "Reserved (ADSP_IPC_UNLOAD_INST_EXISTS removed)"},
  59. {116, "Invalid target code ID provided"},
  60. {117, "Injection DMA buffer is too small for probing the input pin"},
  61. {118, "Extraction DMA buffer is too small for probing the output pin"},
  62. {120, "Invalid ID of configuration item provided in TLV list"},
  63. {121, "Invalid length of configuration item provided in TLV list"},
  64. {122, "Invalid structure of configuration item provided"},
  65. {140, "Initialization of DMA Gateway failed"},
  66. {141, "Invalid ID of gateway provided"},
  67. {142, "Setting state of DMA Gateway failed"},
  68. {143, "DMA_CONTROL message targeting gateway not allocated yet"},
  69. {150, "Attempt to configure SCLK while I2S port is running"},
  70. {151, "Attempt to configure MCLK while I2S port is running"},
  71. {152, "Attempt to stop SCLK that is not running"},
  72. {153, "Attempt to stop MCLK that is not running"},
  73. {160, "Reserved (ADSP_IPC_PIPELINE_NOT_INITIALIZED removed)"},
  74. {161, "Reserved (ADSP_IPC_PIPELINE_NOT_EXIST removed)"},
  75. {162, "Reserved (ADSP_IPC_PIPELINE_SAVE_FAILED removed)"},
  76. {163, "Reserved (ADSP_IPC_PIPELINE_RESTORE_FAILED removed)"},
  77. {165, "Reserved (ADSP_IPC_PIPELINE_ALREADY_EXISTS removed)"},
  78. };
  79. typedef void (*ipc4_notification_handler)(struct snd_sof_dev *sdev,
  80. struct sof_ipc4_msg *msg);
  81. static int sof_ipc4_check_reply_status(struct snd_sof_dev *sdev, u32 status)
  82. {
  83. int i, ret;
  84. status &= SOF_IPC4_REPLY_STATUS;
  85. if (!status)
  86. return 0;
  87. for (i = 0; i < ARRAY_SIZE(ipc4_status); i++) {
  88. if (ipc4_status[i].status == status) {
  89. dev_err(sdev->dev, "FW reported error: %u - %s\n",
  90. status, ipc4_status[i].msg);
  91. goto to_errno;
  92. }
  93. }
  94. if (i == ARRAY_SIZE(ipc4_status))
  95. dev_err(sdev->dev, "FW reported error: %u - Unknown\n", status);
  96. to_errno:
  97. switch (status) {
  98. case 2:
  99. case 15:
  100. ret = -EOPNOTSUPP;
  101. break;
  102. case 8:
  103. case 11:
  104. case 105 ... 109:
  105. case 114 ... 115:
  106. case 160 ... 163:
  107. case 165:
  108. ret = -ENOENT;
  109. break;
  110. case 4:
  111. case 150:
  112. case 151:
  113. ret = -EBUSY;
  114. break;
  115. default:
  116. ret = -EINVAL;
  117. break;
  118. }
  119. return ret;
  120. }
  121. #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
  122. #define DBG_IPC4_MSG_TYPE_ENTRY(type) [SOF_IPC4_##type] = #type
  123. static const char * const ipc4_dbg_mod_msg_type[] = {
  124. DBG_IPC4_MSG_TYPE_ENTRY(MOD_INIT_INSTANCE),
  125. DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_GET),
  126. DBG_IPC4_MSG_TYPE_ENTRY(MOD_CONFIG_SET),
  127. DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_GET),
  128. DBG_IPC4_MSG_TYPE_ENTRY(MOD_LARGE_CONFIG_SET),
  129. DBG_IPC4_MSG_TYPE_ENTRY(MOD_BIND),
  130. DBG_IPC4_MSG_TYPE_ENTRY(MOD_UNBIND),
  131. DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_DX),
  132. DBG_IPC4_MSG_TYPE_ENTRY(MOD_SET_D0IX),
  133. DBG_IPC4_MSG_TYPE_ENTRY(MOD_ENTER_MODULE_RESTORE),
  134. DBG_IPC4_MSG_TYPE_ENTRY(MOD_EXIT_MODULE_RESTORE),
  135. DBG_IPC4_MSG_TYPE_ENTRY(MOD_DELETE_INSTANCE),
  136. };
  137. static const char * const ipc4_dbg_glb_msg_type[] = {
  138. DBG_IPC4_MSG_TYPE_ENTRY(GLB_BOOT_CONFIG),
  139. DBG_IPC4_MSG_TYPE_ENTRY(GLB_ROM_CONTROL),
  140. DBG_IPC4_MSG_TYPE_ENTRY(GLB_IPCGATEWAY_CMD),
  141. DBG_IPC4_MSG_TYPE_ENTRY(GLB_PERF_MEASUREMENTS_CMD),
  142. DBG_IPC4_MSG_TYPE_ENTRY(GLB_CHAIN_DMA),
  143. DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_MULTIPLE_MODULES),
  144. DBG_IPC4_MSG_TYPE_ENTRY(GLB_UNLOAD_MULTIPLE_MODULES),
  145. DBG_IPC4_MSG_TYPE_ENTRY(GLB_CREATE_PIPELINE),
  146. DBG_IPC4_MSG_TYPE_ENTRY(GLB_DELETE_PIPELINE),
  147. DBG_IPC4_MSG_TYPE_ENTRY(GLB_SET_PIPELINE_STATE),
  148. DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_STATE),
  149. DBG_IPC4_MSG_TYPE_ENTRY(GLB_GET_PIPELINE_CONTEXT_SIZE),
  150. DBG_IPC4_MSG_TYPE_ENTRY(GLB_SAVE_PIPELINE),
  151. DBG_IPC4_MSG_TYPE_ENTRY(GLB_RESTORE_PIPELINE),
  152. DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_LIBRARY),
  153. DBG_IPC4_MSG_TYPE_ENTRY(GLB_LOAD_LIBRARY_PREPARE),
  154. DBG_IPC4_MSG_TYPE_ENTRY(GLB_INTERNAL_MESSAGE),
  155. DBG_IPC4_MSG_TYPE_ENTRY(GLB_NOTIFICATION),
  156. };
  157. #define DBG_IPC4_NOTIFICATION_TYPE_ENTRY(type) [SOF_IPC4_NOTIFY_##type] = #type
  158. static const char * const ipc4_dbg_notification_type[] = {
  159. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PHRASE_DETECTED),
  160. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(RESOURCE_EVENT),
  161. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(LOG_BUFFER_STATUS),
  162. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(TIMESTAMP_CAPTURED),
  163. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_READY),
  164. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(FW_AUD_CLASS_RESULT),
  165. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(EXCEPTION_CAUGHT),
  166. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(MODULE_NOTIFICATION),
  167. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(PROBE_DATA_AVAILABLE),
  168. DBG_IPC4_NOTIFICATION_TYPE_ENTRY(ASYNC_MSG_SRVC_MESSAGE),
  169. };
  170. static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg,
  171. bool data_size_valid)
  172. {
  173. u32 val, type;
  174. const u8 *str2 = NULL;
  175. const u8 *str = NULL;
  176. val = msg->primary & SOF_IPC4_MSG_TARGET_MASK;
  177. type = SOF_IPC4_MSG_TYPE_GET(msg->primary);
  178. if (val == SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG)) {
  179. /* Module message */
  180. if (type < SOF_IPC4_MOD_TYPE_LAST)
  181. str = ipc4_dbg_mod_msg_type[type];
  182. if (!str)
  183. str = "Unknown Module message type";
  184. } else {
  185. /* Global FW message */
  186. if (type < SOF_IPC4_GLB_TYPE_LAST)
  187. str = ipc4_dbg_glb_msg_type[type];
  188. if (!str)
  189. str = "Unknown Global message type";
  190. if (type == SOF_IPC4_GLB_NOTIFICATION) {
  191. /* Notification message */
  192. u32 notif = SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary);
  193. /* Do not print log buffer notification if not desired */
  194. if (notif == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS &&
  195. !sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
  196. return;
  197. if (notif < SOF_IPC4_NOTIFY_TYPE_LAST)
  198. str2 = ipc4_dbg_notification_type[notif];
  199. if (!str2)
  200. str2 = "Unknown Global notification";
  201. }
  202. }
  203. if (str2) {
  204. if (data_size_valid && msg->data_size)
  205. dev_dbg(dev, "%s: %#x|%#x: %s|%s [data size: %zu]\n",
  206. text, msg->primary, msg->extension, str, str2,
  207. msg->data_size);
  208. else
  209. dev_dbg(dev, "%s: %#x|%#x: %s|%s\n", text, msg->primary,
  210. msg->extension, str, str2);
  211. } else {
  212. if (data_size_valid && msg->data_size)
  213. dev_dbg(dev, "%s: %#x|%#x: %s [data size: %zu]\n",
  214. text, msg->primary, msg->extension, str,
  215. msg->data_size);
  216. else
  217. dev_dbg(dev, "%s: %#x|%#x: %s\n", text, msg->primary,
  218. msg->extension, str);
  219. }
  220. }
  221. #else /* CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC */
  222. static void sof_ipc4_log_header(struct device *dev, u8 *text, struct sof_ipc4_msg *msg,
  223. bool data_size_valid)
  224. {
  225. /* Do not print log buffer notification if not desired */
  226. if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS) &&
  227. !SOF_IPC4_MSG_IS_MODULE_MSG(msg->primary) &&
  228. SOF_IPC4_MSG_TYPE_GET(msg->primary) == SOF_IPC4_GLB_NOTIFICATION &&
  229. SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary) == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS)
  230. return;
  231. if (data_size_valid && msg->data_size)
  232. dev_dbg(dev, "%s: %#x|%#x [data size: %zu]\n", text,
  233. msg->primary, msg->extension, msg->data_size);
  234. else
  235. dev_dbg(dev, "%s: %#x|%#x\n", text, msg->primary, msg->extension);
  236. }
  237. #endif
  238. static void sof_ipc4_dump_payload(struct snd_sof_dev *sdev,
  239. void *ipc_data, size_t size)
  240. {
  241. print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
  242. 16, 4, ipc_data, size, false);
  243. }
  244. static int sof_ipc4_get_reply(struct snd_sof_dev *sdev)
  245. {
  246. struct snd_sof_ipc_msg *msg = sdev->msg;
  247. struct sof_ipc4_msg *ipc4_reply;
  248. int ret;
  249. /* get the generic reply */
  250. ipc4_reply = msg->reply_data;
  251. sof_ipc4_log_header(sdev->dev, "ipc tx reply", ipc4_reply, false);
  252. ret = sof_ipc4_check_reply_status(sdev, ipc4_reply->primary);
  253. if (ret)
  254. return ret;
  255. /* No other information is expected for non large config get replies */
  256. if (!msg->reply_size || !SOF_IPC4_MSG_IS_MODULE_MSG(ipc4_reply->primary) ||
  257. (SOF_IPC4_MSG_TYPE_GET(ipc4_reply->primary) != SOF_IPC4_MOD_LARGE_CONFIG_GET))
  258. return 0;
  259. /* Read the requested payload */
  260. snd_sof_dsp_mailbox_read(sdev, sdev->dsp_box.offset, ipc4_reply->data_ptr,
  261. msg->reply_size);
  262. return 0;
  263. }
  264. /* wait for IPC message reply */
  265. static int ipc4_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
  266. {
  267. struct snd_sof_ipc_msg *msg = &ipc->msg;
  268. struct sof_ipc4_msg *ipc4_msg = msg->msg_data;
  269. struct snd_sof_dev *sdev = ipc->sdev;
  270. int ret;
  271. /* wait for DSP IPC completion */
  272. ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
  273. msecs_to_jiffies(sdev->ipc_timeout));
  274. if (ret == 0) {
  275. dev_err(sdev->dev, "ipc timed out for %#x|%#x\n",
  276. ipc4_msg->primary, ipc4_msg->extension);
  277. snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
  278. return -ETIMEDOUT;
  279. }
  280. if (msg->reply_error) {
  281. dev_err(sdev->dev, "ipc error for msg %#x|%#x\n",
  282. ipc4_msg->primary, ipc4_msg->extension);
  283. ret = msg->reply_error;
  284. } else {
  285. if (reply_data) {
  286. struct sof_ipc4_msg *ipc4_reply = msg->reply_data;
  287. struct sof_ipc4_msg *ipc4_reply_data = reply_data;
  288. /* Copy the header */
  289. ipc4_reply_data->header_u64 = ipc4_reply->header_u64;
  290. if (msg->reply_size && ipc4_reply_data->data_ptr) {
  291. /* copy the payload returned from DSP */
  292. memcpy(ipc4_reply_data->data_ptr, ipc4_reply->data_ptr,
  293. msg->reply_size);
  294. ipc4_reply_data->data_size = msg->reply_size;
  295. }
  296. }
  297. ret = 0;
  298. sof_ipc4_log_header(sdev->dev, "ipc tx done ", ipc4_msg, true);
  299. }
  300. /* re-enable dumps after successful IPC tx */
  301. if (sdev->ipc_dump_printed) {
  302. sdev->dbg_dump_printed = false;
  303. sdev->ipc_dump_printed = false;
  304. }
  305. return ret;
  306. }
  307. static int ipc4_tx_msg_unlocked(struct snd_sof_ipc *ipc,
  308. void *msg_data, size_t msg_bytes,
  309. void *reply_data, size_t reply_bytes)
  310. {
  311. struct sof_ipc4_msg *ipc4_msg = msg_data;
  312. struct snd_sof_dev *sdev = ipc->sdev;
  313. int ret;
  314. if (msg_bytes > ipc->max_payload_size || reply_bytes > ipc->max_payload_size)
  315. return -EINVAL;
  316. sof_ipc4_log_header(sdev->dev, "ipc tx ", msg_data, true);
  317. ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
  318. if (ret) {
  319. dev_err_ratelimited(sdev->dev,
  320. "%s: ipc message send for %#x|%#x failed: %d\n",
  321. __func__, ipc4_msg->primary, ipc4_msg->extension, ret);
  322. return ret;
  323. }
  324. /* now wait for completion */
  325. return ipc4_wait_tx_done(ipc, reply_data);
  326. }
  327. static int sof_ipc4_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
  328. void *reply_data, size_t reply_bytes, bool no_pm)
  329. {
  330. struct snd_sof_ipc *ipc = sdev->ipc;
  331. int ret;
  332. if (!msg_data)
  333. return -EINVAL;
  334. if (!no_pm) {
  335. const struct sof_dsp_power_state target_state = {
  336. .state = SOF_DSP_PM_D0,
  337. };
  338. /* ensure the DSP is in D0i0 before sending a new IPC */
  339. ret = snd_sof_dsp_set_power_state(sdev, &target_state);
  340. if (ret < 0)
  341. return ret;
  342. }
  343. /* Serialise IPC TX */
  344. mutex_lock(&ipc->tx_mutex);
  345. ret = ipc4_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
  346. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
  347. struct sof_ipc4_msg *msg = NULL;
  348. /* payload is indicated by non zero msg/reply_bytes */
  349. if (msg_bytes)
  350. msg = msg_data;
  351. else if (reply_bytes)
  352. msg = reply_data;
  353. if (msg)
  354. sof_ipc4_dump_payload(sdev, msg->data_ptr, msg->data_size);
  355. }
  356. mutex_unlock(&ipc->tx_mutex);
  357. return ret;
  358. }
  359. static int sof_ipc4_set_get_data(struct snd_sof_dev *sdev, void *data,
  360. size_t payload_bytes, bool set)
  361. {
  362. const struct sof_dsp_power_state target_state = {
  363. .state = SOF_DSP_PM_D0,
  364. };
  365. size_t payload_limit = sdev->ipc->max_payload_size;
  366. struct sof_ipc4_msg *ipc4_msg = data;
  367. struct sof_ipc4_msg tx = {{ 0 }};
  368. struct sof_ipc4_msg rx = {{ 0 }};
  369. size_t remaining = payload_bytes;
  370. size_t offset = 0;
  371. size_t chunk_size;
  372. int ret;
  373. if (!data)
  374. return -EINVAL;
  375. if ((ipc4_msg->primary & SOF_IPC4_MSG_TARGET_MASK) !=
  376. SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG))
  377. return -EINVAL;
  378. ipc4_msg->primary &= ~SOF_IPC4_MSG_TYPE_MASK;
  379. tx.primary = ipc4_msg->primary;
  380. tx.extension = ipc4_msg->extension;
  381. if (set)
  382. tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_SET);
  383. else
  384. tx.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_LARGE_CONFIG_GET);
  385. tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
  386. tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(payload_bytes);
  387. tx.extension |= SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(1);
  388. /* ensure the DSP is in D0i0 before sending IPC */
  389. ret = snd_sof_dsp_set_power_state(sdev, &target_state);
  390. if (ret < 0)
  391. return ret;
  392. /* Serialise IPC TX */
  393. mutex_lock(&sdev->ipc->tx_mutex);
  394. do {
  395. size_t tx_size, rx_size;
  396. if (remaining > payload_limit) {
  397. chunk_size = payload_limit;
  398. } else {
  399. chunk_size = remaining;
  400. if (set)
  401. tx.extension |= SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(1);
  402. }
  403. if (offset) {
  404. tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK;
  405. tx.extension &= ~SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
  406. tx.extension |= SOF_IPC4_MOD_EXT_MSG_SIZE(offset);
  407. }
  408. if (set) {
  409. tx.data_size = chunk_size;
  410. tx.data_ptr = ipc4_msg->data_ptr + offset;
  411. tx_size = chunk_size;
  412. rx_size = 0;
  413. } else {
  414. rx.primary = 0;
  415. rx.extension = 0;
  416. rx.data_size = chunk_size;
  417. rx.data_ptr = ipc4_msg->data_ptr + offset;
  418. tx_size = 0;
  419. rx_size = chunk_size;
  420. }
  421. /* Send the message for the current chunk */
  422. ret = ipc4_tx_msg_unlocked(sdev->ipc, &tx, tx_size, &rx, rx_size);
  423. if (ret < 0) {
  424. dev_err(sdev->dev,
  425. "%s: large config %s failed at offset %zu: %d\n",
  426. __func__, set ? "set" : "get", offset, ret);
  427. goto out;
  428. }
  429. if (!set && rx.extension & SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK) {
  430. /* Verify the firmware reported total payload size */
  431. rx_size = rx.extension & SOF_IPC4_MOD_EXT_MSG_SIZE_MASK;
  432. if (rx_size > payload_bytes) {
  433. dev_err(sdev->dev,
  434. "%s: Receive buffer (%zu) is too small for %zu\n",
  435. __func__, payload_bytes, rx_size);
  436. ret = -ENOMEM;
  437. goto out;
  438. }
  439. if (rx_size < chunk_size) {
  440. chunk_size = rx_size;
  441. remaining = rx_size;
  442. } else if (rx_size < payload_bytes) {
  443. remaining = rx_size;
  444. }
  445. }
  446. offset += chunk_size;
  447. remaining -= chunk_size;
  448. } while (remaining);
  449. /* Adjust the received data size if needed */
  450. if (!set && payload_bytes != offset)
  451. ipc4_msg->data_size = offset;
  452. out:
  453. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD))
  454. sof_ipc4_dump_payload(sdev, ipc4_msg->data_ptr, ipc4_msg->data_size);
  455. mutex_unlock(&sdev->ipc->tx_mutex);
  456. return ret;
  457. }
  458. static int sof_ipc4_init_msg_memory(struct snd_sof_dev *sdev)
  459. {
  460. struct sof_ipc4_msg *ipc4_msg;
  461. struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
  462. /* TODO: get max_payload_size from firmware */
  463. sdev->ipc->max_payload_size = SOF_IPC4_MSG_MAX_SIZE;
  464. /* Allocate memory for the ipc4 container and the maximum payload */
  465. msg->reply_data = devm_kzalloc(sdev->dev, sdev->ipc->max_payload_size +
  466. sizeof(struct sof_ipc4_msg), GFP_KERNEL);
  467. if (!msg->reply_data)
  468. return -ENOMEM;
  469. ipc4_msg = msg->reply_data;
  470. ipc4_msg->data_ptr = msg->reply_data + sizeof(struct sof_ipc4_msg);
  471. return 0;
  472. }
  473. size_t sof_ipc4_find_debug_slot_offset_by_type(struct snd_sof_dev *sdev,
  474. u32 slot_type)
  475. {
  476. size_t slot_desc_type_offset;
  477. u32 type;
  478. int i;
  479. /* The type is the second u32 in the slot descriptor */
  480. slot_desc_type_offset = sdev->debug_box.offset + sizeof(u32);
  481. for (i = 0; i < SOF_IPC4_MAX_DEBUG_SLOTS; i++) {
  482. sof_mailbox_read(sdev, slot_desc_type_offset, &type, sizeof(type));
  483. if (type == slot_type)
  484. return sdev->debug_box.offset + (i + 1) * SOF_IPC4_DEBUG_SLOT_SIZE;
  485. slot_desc_type_offset += SOF_IPC4_DEBUG_DESCRIPTOR_SIZE;
  486. }
  487. dev_dbg(sdev->dev, "Slot type %#x is not available in debug window\n", slot_type);
  488. return 0;
  489. }
  490. EXPORT_SYMBOL(sof_ipc4_find_debug_slot_offset_by_type);
  491. static int ipc4_fw_ready(struct snd_sof_dev *sdev, struct sof_ipc4_msg *ipc4_msg)
  492. {
  493. /* no need to re-check version/ABI for subsequent boots */
  494. if (!sdev->first_boot)
  495. return 0;
  496. sof_ipc4_create_exception_debugfs_node(sdev);
  497. return sof_ipc4_init_msg_memory(sdev);
  498. }
  499. static void sof_ipc4_module_notification_handler(struct snd_sof_dev *sdev,
  500. struct sof_ipc4_msg *ipc4_msg)
  501. {
  502. struct sof_ipc4_notify_module_data *data = ipc4_msg->data_ptr;
  503. /*
  504. * If the notification includes additional, module specific data, then
  505. * we need to re-allocate the buffer and re-read the whole payload,
  506. * including the event_data
  507. */
  508. if (data->event_data_size) {
  509. void *new;
  510. int ret;
  511. ipc4_msg->data_size += data->event_data_size;
  512. new = krealloc(ipc4_msg->data_ptr, ipc4_msg->data_size, GFP_KERNEL);
  513. if (!new) {
  514. ipc4_msg->data_size -= data->event_data_size;
  515. return;
  516. }
  517. /* re-read the whole payload */
  518. ipc4_msg->data_ptr = new;
  519. ret = snd_sof_ipc_msg_data(sdev, NULL, ipc4_msg->data_ptr,
  520. ipc4_msg->data_size);
  521. if (ret < 0) {
  522. dev_err(sdev->dev,
  523. "Failed to read the full module notification: %d\n",
  524. ret);
  525. return;
  526. }
  527. data = ipc4_msg->data_ptr;
  528. }
  529. /* Handle ALSA kcontrol notification */
  530. if ((data->event_id & SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_MASK) ==
  531. SOF_IPC4_NOTIFY_MODULE_EVENTID_ALSA_MAGIC_VAL) {
  532. const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg;
  533. if (tplg_ops->control->update)
  534. tplg_ops->control->update(sdev, ipc4_msg);
  535. }
  536. }
  537. static void sof_ipc4_rx_msg(struct snd_sof_dev *sdev)
  538. {
  539. struct sof_ipc4_msg *ipc4_msg = sdev->ipc->msg.rx_data;
  540. ipc4_notification_handler handler_func = NULL;
  541. size_t data_size = 0;
  542. int err;
  543. if (!ipc4_msg || !SOF_IPC4_MSG_IS_NOTIFICATION(ipc4_msg->primary))
  544. return;
  545. ipc4_msg->data_ptr = NULL;
  546. ipc4_msg->data_size = 0;
  547. sof_ipc4_log_header(sdev->dev, "ipc rx ", ipc4_msg, false);
  548. switch (SOF_IPC4_NOTIFICATION_TYPE_GET(ipc4_msg->primary)) {
  549. case SOF_IPC4_NOTIFY_FW_READY:
  550. /* check for FW boot completion */
  551. if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
  552. err = ipc4_fw_ready(sdev, ipc4_msg);
  553. if (err < 0)
  554. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
  555. else
  556. sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
  557. /* wake up firmware loader */
  558. wake_up(&sdev->boot_wait);
  559. }
  560. break;
  561. case SOF_IPC4_NOTIFY_RESOURCE_EVENT:
  562. data_size = sizeof(struct sof_ipc4_notify_resource_data);
  563. break;
  564. case SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS:
  565. sof_ipc4_mtrace_update_pos(sdev, SOF_IPC4_LOG_CORE_GET(ipc4_msg->primary));
  566. break;
  567. case SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT:
  568. snd_sof_dsp_panic(sdev, 0, true);
  569. break;
  570. case SOF_IPC4_NOTIFY_MODULE_NOTIFICATION:
  571. data_size = sizeof(struct sof_ipc4_notify_module_data);
  572. handler_func = sof_ipc4_module_notification_handler;
  573. break;
  574. default:
  575. dev_dbg(sdev->dev, "Unhandled DSP message: %#x|%#x\n",
  576. ipc4_msg->primary, ipc4_msg->extension);
  577. break;
  578. }
  579. if (data_size) {
  580. ipc4_msg->data_ptr = kmalloc(data_size, GFP_KERNEL);
  581. if (!ipc4_msg->data_ptr)
  582. return;
  583. ipc4_msg->data_size = data_size;
  584. err = snd_sof_ipc_msg_data(sdev, NULL, ipc4_msg->data_ptr, ipc4_msg->data_size);
  585. if (err < 0) {
  586. dev_err(sdev->dev, "failed to read IPC notification data: %d\n", err);
  587. kfree(ipc4_msg->data_ptr);
  588. ipc4_msg->data_ptr = NULL;
  589. ipc4_msg->data_size = 0;
  590. return;
  591. }
  592. }
  593. /* Handle notifications with payload */
  594. if (handler_func)
  595. handler_func(sdev, ipc4_msg);
  596. sof_ipc4_log_header(sdev->dev, "ipc rx done ", ipc4_msg, true);
  597. if (data_size) {
  598. if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD))
  599. sof_ipc4_dump_payload(sdev, ipc4_msg->data_ptr,
  600. ipc4_msg->data_size);
  601. kfree(ipc4_msg->data_ptr);
  602. ipc4_msg->data_ptr = NULL;
  603. ipc4_msg->data_size = 0;
  604. }
  605. }
  606. static int sof_ipc4_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
  607. {
  608. struct sof_ipc4_dx_state_info dx_state;
  609. struct sof_ipc4_msg msg;
  610. dx_state.core_mask = BIT(core_idx);
  611. if (on)
  612. dx_state.dx_mask = BIT(core_idx);
  613. else
  614. dx_state.dx_mask = 0;
  615. msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_DX);
  616. msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
  617. msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
  618. msg.extension = 0;
  619. msg.data_ptr = &dx_state;
  620. msg.data_size = sizeof(dx_state);
  621. return sof_ipc4_tx_msg(sdev, &msg, msg.data_size, NULL, 0, false);
  622. }
  623. /*
  624. * The context save callback is used to send a message to the firmware notifying
  625. * it that the primary core is going to be turned off, which is used as an
  626. * indication to prepare for a full power down, thus preparing for IMR boot
  627. * (when supported)
  628. *
  629. * Note: in IPC4 there is no message used to restore context, thus no context
  630. * restore callback is implemented
  631. */
  632. static int sof_ipc4_ctx_save(struct snd_sof_dev *sdev)
  633. {
  634. return sof_ipc4_set_core_state(sdev, SOF_DSP_PRIMARY_CORE, false);
  635. }
  636. static int sof_ipc4_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
  637. {
  638. struct sof_ipc4_msg msg = {{0}};
  639. msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_SET_D0IX);
  640. msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
  641. msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
  642. msg.extension = flags;
  643. return sof_ipc4_tx_msg(sdev, &msg, 0, NULL, 0, true);
  644. }
  645. static const struct sof_ipc_pm_ops ipc4_pm_ops = {
  646. .ctx_save = sof_ipc4_ctx_save,
  647. .set_core_state = sof_ipc4_set_core_state,
  648. .set_pm_gate = sof_ipc4_set_pm_gate,
  649. };
  650. static int sof_ipc4_init(struct snd_sof_dev *sdev)
  651. {
  652. struct sof_ipc4_fw_data *ipc4_data = sdev->private;
  653. int inbox_offset;
  654. mutex_init(&ipc4_data->pipeline_state_mutex);
  655. xa_init_flags(&ipc4_data->fw_lib_xa, XA_FLAGS_ALLOC);
  656. /* Set up the windows for IPC communication */
  657. inbox_offset = snd_sof_dsp_get_mailbox_offset(sdev);
  658. if (inbox_offset < 0) {
  659. dev_err(sdev->dev, "%s: No mailbox offset\n", __func__);
  660. return inbox_offset;
  661. }
  662. sdev->dsp_box.offset = inbox_offset;
  663. sdev->dsp_box.size = SOF_IPC4_MSG_MAX_SIZE;
  664. sdev->host_box.offset = snd_sof_dsp_get_window_offset(sdev,
  665. SOF_IPC4_OUTBOX_WINDOW_IDX);
  666. sdev->host_box.size = SOF_IPC4_MSG_MAX_SIZE;
  667. sdev->debug_box.offset = snd_sof_dsp_get_window_offset(sdev,
  668. SOF_IPC4_DEBUG_WINDOW_IDX);
  669. sdev->fw_info_box.offset = snd_sof_dsp_get_window_offset(sdev,
  670. SOF_IPC4_INBOX_WINDOW_IDX);
  671. sdev->fw_info_box.size = sizeof(struct sof_ipc4_fw_registers);
  672. dev_dbg(sdev->dev, "mailbox upstream %#x - size %#x\n",
  673. sdev->dsp_box.offset, SOF_IPC4_MSG_MAX_SIZE);
  674. dev_dbg(sdev->dev, "mailbox downstream %#x - size %#x\n",
  675. sdev->host_box.offset, SOF_IPC4_MSG_MAX_SIZE);
  676. dev_dbg(sdev->dev, "debug box %#x\n", sdev->debug_box.offset);
  677. return 0;
  678. }
  679. static void sof_ipc4_exit(struct snd_sof_dev *sdev)
  680. {
  681. struct sof_ipc4_fw_data *ipc4_data = sdev->private;
  682. struct sof_ipc4_fw_library *fw_lib;
  683. unsigned long lib_id;
  684. xa_for_each(&ipc4_data->fw_lib_xa, lib_id, fw_lib) {
  685. /*
  686. * The basefw (ID == 0) is handled by generic code, it is not
  687. * loaded by IPC4 code.
  688. */
  689. if (lib_id != 0)
  690. release_firmware(fw_lib->sof_fw.fw);
  691. fw_lib->sof_fw.fw = NULL;
  692. }
  693. xa_destroy(&ipc4_data->fw_lib_xa);
  694. }
  695. static int sof_ipc4_post_boot(struct snd_sof_dev *sdev)
  696. {
  697. if (sdev->first_boot)
  698. return sof_ipc4_query_fw_configuration(sdev);
  699. return sof_ipc4_reload_fw_libraries(sdev);
  700. }
  701. const struct sof_ipc_ops ipc4_ops = {
  702. .init = sof_ipc4_init,
  703. .exit = sof_ipc4_exit,
  704. .post_fw_boot = sof_ipc4_post_boot,
  705. .tx_msg = sof_ipc4_tx_msg,
  706. .rx_msg = sof_ipc4_rx_msg,
  707. .set_get_data = sof_ipc4_set_get_data,
  708. .get_reply = sof_ipc4_get_reply,
  709. .pm = &ipc4_pm_ops,
  710. .fw_loader = &ipc4_loader_ops,
  711. .tplg = &ipc4_tplg_ops,
  712. .pcm = &ipc4_pcm_ops,
  713. .fw_tracing = &ipc4_mtrace_ops,
  714. };