iommufd_utils.h 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES */
  3. #ifndef __SELFTEST_IOMMUFD_UTILS
  4. #define __SELFTEST_IOMMUFD_UTILS
  5. #include <unistd.h>
  6. #include <stddef.h>
  7. #include <sys/fcntl.h>
  8. #include <sys/ioctl.h>
  9. #include <stdint.h>
  10. #include <assert.h>
  11. #include "../kselftest_harness.h"
  12. #include "../../../../drivers/iommu/iommufd/iommufd_test.h"
  13. /* Hack to make assertions more readable */
  14. #define _IOMMU_TEST_CMD(x) IOMMU_TEST_CMD
  15. /* Imported from include/asm-generic/bitops/generic-non-atomic.h */
  16. #define BITS_PER_BYTE 8
  17. #define BITS_PER_LONG __BITS_PER_LONG
  18. #define BIT_MASK(nr) (1UL << ((nr) % __BITS_PER_LONG))
  19. #define BIT_WORD(nr) ((nr) / __BITS_PER_LONG)
  20. #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
  21. static inline void set_bit(unsigned int nr, unsigned long *addr)
  22. {
  23. unsigned long mask = BIT_MASK(nr);
  24. unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
  25. *p |= mask;
  26. }
  27. static inline bool test_bit(unsigned int nr, unsigned long *addr)
  28. {
  29. return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)));
  30. }
  31. static void *buffer;
  32. static unsigned long BUFFER_SIZE;
  33. static unsigned long PAGE_SIZE;
  34. #define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER))
  35. #define offsetofend(TYPE, MEMBER) \
  36. (offsetof(TYPE, MEMBER) + sizeof_field(TYPE, MEMBER))
  37. /*
  38. * Have the kernel check the refcount on pages. I don't know why a freshly
  39. * mmap'd anon non-compound page starts out with a ref of 3
  40. */
  41. #define check_refs(_ptr, _length, _refs) \
  42. ({ \
  43. struct iommu_test_cmd test_cmd = { \
  44. .size = sizeof(test_cmd), \
  45. .op = IOMMU_TEST_OP_MD_CHECK_REFS, \
  46. .check_refs = { .length = _length, \
  47. .uptr = (uintptr_t)(_ptr), \
  48. .refs = _refs }, \
  49. }; \
  50. ASSERT_EQ(0, \
  51. ioctl(self->fd, \
  52. _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_REFS), \
  53. &test_cmd)); \
  54. })
  55. static int _test_cmd_mock_domain(int fd, unsigned int ioas_id, __u32 *stdev_id,
  56. __u32 *hwpt_id, __u32 *idev_id)
  57. {
  58. struct iommu_test_cmd cmd = {
  59. .size = sizeof(cmd),
  60. .op = IOMMU_TEST_OP_MOCK_DOMAIN,
  61. .id = ioas_id,
  62. .mock_domain = {},
  63. };
  64. int ret;
  65. ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);
  66. if (ret)
  67. return ret;
  68. if (stdev_id)
  69. *stdev_id = cmd.mock_domain.out_stdev_id;
  70. assert(cmd.id != 0);
  71. if (hwpt_id)
  72. *hwpt_id = cmd.mock_domain.out_hwpt_id;
  73. if (idev_id)
  74. *idev_id = cmd.mock_domain.out_idev_id;
  75. return 0;
  76. }
  77. #define test_cmd_mock_domain(ioas_id, stdev_id, hwpt_id, idev_id) \
  78. ASSERT_EQ(0, _test_cmd_mock_domain(self->fd, ioas_id, stdev_id, \
  79. hwpt_id, idev_id))
  80. #define test_err_mock_domain(_errno, ioas_id, stdev_id, hwpt_id) \
  81. EXPECT_ERRNO(_errno, _test_cmd_mock_domain(self->fd, ioas_id, \
  82. stdev_id, hwpt_id, NULL))
  83. static int _test_cmd_mock_domain_flags(int fd, unsigned int ioas_id,
  84. __u32 stdev_flags, __u32 *stdev_id,
  85. __u32 *hwpt_id, __u32 *idev_id)
  86. {
  87. struct iommu_test_cmd cmd = {
  88. .size = sizeof(cmd),
  89. .op = IOMMU_TEST_OP_MOCK_DOMAIN_FLAGS,
  90. .id = ioas_id,
  91. .mock_domain_flags = { .dev_flags = stdev_flags },
  92. };
  93. int ret;
  94. ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);
  95. if (ret)
  96. return ret;
  97. if (stdev_id)
  98. *stdev_id = cmd.mock_domain_flags.out_stdev_id;
  99. assert(cmd.id != 0);
  100. if (hwpt_id)
  101. *hwpt_id = cmd.mock_domain_flags.out_hwpt_id;
  102. if (idev_id)
  103. *idev_id = cmd.mock_domain_flags.out_idev_id;
  104. return 0;
  105. }
  106. #define test_cmd_mock_domain_flags(ioas_id, flags, stdev_id, hwpt_id, idev_id) \
  107. ASSERT_EQ(0, _test_cmd_mock_domain_flags(self->fd, ioas_id, flags, \
  108. stdev_id, hwpt_id, idev_id))
  109. #define test_err_mock_domain_flags(_errno, ioas_id, flags, stdev_id, hwpt_id) \
  110. EXPECT_ERRNO(_errno, \
  111. _test_cmd_mock_domain_flags(self->fd, ioas_id, flags, \
  112. stdev_id, hwpt_id, NULL))
  113. static int _test_cmd_mock_domain_replace(int fd, __u32 stdev_id, __u32 pt_id,
  114. __u32 *hwpt_id)
  115. {
  116. struct iommu_test_cmd cmd = {
  117. .size = sizeof(cmd),
  118. .op = IOMMU_TEST_OP_MOCK_DOMAIN_REPLACE,
  119. .id = stdev_id,
  120. .mock_domain_replace = {
  121. .pt_id = pt_id,
  122. },
  123. };
  124. int ret;
  125. ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);
  126. if (ret)
  127. return ret;
  128. if (hwpt_id)
  129. *hwpt_id = cmd.mock_domain_replace.pt_id;
  130. return 0;
  131. }
  132. #define test_cmd_mock_domain_replace(stdev_id, pt_id) \
  133. ASSERT_EQ(0, _test_cmd_mock_domain_replace(self->fd, stdev_id, pt_id, \
  134. NULL))
  135. #define test_err_mock_domain_replace(_errno, stdev_id, pt_id) \
  136. EXPECT_ERRNO(_errno, _test_cmd_mock_domain_replace(self->fd, stdev_id, \
  137. pt_id, NULL))
  138. static int _test_cmd_hwpt_alloc(int fd, __u32 device_id, __u32 pt_id, __u32 ft_id,
  139. __u32 flags, __u32 *hwpt_id, __u32 data_type,
  140. void *data, size_t data_len)
  141. {
  142. struct iommu_hwpt_alloc cmd = {
  143. .size = sizeof(cmd),
  144. .flags = flags,
  145. .dev_id = device_id,
  146. .pt_id = pt_id,
  147. .data_type = data_type,
  148. .data_len = data_len,
  149. .data_uptr = (uint64_t)data,
  150. .fault_id = ft_id,
  151. };
  152. int ret;
  153. ret = ioctl(fd, IOMMU_HWPT_ALLOC, &cmd);
  154. if (ret)
  155. return ret;
  156. if (hwpt_id)
  157. *hwpt_id = cmd.out_hwpt_id;
  158. return 0;
  159. }
  160. #define test_cmd_hwpt_alloc(device_id, pt_id, flags, hwpt_id) \
  161. ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \
  162. hwpt_id, IOMMU_HWPT_DATA_NONE, NULL, \
  163. 0))
  164. #define test_err_hwpt_alloc(_errno, device_id, pt_id, flags, hwpt_id) \
  165. EXPECT_ERRNO(_errno, _test_cmd_hwpt_alloc( \
  166. self->fd, device_id, pt_id, 0, flags, \
  167. hwpt_id, IOMMU_HWPT_DATA_NONE, NULL, 0))
  168. #define test_cmd_hwpt_alloc_nested(device_id, pt_id, flags, hwpt_id, \
  169. data_type, data, data_len) \
  170. ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \
  171. hwpt_id, data_type, data, data_len))
  172. #define test_err_hwpt_alloc_nested(_errno, device_id, pt_id, flags, hwpt_id, \
  173. data_type, data, data_len) \
  174. EXPECT_ERRNO(_errno, \
  175. _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, 0, flags, \
  176. hwpt_id, data_type, data, data_len))
  177. #define test_cmd_hwpt_alloc_iopf(device_id, pt_id, fault_id, flags, hwpt_id, \
  178. data_type, data, data_len) \
  179. ASSERT_EQ(0, _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, fault_id, \
  180. flags, hwpt_id, data_type, data, \
  181. data_len))
  182. #define test_err_hwpt_alloc_iopf(_errno, device_id, pt_id, fault_id, flags, \
  183. hwpt_id, data_type, data, data_len) \
  184. EXPECT_ERRNO(_errno, \
  185. _test_cmd_hwpt_alloc(self->fd, device_id, pt_id, fault_id, \
  186. flags, hwpt_id, data_type, data, \
  187. data_len))
  188. #define test_cmd_hwpt_check_iotlb(hwpt_id, iotlb_id, expected) \
  189. ({ \
  190. struct iommu_test_cmd test_cmd = { \
  191. .size = sizeof(test_cmd), \
  192. .op = IOMMU_TEST_OP_MD_CHECK_IOTLB, \
  193. .id = hwpt_id, \
  194. .check_iotlb = { \
  195. .id = iotlb_id, \
  196. .iotlb = expected, \
  197. }, \
  198. }; \
  199. ASSERT_EQ(0, \
  200. ioctl(self->fd, \
  201. _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_IOTLB), \
  202. &test_cmd)); \
  203. })
  204. #define test_cmd_hwpt_check_iotlb_all(hwpt_id, expected) \
  205. ({ \
  206. int i; \
  207. for (i = 0; i < MOCK_NESTED_DOMAIN_IOTLB_NUM; i++) \
  208. test_cmd_hwpt_check_iotlb(hwpt_id, i, expected); \
  209. })
  210. static int _test_cmd_hwpt_invalidate(int fd, __u32 hwpt_id, void *reqs,
  211. uint32_t data_type, uint32_t lreq,
  212. uint32_t *nreqs)
  213. {
  214. struct iommu_hwpt_invalidate cmd = {
  215. .size = sizeof(cmd),
  216. .hwpt_id = hwpt_id,
  217. .data_type = data_type,
  218. .data_uptr = (uint64_t)reqs,
  219. .entry_len = lreq,
  220. .entry_num = *nreqs,
  221. };
  222. int rc = ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd);
  223. *nreqs = cmd.entry_num;
  224. return rc;
  225. }
  226. #define test_cmd_hwpt_invalidate(hwpt_id, reqs, data_type, lreq, nreqs) \
  227. ({ \
  228. ASSERT_EQ(0, \
  229. _test_cmd_hwpt_invalidate(self->fd, hwpt_id, reqs, \
  230. data_type, lreq, nreqs)); \
  231. })
  232. #define test_err_hwpt_invalidate(_errno, hwpt_id, reqs, data_type, lreq, \
  233. nreqs) \
  234. ({ \
  235. EXPECT_ERRNO(_errno, _test_cmd_hwpt_invalidate( \
  236. self->fd, hwpt_id, reqs, \
  237. data_type, lreq, nreqs)); \
  238. })
  239. static int _test_cmd_access_replace_ioas(int fd, __u32 access_id,
  240. unsigned int ioas_id)
  241. {
  242. struct iommu_test_cmd cmd = {
  243. .size = sizeof(cmd),
  244. .op = IOMMU_TEST_OP_ACCESS_REPLACE_IOAS,
  245. .id = access_id,
  246. .access_replace_ioas = { .ioas_id = ioas_id },
  247. };
  248. int ret;
  249. ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);
  250. if (ret)
  251. return ret;
  252. return 0;
  253. }
  254. #define test_cmd_access_replace_ioas(access_id, ioas_id) \
  255. ASSERT_EQ(0, _test_cmd_access_replace_ioas(self->fd, access_id, ioas_id))
  256. static int _test_cmd_set_dirty_tracking(int fd, __u32 hwpt_id, bool enabled)
  257. {
  258. struct iommu_hwpt_set_dirty_tracking cmd = {
  259. .size = sizeof(cmd),
  260. .flags = enabled ? IOMMU_HWPT_DIRTY_TRACKING_ENABLE : 0,
  261. .hwpt_id = hwpt_id,
  262. };
  263. int ret;
  264. ret = ioctl(fd, IOMMU_HWPT_SET_DIRTY_TRACKING, &cmd);
  265. if (ret)
  266. return -errno;
  267. return 0;
  268. }
  269. #define test_cmd_set_dirty_tracking(hwpt_id, enabled) \
  270. ASSERT_EQ(0, _test_cmd_set_dirty_tracking(self->fd, hwpt_id, enabled))
  271. static int _test_cmd_get_dirty_bitmap(int fd, __u32 hwpt_id, size_t length,
  272. __u64 iova, size_t page_size,
  273. __u64 *bitmap, __u32 flags)
  274. {
  275. struct iommu_hwpt_get_dirty_bitmap cmd = {
  276. .size = sizeof(cmd),
  277. .hwpt_id = hwpt_id,
  278. .flags = flags,
  279. .iova = iova,
  280. .length = length,
  281. .page_size = page_size,
  282. .data = (uintptr_t)bitmap,
  283. };
  284. int ret;
  285. ret = ioctl(fd, IOMMU_HWPT_GET_DIRTY_BITMAP, &cmd);
  286. if (ret)
  287. return ret;
  288. return 0;
  289. }
  290. #define test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, \
  291. bitmap, flags) \
  292. ASSERT_EQ(0, _test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, \
  293. page_size, bitmap, flags))
  294. static int _test_cmd_mock_domain_set_dirty(int fd, __u32 hwpt_id, size_t length,
  295. __u64 iova, size_t page_size,
  296. __u64 *bitmap, __u64 *dirty)
  297. {
  298. struct iommu_test_cmd cmd = {
  299. .size = sizeof(cmd),
  300. .op = IOMMU_TEST_OP_DIRTY,
  301. .id = hwpt_id,
  302. .dirty = {
  303. .iova = iova,
  304. .length = length,
  305. .page_size = page_size,
  306. .uptr = (uintptr_t)bitmap,
  307. }
  308. };
  309. int ret;
  310. ret = ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_DIRTY), &cmd);
  311. if (ret)
  312. return -ret;
  313. if (dirty)
  314. *dirty = cmd.dirty.out_nr_dirty;
  315. return 0;
  316. }
  317. #define test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, page_size, \
  318. bitmap, nr) \
  319. ASSERT_EQ(0, \
  320. _test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, \
  321. page_size, bitmap, nr))
  322. static int _test_mock_dirty_bitmaps(int fd, __u32 hwpt_id, size_t length,
  323. __u64 iova, size_t page_size,
  324. size_t pte_page_size, __u64 *bitmap,
  325. __u64 nbits, __u32 flags,
  326. struct __test_metadata *_metadata)
  327. {
  328. unsigned long npte = pte_page_size / page_size, pteset = 2 * npte;
  329. unsigned long j, i, nr = nbits / pteset ?: 1;
  330. unsigned long bitmap_size = DIV_ROUND_UP(nbits, BITS_PER_BYTE);
  331. __u64 out_dirty = 0;
  332. /* Mark all even bits as dirty in the mock domain */
  333. memset(bitmap, 0, bitmap_size);
  334. for (i = 0; i < nbits; i += pteset)
  335. set_bit(i, (unsigned long *)bitmap);
  336. test_cmd_mock_domain_set_dirty(fd, hwpt_id, length, iova, page_size,
  337. bitmap, &out_dirty);
  338. ASSERT_EQ(nr, out_dirty);
  339. /* Expect all even bits as dirty in the user bitmap */
  340. memset(bitmap, 0, bitmap_size);
  341. test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, bitmap,
  342. flags);
  343. /* Beware ASSERT_EQ() is two statements -- braces are not redundant! */
  344. for (i = 0; i < nbits; i += pteset) {
  345. for (j = 0; j < pteset; j++) {
  346. ASSERT_EQ(j < npte,
  347. test_bit(i + j, (unsigned long *)bitmap));
  348. }
  349. ASSERT_EQ(!(i % pteset), test_bit(i, (unsigned long *)bitmap));
  350. }
  351. memset(bitmap, 0, bitmap_size);
  352. test_cmd_get_dirty_bitmap(fd, hwpt_id, length, iova, page_size, bitmap,
  353. flags);
  354. /* It as read already -- expect all zeroes */
  355. for (i = 0; i < nbits; i += pteset) {
  356. for (j = 0; j < pteset; j++) {
  357. ASSERT_EQ(
  358. (j < npte) &&
  359. (flags &
  360. IOMMU_HWPT_GET_DIRTY_BITMAP_NO_CLEAR),
  361. test_bit(i + j, (unsigned long *)bitmap));
  362. }
  363. }
  364. return 0;
  365. }
  366. #define test_mock_dirty_bitmaps(hwpt_id, length, iova, page_size, pte_size,\
  367. bitmap, bitmap_size, flags, _metadata) \
  368. ASSERT_EQ(0, _test_mock_dirty_bitmaps(self->fd, hwpt_id, length, iova, \
  369. page_size, pte_size, bitmap, \
  370. bitmap_size, flags, _metadata))
  371. static int _test_cmd_create_access(int fd, unsigned int ioas_id,
  372. __u32 *access_id, unsigned int flags)
  373. {
  374. struct iommu_test_cmd cmd = {
  375. .size = sizeof(cmd),
  376. .op = IOMMU_TEST_OP_CREATE_ACCESS,
  377. .id = ioas_id,
  378. .create_access = { .flags = flags },
  379. };
  380. int ret;
  381. ret = ioctl(fd, IOMMU_TEST_CMD, &cmd);
  382. if (ret)
  383. return ret;
  384. *access_id = cmd.create_access.out_access_fd;
  385. return 0;
  386. }
  387. #define test_cmd_create_access(ioas_id, access_id, flags) \
  388. ASSERT_EQ(0, _test_cmd_create_access(self->fd, ioas_id, access_id, \
  389. flags))
  390. static int _test_cmd_destroy_access(unsigned int access_id)
  391. {
  392. return close(access_id);
  393. }
  394. #define test_cmd_destroy_access(access_id) \
  395. ASSERT_EQ(0, _test_cmd_destroy_access(access_id))
  396. static int _test_cmd_destroy_access_pages(int fd, unsigned int access_id,
  397. unsigned int access_pages_id)
  398. {
  399. struct iommu_test_cmd cmd = {
  400. .size = sizeof(cmd),
  401. .op = IOMMU_TEST_OP_DESTROY_ACCESS_PAGES,
  402. .id = access_id,
  403. .destroy_access_pages = { .access_pages_id = access_pages_id },
  404. };
  405. return ioctl(fd, IOMMU_TEST_CMD, &cmd);
  406. }
  407. #define test_cmd_destroy_access_pages(access_id, access_pages_id) \
  408. ASSERT_EQ(0, _test_cmd_destroy_access_pages(self->fd, access_id, \
  409. access_pages_id))
  410. #define test_err_destroy_access_pages(_errno, access_id, access_pages_id) \
  411. EXPECT_ERRNO(_errno, _test_cmd_destroy_access_pages( \
  412. self->fd, access_id, access_pages_id))
  413. static int _test_ioctl_destroy(int fd, unsigned int id)
  414. {
  415. struct iommu_destroy cmd = {
  416. .size = sizeof(cmd),
  417. .id = id,
  418. };
  419. return ioctl(fd, IOMMU_DESTROY, &cmd);
  420. }
  421. #define test_ioctl_destroy(id) ASSERT_EQ(0, _test_ioctl_destroy(self->fd, id))
  422. static int _test_ioctl_ioas_alloc(int fd, __u32 *id)
  423. {
  424. struct iommu_ioas_alloc cmd = {
  425. .size = sizeof(cmd),
  426. };
  427. int ret;
  428. ret = ioctl(fd, IOMMU_IOAS_ALLOC, &cmd);
  429. if (ret)
  430. return ret;
  431. *id = cmd.out_ioas_id;
  432. return 0;
  433. }
  434. #define test_ioctl_ioas_alloc(id) \
  435. ({ \
  436. ASSERT_EQ(0, _test_ioctl_ioas_alloc(self->fd, id)); \
  437. ASSERT_NE(0, *(id)); \
  438. })
  439. static int _test_ioctl_ioas_map(int fd, unsigned int ioas_id, void *buffer,
  440. size_t length, __u64 *iova, unsigned int flags)
  441. {
  442. struct iommu_ioas_map cmd = {
  443. .size = sizeof(cmd),
  444. .flags = flags,
  445. .ioas_id = ioas_id,
  446. .user_va = (uintptr_t)buffer,
  447. .length = length,
  448. };
  449. int ret;
  450. if (flags & IOMMU_IOAS_MAP_FIXED_IOVA)
  451. cmd.iova = *iova;
  452. ret = ioctl(fd, IOMMU_IOAS_MAP, &cmd);
  453. *iova = cmd.iova;
  454. return ret;
  455. }
  456. #define test_ioctl_ioas_map(buffer, length, iova_p) \
  457. ASSERT_EQ(0, _test_ioctl_ioas_map(self->fd, self->ioas_id, buffer, \
  458. length, iova_p, \
  459. IOMMU_IOAS_MAP_WRITEABLE | \
  460. IOMMU_IOAS_MAP_READABLE))
  461. #define test_err_ioctl_ioas_map(_errno, buffer, length, iova_p) \
  462. EXPECT_ERRNO(_errno, \
  463. _test_ioctl_ioas_map(self->fd, self->ioas_id, buffer, \
  464. length, iova_p, \
  465. IOMMU_IOAS_MAP_WRITEABLE | \
  466. IOMMU_IOAS_MAP_READABLE))
  467. #define test_ioctl_ioas_map_id(ioas_id, buffer, length, iova_p) \
  468. ASSERT_EQ(0, _test_ioctl_ioas_map(self->fd, ioas_id, buffer, length, \
  469. iova_p, \
  470. IOMMU_IOAS_MAP_WRITEABLE | \
  471. IOMMU_IOAS_MAP_READABLE))
  472. #define test_ioctl_ioas_map_fixed(buffer, length, iova) \
  473. ({ \
  474. __u64 __iova = iova; \
  475. ASSERT_EQ(0, _test_ioctl_ioas_map( \
  476. self->fd, self->ioas_id, buffer, length, \
  477. &__iova, \
  478. IOMMU_IOAS_MAP_FIXED_IOVA | \
  479. IOMMU_IOAS_MAP_WRITEABLE | \
  480. IOMMU_IOAS_MAP_READABLE)); \
  481. })
  482. #define test_ioctl_ioas_map_fixed_id(ioas_id, buffer, length, iova) \
  483. ({ \
  484. __u64 __iova = iova; \
  485. ASSERT_EQ(0, \
  486. _test_ioctl_ioas_map( \
  487. self->fd, ioas_id, buffer, length, &__iova, \
  488. IOMMU_IOAS_MAP_FIXED_IOVA | \
  489. IOMMU_IOAS_MAP_WRITEABLE | \
  490. IOMMU_IOAS_MAP_READABLE)); \
  491. })
  492. #define test_err_ioctl_ioas_map_fixed(_errno, buffer, length, iova) \
  493. ({ \
  494. __u64 __iova = iova; \
  495. EXPECT_ERRNO(_errno, \
  496. _test_ioctl_ioas_map( \
  497. self->fd, self->ioas_id, buffer, length, \
  498. &__iova, \
  499. IOMMU_IOAS_MAP_FIXED_IOVA | \
  500. IOMMU_IOAS_MAP_WRITEABLE | \
  501. IOMMU_IOAS_MAP_READABLE)); \
  502. })
  503. static int _test_ioctl_ioas_unmap(int fd, unsigned int ioas_id, uint64_t iova,
  504. size_t length, uint64_t *out_len)
  505. {
  506. struct iommu_ioas_unmap cmd = {
  507. .size = sizeof(cmd),
  508. .ioas_id = ioas_id,
  509. .iova = iova,
  510. .length = length,
  511. };
  512. int ret;
  513. ret = ioctl(fd, IOMMU_IOAS_UNMAP, &cmd);
  514. if (out_len)
  515. *out_len = cmd.length;
  516. return ret;
  517. }
  518. #define test_ioctl_ioas_unmap(iova, length) \
  519. ASSERT_EQ(0, _test_ioctl_ioas_unmap(self->fd, self->ioas_id, iova, \
  520. length, NULL))
  521. #define test_ioctl_ioas_unmap_id(ioas_id, iova, length) \
  522. ASSERT_EQ(0, _test_ioctl_ioas_unmap(self->fd, ioas_id, iova, length, \
  523. NULL))
  524. #define test_err_ioctl_ioas_unmap(_errno, iova, length) \
  525. EXPECT_ERRNO(_errno, _test_ioctl_ioas_unmap(self->fd, self->ioas_id, \
  526. iova, length, NULL))
  527. static int _test_ioctl_set_temp_memory_limit(int fd, unsigned int limit)
  528. {
  529. struct iommu_test_cmd memlimit_cmd = {
  530. .size = sizeof(memlimit_cmd),
  531. .op = IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT,
  532. .memory_limit = { .limit = limit },
  533. };
  534. return ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_SET_TEMP_MEMORY_LIMIT),
  535. &memlimit_cmd);
  536. }
  537. #define test_ioctl_set_temp_memory_limit(limit) \
  538. ASSERT_EQ(0, _test_ioctl_set_temp_memory_limit(self->fd, limit))
  539. #define test_ioctl_set_default_memory_limit() \
  540. test_ioctl_set_temp_memory_limit(65536)
  541. static void teardown_iommufd(int fd, struct __test_metadata *_metadata)
  542. {
  543. struct iommu_test_cmd test_cmd = {
  544. .size = sizeof(test_cmd),
  545. .op = IOMMU_TEST_OP_MD_CHECK_REFS,
  546. .check_refs = { .length = BUFFER_SIZE,
  547. .uptr = (uintptr_t)buffer },
  548. };
  549. if (fd == -1)
  550. return;
  551. EXPECT_EQ(0, close(fd));
  552. fd = open("/dev/iommu", O_RDWR);
  553. EXPECT_NE(-1, fd);
  554. EXPECT_EQ(0, ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_MD_CHECK_REFS),
  555. &test_cmd));
  556. EXPECT_EQ(0, close(fd));
  557. }
  558. #define EXPECT_ERRNO(expected_errno, cmd) \
  559. ({ \
  560. ASSERT_EQ(-1, cmd); \
  561. EXPECT_EQ(expected_errno, errno); \
  562. })
  563. #endif
  564. /* @data can be NULL */
  565. static int _test_cmd_get_hw_info(int fd, __u32 device_id, void *data,
  566. size_t data_len, uint32_t *capabilities)
  567. {
  568. struct iommu_test_hw_info *info = (struct iommu_test_hw_info *)data;
  569. struct iommu_hw_info cmd = {
  570. .size = sizeof(cmd),
  571. .dev_id = device_id,
  572. .data_len = data_len,
  573. .data_uptr = (uint64_t)data,
  574. .out_capabilities = 0,
  575. };
  576. int ret;
  577. ret = ioctl(fd, IOMMU_GET_HW_INFO, &cmd);
  578. if (ret)
  579. return ret;
  580. assert(cmd.out_data_type == IOMMU_HW_INFO_TYPE_SELFTEST);
  581. /*
  582. * The struct iommu_test_hw_info should be the one defined
  583. * by the current kernel.
  584. */
  585. assert(cmd.data_len == sizeof(struct iommu_test_hw_info));
  586. /*
  587. * Trailing bytes should be 0 if user buffer is larger than
  588. * the data that kernel reports.
  589. */
  590. if (data_len > cmd.data_len) {
  591. char *ptr = (char *)(data + cmd.data_len);
  592. int idx = 0;
  593. while (idx < data_len - cmd.data_len) {
  594. assert(!*(ptr + idx));
  595. idx++;
  596. }
  597. }
  598. if (info) {
  599. if (data_len >= offsetofend(struct iommu_test_hw_info, test_reg))
  600. assert(info->test_reg == IOMMU_HW_INFO_SELFTEST_REGVAL);
  601. if (data_len >= offsetofend(struct iommu_test_hw_info, flags))
  602. assert(!info->flags);
  603. }
  604. if (capabilities)
  605. *capabilities = cmd.out_capabilities;
  606. return 0;
  607. }
  608. #define test_cmd_get_hw_info(device_id, data, data_len) \
  609. ASSERT_EQ(0, _test_cmd_get_hw_info(self->fd, device_id, data, \
  610. data_len, NULL))
  611. #define test_err_get_hw_info(_errno, device_id, data, data_len) \
  612. EXPECT_ERRNO(_errno, _test_cmd_get_hw_info(self->fd, device_id, data, \
  613. data_len, NULL))
  614. #define test_cmd_get_hw_capabilities(device_id, caps, mask) \
  615. ASSERT_EQ(0, _test_cmd_get_hw_info(self->fd, device_id, NULL, 0, &caps))
  616. static int _test_ioctl_fault_alloc(int fd, __u32 *fault_id, __u32 *fault_fd)
  617. {
  618. struct iommu_fault_alloc cmd = {
  619. .size = sizeof(cmd),
  620. };
  621. int ret;
  622. ret = ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd);
  623. if (ret)
  624. return ret;
  625. *fault_id = cmd.out_fault_id;
  626. *fault_fd = cmd.out_fault_fd;
  627. return 0;
  628. }
  629. #define test_ioctl_fault_alloc(fault_id, fault_fd) \
  630. ({ \
  631. ASSERT_EQ(0, _test_ioctl_fault_alloc(self->fd, fault_id, \
  632. fault_fd)); \
  633. ASSERT_NE(0, *(fault_id)); \
  634. ASSERT_NE(0, *(fault_fd)); \
  635. })
  636. static int _test_cmd_trigger_iopf(int fd, __u32 device_id, __u32 fault_fd)
  637. {
  638. struct iommu_test_cmd trigger_iopf_cmd = {
  639. .size = sizeof(trigger_iopf_cmd),
  640. .op = IOMMU_TEST_OP_TRIGGER_IOPF,
  641. .trigger_iopf = {
  642. .dev_id = device_id,
  643. .pasid = 0x1,
  644. .grpid = 0x2,
  645. .perm = IOMMU_PGFAULT_PERM_READ | IOMMU_PGFAULT_PERM_WRITE,
  646. .addr = 0xdeadbeaf,
  647. },
  648. };
  649. struct iommu_hwpt_page_response response = {
  650. .code = IOMMUFD_PAGE_RESP_SUCCESS,
  651. };
  652. struct iommu_hwpt_pgfault fault = {};
  653. ssize_t bytes;
  654. int ret;
  655. ret = ioctl(fd, _IOMMU_TEST_CMD(IOMMU_TEST_OP_TRIGGER_IOPF), &trigger_iopf_cmd);
  656. if (ret)
  657. return ret;
  658. bytes = read(fault_fd, &fault, sizeof(fault));
  659. if (bytes <= 0)
  660. return -EIO;
  661. response.cookie = fault.cookie;
  662. bytes = write(fault_fd, &response, sizeof(response));
  663. if (bytes <= 0)
  664. return -EIO;
  665. return 0;
  666. }
  667. #define test_cmd_trigger_iopf(device_id, fault_fd) \
  668. ASSERT_EQ(0, _test_cmd_trigger_iopf(self->fd, device_id, fault_fd))