clk_fixed_factor.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Author: Anup Patel <anup.patel@wdc.com>
  6. */
  7. #define LOG_CATEGORY UCLASS_CLK
  8. #include <common.h>
  9. #include <clk-uclass.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <linux/err.h>
  14. struct clk_fixed_factor {
  15. struct clk parent;
  16. unsigned int div;
  17. unsigned int mult;
  18. };
  19. #define to_clk_fixed_factor(dev) \
  20. ((struct clk_fixed_factor *)dev_get_plat(dev))
  21. static ulong clk_fixed_factor_get_rate(struct clk *clk)
  22. {
  23. uint64_t rate;
  24. struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
  25. rate = clk_get_rate(&ff->parent);
  26. if (IS_ERR_VALUE(rate))
  27. return rate;
  28. do_div(rate, ff->div);
  29. return rate * ff->mult;
  30. }
  31. const struct clk_ops clk_fixed_factor_ops = {
  32. .get_rate = clk_fixed_factor_get_rate,
  33. };
  34. static int clk_fixed_factor_of_to_plat(struct udevice *dev)
  35. {
  36. if (CONFIG_IS_ENABLED(OF_REAL)) {
  37. int err;
  38. struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
  39. err = clk_get_by_index(dev, 0, &ff->parent);
  40. if (err)
  41. return err;
  42. ff->div = dev_read_u32_default(dev, "clock-div", 1);
  43. ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
  44. }
  45. return 0;
  46. }
  47. static const struct udevice_id clk_fixed_factor_match[] = {
  48. {
  49. .compatible = "fixed-factor-clock",
  50. },
  51. { /* sentinel */ }
  52. };
  53. U_BOOT_DRIVER(clk_fixed_factor) = {
  54. .name = "fixed_factor_clock",
  55. .id = UCLASS_CLK,
  56. .of_match = clk_fixed_factor_match,
  57. .of_to_plat = clk_fixed_factor_of_to_plat,
  58. .plat_auto = sizeof(struct clk_fixed_factor),
  59. .ops = &clk_fixed_factor_ops,
  60. };