Kconfig 5.0 KB

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  1. menu "FPGA support"
  2. config FPGA
  3. bool
  4. config FPGA_ALTERA
  5. bool "Enable Altera FPGA drivers"
  6. select FPGA
  7. help
  8. Say Y here to enable the Altera FPGA driver
  9. This provides basic infrastructure to support Altera FPGA devices.
  10. Enable Altera FPGA specific functions which includes bitstream
  11. (in BIT format), fpga and device validation.
  12. config FPGA_SOCFPGA
  13. bool "Enable Gen5 and Arria10 common FPGA drivers"
  14. select FPGA_ALTERA
  15. help
  16. Say Y here to enable the Gen5 and Arria10 common FPGA driver
  17. This provides common functionality for Gen5 and Arria10 devices.
  18. config FPGA_STRATIX_II
  19. bool "Enable Stratix II FPGA drivers"
  20. depends on FPGA_ALTERA
  21. help
  22. Say Y here to enable the Altera Stratix II FPGA-specific driver.
  23. config FPGA_STRATIX_V
  24. bool "Enable Stratix V FPGA drivers"
  25. depends on FPGA_ALTERA
  26. help
  27. Say Y here to enable the Altera Stratix V FPGA specific driver.
  28. config FPGA_ACEX1K
  29. bool "Enable Altera ACEX 1K driver"
  30. depends on FPGA_ALTERA
  31. help
  32. Say Y here to enable the Altera ACEX 1K FPGA specific driver.
  33. config FPGA_CYCLON2
  34. bool "Enable Altera FPGA driver for Cyclone II"
  35. depends on FPGA_ALTERA
  36. help
  37. Say Y here to enable the Altera Cyclone II FPGA specific driver
  38. This provides common functionality for Altera Cyclone II devices.
  39. Enable FPGA driver for loading bitstream in BIT and BIN format
  40. on Altera Cyclone II device.
  41. config FPGA_INTEL_SDM_MAILBOX
  42. bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
  43. depends on TARGET_SOCFPGA_SOC64
  44. select FPGA_ALTERA
  45. help
  46. Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
  47. This provides common functionality for Intel FPGA devices.
  48. Enable FPGA driver for writing full bitstream into Intel FPGA
  49. devices through SDM (Secure Device Manager) Mailbox.
  50. config FPGA_LATTICE
  51. bool "Enable Lattice FPGA driver"
  52. help
  53. This is used for the lattice FPGAs. Please check the source code as
  54. there is no documentation for this at present.
  55. config FPGA_XILINX
  56. bool "Enable Xilinx FPGA drivers"
  57. select FPGA
  58. help
  59. Enable Xilinx FPGA specific functions which includes bitstream
  60. (in BIT format), fpga and device validation.
  61. config FPGA_ZYNQMPPL
  62. bool "Enable Xilinx FPGA driver for ZynqMP"
  63. depends on FPGA_XILINX && ZYNQMP_FIRMWARE
  64. help
  65. Enable FPGA driver for loading bitstream in BIT and BIN format
  66. on Xilinx Zynq UltraScale+ (ZynqMP) device.
  67. config FPGA_VERSALPL
  68. bool "Enable Xilinx FPGA driver for Versal"
  69. depends on FPGA_XILINX
  70. help
  71. Enable FPGA driver for loading bitstream in PDI format on Xilinx
  72. Versal device. PDI is a new programmable device image format for
  73. Versal. The bitstream will only be generated as PDI for Versal
  74. platform.
  75. config FPGA_SPARTAN2
  76. bool "Enable Spartan2 FPGA driver"
  77. depends on FPGA_XILINX
  78. help
  79. Enable Spartan2 FPGA driver.
  80. config FPGA_SPARTAN3
  81. bool "Enable Spartan3 FPGA driver"
  82. depends on FPGA_XILINX
  83. help
  84. Enable Spartan3 FPGA driver for loading in BIT format.
  85. config FPGA_VIRTEX2
  86. bool "Enable Xilinx Virtex-II and later FPGA driver"
  87. depends on FPGA_XILINX
  88. help
  89. Enable Virtex-II FPGA driver for loading in BIT format. This driver
  90. also supports many newer Xilinx FPGA families.
  91. config SYS_FPGA_CHECK_BUSY
  92. bool "Perform busy check during load from FPGA"
  93. depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2
  94. config FPGA_ZYNQPL
  95. bool "Enable Xilinx FPGA for Zynq"
  96. depends on ARCH_ZYNQ
  97. help
  98. Enable FPGA driver for loading bitstream in BIT and BIN format
  99. on Xilinx Zynq devices.
  100. config SYS_FPGA_CHECK_CTRLC
  101. bool "Allow Control-C to interrupt FPGA configuration"
  102. depends on FPGA
  103. help
  104. User can interrupt FPGA configuration by pressing CTRL+C.
  105. config SYS_FPGA_PROG_FEEDBACK
  106. bool "Progress output during FPGA configuration"
  107. depends on FPGA
  108. default y if FPGA_VIRTEX2
  109. help
  110. Enable printing of hash marks during FPGA configuration.
  111. config FPGA_LOAD_SECURE
  112. bool "Enable loading secure bitstreams"
  113. depends on FPGA
  114. help
  115. Enables the fpga loads() functions that are used to load secure
  116. (authenticated or encrypted or both) bitstreams on to FPGA.
  117. config SPL_FPGA_LOAD_SECURE
  118. bool "Enable loading secure bitstreams for SPL"
  119. depends on SPL_FPGA
  120. help
  121. Enables the fpga loads() functions that are used to load secure
  122. (authenticated or encrypted or both) bitstreams on to FPGA.
  123. config DM_FPGA
  124. bool "Enable Driver Model for FPGA drivers"
  125. depends on DM
  126. select FPGA
  127. help
  128. Enable driver model for Field-Programmable Gate Array (FPGA) devices.
  129. The devices cover a wide range of applications and are configured at
  130. runtime by loading a bitstream into the FPGA device.
  131. Loading a bitstream from any kind of storage is the main task of the
  132. FPGA drivers.
  133. For now this uclass has no methods yet.
  134. config SANDBOX_FPGA
  135. bool "Enable sandbox FPGA driver"
  136. depends on SANDBOX && DM_FPGA
  137. help
  138. This is a driver model based FPGA driver for sandbox.
  139. Currently it is a stub only, as there are no usable uclass methods yet.
  140. config MAX_FPGA_DEVICES
  141. int "Maximum number of FPGA devices"
  142. depends on FPGA
  143. default 5
  144. endmenu