ds1307.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001, 2002, 2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. * Keith Outwater, keith_outwater@mvis.com`
  6. * Steven Scholz, steven.scholz@imc-berlin.de
  7. */
  8. /*
  9. * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
  10. * DS1307 and DS1338/9 Real Time Clock (RTC).
  11. *
  12. * based on ds1337.c
  13. */
  14. #include <common.h>
  15. #include <command.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <rtc.h>
  19. #include <i2c.h>
  20. enum ds_type {
  21. ds_1307,
  22. ds_1337,
  23. ds_1339,
  24. ds_1340,
  25. m41t11,
  26. mcp794xx,
  27. };
  28. /*
  29. * RTC register addresses
  30. */
  31. #define RTC_SEC_REG_ADDR 0x00
  32. #define RTC_MIN_REG_ADDR 0x01
  33. #define RTC_HR_REG_ADDR 0x02
  34. #define RTC_DAY_REG_ADDR 0x03
  35. #define RTC_DATE_REG_ADDR 0x04
  36. #define RTC_MON_REG_ADDR 0x05
  37. #define RTC_YR_REG_ADDR 0x06
  38. #define RTC_CTL_REG_ADDR 0x07
  39. #define DS1337_CTL_REG_ADDR 0x0e
  40. #define DS1337_STAT_REG_ADDR 0x0f
  41. #define DS1340_STAT_REG_ADDR 0x09
  42. #define RTC_STAT_BIT_OSF 0x80
  43. #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
  44. /* DS1307-specific bits */
  45. #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
  46. #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
  47. #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
  48. #define RTC_CTL_BIT_OUT 0x80 /* Output Control */
  49. /* DS1337-specific bits */
  50. #define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */
  51. #define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */
  52. #define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */
  53. /* DS1340-specific bits */
  54. #define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */
  55. #define DS1340_CTL_BIT_OUT 0x80 /* Output Control */
  56. /* MCP7941X-specific bits */
  57. #define MCP7941X_BIT_ST 0x80
  58. #define MCP7941X_BIT_VBATEN 0x08
  59. #ifndef CONFIG_DM_RTC
  60. /*---------------------------------------------------------------------*/
  61. #undef DEBUG_RTC
  62. #ifdef DEBUG_RTC
  63. #define DEBUGR(fmt, args...) printf(fmt, ##args)
  64. #else
  65. #define DEBUGR(fmt, args...)
  66. #endif
  67. /*---------------------------------------------------------------------*/
  68. #ifndef CFG_SYS_I2C_RTC_ADDR
  69. # define CFG_SYS_I2C_RTC_ADDR 0x68
  70. #endif
  71. #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
  72. # error The DS1307 is specified only up to 100kHz!
  73. #endif
  74. static uchar rtc_read (uchar reg);
  75. static void rtc_write (uchar reg, uchar val);
  76. /*
  77. * Get the current time from the RTC
  78. */
  79. int rtc_get (struct rtc_time *tmp)
  80. {
  81. int rel = 0;
  82. uchar sec, min, hour, mday, wday, mon, year;
  83. #ifdef CONFIG_RTC_MCP79411
  84. read_rtc:
  85. #endif
  86. sec = rtc_read (RTC_SEC_REG_ADDR);
  87. min = rtc_read (RTC_MIN_REG_ADDR);
  88. hour = rtc_read (RTC_HR_REG_ADDR);
  89. wday = rtc_read (RTC_DAY_REG_ADDR);
  90. mday = rtc_read (RTC_DATE_REG_ADDR);
  91. mon = rtc_read (RTC_MON_REG_ADDR);
  92. year = rtc_read (RTC_YR_REG_ADDR);
  93. DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
  94. "hr: %02x min: %02x sec: %02x\n",
  95. year, mon, mday, wday, hour, min, sec);
  96. #ifdef CONFIG_RTC_DS1307
  97. if (sec & RTC_SEC_BIT_CH) {
  98. printf ("### Warning: RTC oscillator has stopped\n");
  99. /* clear the CH flag */
  100. rtc_write (RTC_SEC_REG_ADDR,
  101. rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
  102. rel = -1;
  103. }
  104. #endif
  105. #ifdef CONFIG_RTC_MCP79411
  106. /* make sure that the backup battery is enabled */
  107. if (!(wday & MCP7941X_BIT_VBATEN)) {
  108. rtc_write(RTC_DAY_REG_ADDR,
  109. wday | MCP7941X_BIT_VBATEN);
  110. }
  111. /* clock halted? turn it on, so clock can tick. */
  112. if (!(sec & MCP7941X_BIT_ST)) {
  113. rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST);
  114. printf("Started RTC\n");
  115. goto read_rtc;
  116. }
  117. #endif
  118. tmp->tm_sec = bcd2bin (sec & 0x7F);
  119. tmp->tm_min = bcd2bin (min & 0x7F);
  120. tmp->tm_hour = bcd2bin (hour & 0x3F);
  121. tmp->tm_mday = bcd2bin (mday & 0x3F);
  122. tmp->tm_mon = bcd2bin (mon & 0x1F);
  123. tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
  124. tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
  125. tmp->tm_yday = 0;
  126. tmp->tm_isdst= 0;
  127. DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  128. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  129. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  130. return rel;
  131. }
  132. /*
  133. * Set the RTC
  134. */
  135. int rtc_set (struct rtc_time *tmp)
  136. {
  137. DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  138. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  139. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  140. if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
  141. printf("WARNING: year should be between 1970 and 2069!\n");
  142. rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
  143. rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
  144. #ifdef CONFIG_RTC_MCP79411
  145. rtc_write (RTC_DAY_REG_ADDR,
  146. bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN);
  147. #else
  148. rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
  149. #endif
  150. rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
  151. rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
  152. rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
  153. #ifdef CONFIG_RTC_MCP79411
  154. rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST);
  155. #else
  156. rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
  157. #endif
  158. return 0;
  159. }
  160. /*
  161. * Reset the RTC. We setting the date back to 1970-01-01.
  162. * We also enable the oscillator output on the SQW/OUT pin and program
  163. * it for 32,768 Hz output. Note that according to the datasheet, turning
  164. * on the square wave output increases the current drain on the backup
  165. * battery to something between 480nA and 800nA.
  166. */
  167. void rtc_reset (void)
  168. {
  169. rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
  170. rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
  171. }
  172. /*
  173. * Helper functions
  174. */
  175. static
  176. uchar rtc_read (uchar reg)
  177. {
  178. return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg));
  179. }
  180. static void rtc_write (uchar reg, uchar val)
  181. {
  182. i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val);
  183. }
  184. #endif /* !CONFIG_DM_RTC */
  185. #ifdef CONFIG_DM_RTC
  186. static int ds1307_rtc_set(struct udevice *dev, const struct rtc_time *tm)
  187. {
  188. int ret;
  189. uchar buf[7];
  190. enum ds_type type = dev_get_driver_data(dev);
  191. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  192. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  193. tm->tm_hour, tm->tm_min, tm->tm_sec);
  194. if (tm->tm_year < 1970 || tm->tm_year > 2069)
  195. printf("WARNING: year should be between 1970 and 2069!\n");
  196. buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
  197. buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
  198. buf[RTC_DAY_REG_ADDR] = bin2bcd(tm->tm_wday + 1);
  199. buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
  200. buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
  201. buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
  202. buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
  203. if (type == mcp794xx) {
  204. buf[RTC_DAY_REG_ADDR] |= MCP7941X_BIT_VBATEN;
  205. buf[RTC_SEC_REG_ADDR] |= MCP7941X_BIT_ST;
  206. }
  207. ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
  208. if (ret < 0)
  209. return ret;
  210. if (type == ds_1337) {
  211. /* Ensure oscillator is enabled */
  212. dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR, 0);
  213. }
  214. return 0;
  215. }
  216. static int ds1307_rtc_get(struct udevice *dev, struct rtc_time *tm)
  217. {
  218. int ret;
  219. uchar buf[7];
  220. enum ds_type type = dev_get_driver_data(dev);
  221. ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
  222. if (ret < 0)
  223. return ret;
  224. if (type == ds_1337 || type == ds_1340) {
  225. uint reg = (type == ds_1337) ? DS1337_STAT_REG_ADDR :
  226. DS1340_STAT_REG_ADDR;
  227. int status = dm_i2c_reg_read(dev, reg);
  228. if (status >= 0 && (status & RTC_STAT_BIT_OSF)) {
  229. printf("### Warning: RTC oscillator has stopped\n");
  230. /* clear the OSF flag */
  231. dm_i2c_reg_write(dev, reg, status & ~RTC_STAT_BIT_OSF);
  232. }
  233. }
  234. tm->tm_sec = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
  235. tm->tm_min = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
  236. tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
  237. tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
  238. tm->tm_mon = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
  239. tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) +
  240. (bcd2bin(buf[RTC_YR_REG_ADDR]) >= 70 ?
  241. 1900 : 2000);
  242. tm->tm_wday = bcd2bin((buf[RTC_DAY_REG_ADDR] - 1) & 0x07);
  243. tm->tm_yday = 0;
  244. tm->tm_isdst = 0;
  245. debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  246. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  247. tm->tm_hour, tm->tm_min, tm->tm_sec);
  248. return 0;
  249. }
  250. static int ds1307_rtc_reset(struct udevice *dev)
  251. {
  252. int ret;
  253. enum ds_type type = dev_get_driver_data(dev);
  254. /*
  255. * reset clock/oscillator in the seconds register:
  256. * on DS1307 bit 7 enables Clock Halt (CH),
  257. * on DS1340 bit 7 disables the oscillator (not EOSC)
  258. * on MCP794xx bit 7 enables Start Oscillator (ST)
  259. */
  260. ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00);
  261. if (ret < 0)
  262. return ret;
  263. if (type == ds_1307) {
  264. /* Write control register in order to enable square-wave
  265. * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0).
  266. */
  267. ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR,
  268. RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 |
  269. RTC_CTL_BIT_RS0);
  270. } else if (type == ds_1337) {
  271. /* Write control register in order to enable oscillator output
  272. * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1).
  273. */
  274. ret = dm_i2c_reg_write(dev, DS1337_CTL_REG_ADDR,
  275. DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1);
  276. } else if (type == ds_1340 || type == mcp794xx || type == m41t11) {
  277. /* Reset clock calibration, frequency test and output level. */
  278. ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00);
  279. }
  280. return ret;
  281. }
  282. static int ds1307_probe(struct udevice *dev)
  283. {
  284. i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
  285. DM_I2C_CHIP_WR_ADDRESS);
  286. return 0;
  287. }
  288. static const struct rtc_ops ds1307_rtc_ops = {
  289. .get = ds1307_rtc_get,
  290. .set = ds1307_rtc_set,
  291. .reset = ds1307_rtc_reset,
  292. };
  293. static const struct udevice_id ds1307_rtc_ids[] = {
  294. { .compatible = "dallas,ds1307", .data = ds_1307 },
  295. { .compatible = "dallas,ds1337", .data = ds_1337 },
  296. { .compatible = "dallas,ds1339", .data = ds_1339 },
  297. { .compatible = "dallas,ds1340", .data = ds_1340 },
  298. { .compatible = "microchip,mcp7940x", .data = mcp794xx },
  299. { .compatible = "microchip,mcp7941x", .data = mcp794xx },
  300. { .compatible = "st,m41t11", .data = m41t11 },
  301. { }
  302. };
  303. U_BOOT_DRIVER(rtc_ds1307) = {
  304. .name = "rtc-ds1307",
  305. .id = UCLASS_RTC,
  306. .probe = ds1307_probe,
  307. .of_match = ds1307_rtc_ids,
  308. .ops = &ds1307_rtc_ops,
  309. };
  310. #endif /* CONFIG_DM_RTC */