cpuidle-imx6sx.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <linux/cpuidle.h>
  6. #include <linux/cpu_pm.h>
  7. #include <linux/module.h>
  8. #include <asm/cacheflush.h>
  9. #include <asm/cpuidle.h>
  10. #include <asm/suspend.h>
  11. #include "common.h"
  12. #include "cpuidle.h"
  13. #include "hardware.h"
  14. static int imx6sx_idle_finish(unsigned long val)
  15. {
  16. /*
  17. * for Cortex-A7 which has an internal L2
  18. * cache, need to flush it before powering
  19. * down ARM platform, since flushing L1 cache
  20. * here again has very small overhead, compared
  21. * to adding conditional code for L2 cache type,
  22. * just call flush_cache_all() is fine.
  23. */
  24. flush_cache_all();
  25. cpu_do_idle();
  26. return 0;
  27. }
  28. static __cpuidle int imx6sx_enter_wait(struct cpuidle_device *dev,
  29. struct cpuidle_driver *drv, int index)
  30. {
  31. imx6_set_lpm(WAIT_UNCLOCKED);
  32. switch (index) {
  33. case 1:
  34. cpu_do_idle();
  35. break;
  36. case 2:
  37. imx6_enable_rbc(true);
  38. imx_gpc_set_arm_power_in_lpm(true);
  39. imx_set_cpu_jump(0, v7_cpu_resume);
  40. /* Need to notify there is a cpu pm operation. */
  41. cpu_pm_enter();
  42. cpu_cluster_pm_enter();
  43. ct_cpuidle_enter();
  44. cpu_suspend(0, imx6sx_idle_finish);
  45. ct_cpuidle_exit();
  46. cpu_cluster_pm_exit();
  47. cpu_pm_exit();
  48. imx_gpc_set_arm_power_in_lpm(false);
  49. imx6_enable_rbc(false);
  50. break;
  51. default:
  52. break;
  53. }
  54. imx6_set_lpm(WAIT_CLOCKED);
  55. return index;
  56. }
  57. static struct cpuidle_driver imx6sx_cpuidle_driver = {
  58. .name = "imx6sx_cpuidle",
  59. .owner = THIS_MODULE,
  60. .states = {
  61. /* WFI */
  62. ARM_CPUIDLE_WFI_STATE,
  63. /* WAIT */
  64. {
  65. .exit_latency = 50,
  66. .target_residency = 75,
  67. .flags = CPUIDLE_FLAG_TIMER_STOP,
  68. .enter = imx6sx_enter_wait,
  69. .name = "WAIT",
  70. .desc = "Clock off",
  71. },
  72. /* WAIT + ARM power off */
  73. {
  74. /*
  75. * ARM gating 31us * 5 + RBC clear 65us
  76. * and some margin for SW execution, here set it
  77. * to 300us.
  78. */
  79. .exit_latency = 300,
  80. .target_residency = 500,
  81. .flags = CPUIDLE_FLAG_TIMER_STOP |
  82. CPUIDLE_FLAG_RCU_IDLE,
  83. .enter = imx6sx_enter_wait,
  84. .name = "LOW-POWER-IDLE",
  85. .desc = "ARM power off",
  86. },
  87. },
  88. .state_count = 3,
  89. .safe_state_index = 0,
  90. };
  91. int __init imx6sx_cpuidle_init(void)
  92. {
  93. imx6_set_int_mem_clk_lpm(true);
  94. imx6_enable_rbc(false);
  95. imx_gpc_set_l2_mem_power_in_lpm(false);
  96. /*
  97. * set ARM power up/down timing to the fastest,
  98. * sw2iso and sw can be set to one 32K cycle = 31us
  99. * except for power up sw2iso which need to be
  100. * larger than LDO ramp up time.
  101. */
  102. imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1);
  103. imx_gpc_set_arm_power_down_timing(1, 1);
  104. return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
  105. }