ad4695.rst 4.7 KB

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  1. .. SPDX-License-Identifier: GPL-2.0-only
  2. =============
  3. AD4695 driver
  4. =============
  5. ADC driver for Analog Devices Inc. AD4695 and similar devices. The module name
  6. is ``ad4695``.
  7. Supported devices
  8. =================
  9. The following chips are supported by this driver:
  10. * `AD4695 <https://www.analog.com/AD4695>`_
  11. * `AD4696 <https://www.analog.com/AD4696>`_
  12. * `AD4697 <https://www.analog.com/AD4697>`_
  13. * `AD4698 <https://www.analog.com/AD4698>`_
  14. Supported features
  15. ==================
  16. SPI wiring modes
  17. ----------------
  18. The driver currently supports the following SPI wiring configuration:
  19. 4-wire mode
  20. ^^^^^^^^^^^
  21. In this mode, CNV and CS are tied together and there is a single SDO line.
  22. .. code-block::
  23. +-------------+ +-------------+
  24. | CS |<-+------| CS |
  25. | CNV |<-+ | |
  26. | ADC | | HOST |
  27. | | | |
  28. | SDI |<--------| SDO |
  29. | SDO |-------->| SDI |
  30. | SCLK |<--------| SCLK |
  31. +-------------+ +-------------+
  32. To use this mode, in the device tree, omit the ``cnv-gpios`` and
  33. ``spi-rx-bus-width`` properties.
  34. Channel configuration
  35. ---------------------
  36. Since the chip supports multiple ways to configure each channel, this must be
  37. described in the device tree based on what is actually wired up to the inputs.
  38. There are three typical configurations:
  39. An ``INx`` pin is used as the positive input with the ``REFGND``, ``COM`` or
  40. the next ``INx`` pin as the negative input.
  41. Pairing with REFGND
  42. ^^^^^^^^^^^^^^^^^^^
  43. Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
  44. the ``REFGND`` pin. The device tree will look like this:
  45. .. code-block::
  46. channel@0 {
  47. reg = <0>; /* IN0 */
  48. };
  49. If no other channel properties are needed (e.g. ``adi,no-high-z``), the channel
  50. node can be omitted entirely.
  51. This will appear on the IIO bus as the ``voltage0`` channel. The processed value
  52. (*raw × scale*) will be the voltage present on the ``IN0`` pin relative to
  53. ``REFGND``. (Offset is always 0 when pairing with ``REFGND``.)
  54. Pairing with COM
  55. ^^^^^^^^^^^^^^^^
  56. Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
  57. the ``COM`` pin. The device tree will look like this:
  58. .. code-block::
  59. com-supply = <&vref_div_2>;
  60. channel@1 {
  61. reg = <1>; /* IN1 */
  62. common-mode-channel = <AD4695_COMMON_MODE_COM>;
  63. bipolar;
  64. };
  65. This will appear on the IIO bus as the ``voltage1`` channel. The processed value
  66. (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
  67. relative to ``REFGND``. (The offset is determined by the ``com-supply`` voltage.)
  68. The macro comes from:
  69. .. code-block::
  70. #include <dt-bindings/iio/adi,ad4695.h>
  71. Pairing two INx pins
  72. ^^^^^^^^^^^^^^^^^^^^
  73. An even-numbered ``INx`` pin and the following odd-numbered ``INx`` pin can be
  74. used as a pseudo-differential input. The device tree for using ``IN2`` as the
  75. positive input and ``IN3`` as the negative input will look like this:
  76. .. code-block::
  77. in3-supply = <&vref_div_2>;
  78. channel@2 {
  79. reg = <2>; /* IN2 */
  80. common-mode-channel = <3>; /* IN3 */
  81. bipolar;
  82. };
  83. This will appear on the IIO bus as the ``voltage2`` channel. The processed value
  84. (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
  85. relative to ``REFGND``. (Offset is determined by the ``in3-supply`` voltage.)
  86. VCC supply
  87. ----------
  88. The chip supports being powered by an external LDO via the ``VCC`` input or an
  89. internal LDO via the ``LDO_IN`` input. The driver looks at the device tree to
  90. determine which is being used. If ``ldo-supply`` is present, then the internal
  91. LDO is used. If ``vcc-supply`` is present, then the external LDO is used and
  92. the internal LDO is disabled.
  93. Reference voltage
  94. -----------------
  95. The chip supports an external reference voltage via the ``REF`` input or an
  96. internal buffered reference voltage via the ``REFIN`` input. The driver looks
  97. at the device tree to determine which is being used. If ``ref-supply`` is
  98. present, then the external reference voltage is used and the internal buffer is
  99. disabled. If ``refin-supply`` is present, then the internal buffered reference
  100. voltage is used.
  101. Gain/offset calibration
  102. -----------------------
  103. System calibration is supported using the channel gain and offset registers via
  104. the ``calibscale`` and ``calibbias`` attributes respectively.
  105. Unimplemented features
  106. ----------------------
  107. - Additional wiring modes
  108. - Threshold events
  109. - Oversampling
  110. - GPIO support
  111. - CRC support
  112. Device buffers
  113. ==============
  114. This driver supports hardware triggered buffers. This uses the "advanced
  115. sequencer" feature of the chip to trigger a burst of conversions.
  116. Also see :doc:`iio_devbuf` for more general information.