ark1668ed-pinctrl.dtsi 11 KB

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  1. #include <dt-bindings/pinctrl/ark-pinfunc.h>
  2. &pinctrl0 {
  3. i2c0 {
  4. pinctrl_i2c0: i2c0-0 {
  5. ark,pins =
  6. <ARK_PBANK_2 10 ARK_PVAL_2 /* i2c0 scl gpio74*/
  7. ARK_PBANK_2 11 ARK_PVAL_2>; /* i2c0 sda gpio75*/
  8. };
  9. };
  10. i2c1 {
  11. pinctrl_i2c1: i2c1-0 {
  12. ark,pins =
  13. <ARK_PBANK_2 12 ARK_PVAL_2 /* i2c0 scl gpio76*/
  14. ARK_PBANK_2 13 ARK_PVAL_2>; /* i2c0 sda gpio77*/
  15. };
  16. };
  17. pwm {
  18. pinctrl_pwm0: pwm-0 {
  19. ark,pins =
  20. <ARK_PBANK_4 11 ARK_PVAL_4>;
  21. };
  22. pinctrl_pwm1: pwm-1 {
  23. ark,pins =
  24. <ARK_PBANK_4 12 ARK_PVAL_4>;
  25. };
  26. pinctrl_pwm2: pwm-2 {
  27. ark,pins =
  28. <ARK_PBANK_4 13 ARK_PVAL_4>;
  29. };
  30. pinctrl_pwm3: pwm-3 {
  31. ark,pins =
  32. <ARK_PBANK_4 14 ARK_PVAL_4>;
  33. };
  34. pinctrl_pwm4: pwm-4 {
  35. ark,pins =
  36. <ARK_PBANK_4 15 ARK_PVAL_4>;
  37. };
  38. pinctrl_pwm5: pwm-5 {
  39. ark,pins =
  40. <ARK_PBANK_4 16 ARK_PVAL_4>;
  41. };
  42. pinctrl_pwm6: pwm-6 {
  43. ark,pins =
  44. <ARK_PBANK_4 17 ARK_PVAL_4>;
  45. };
  46. pinctrl_pwm7: pwm-7 {
  47. ark,pins =
  48. <ARK_PBANK_4 18 ARK_PVAL_4>;
  49. };
  50. };
  51. uart {
  52. pinctrl_uart0: uart0-0 {
  53. ark,pins =
  54. <ARK_PBANK_1 30 ARK_PVAL_5 /* uart0 rx */
  55. ARK_PBANK_1 31 ARK_PVAL_5>; /* uart0 tx */
  56. };
  57. pinctrl_uart1: uart1-0 {
  58. ark,pins =
  59. <ARK_PBANK_2 0 ARK_PVAL_5 /* uart1 rx */
  60. ARK_PBANK_2 1 ARK_PVAL_5 /* uart1 tx */
  61. ARK_PBANK_1 19 ARK_PVAL_5 /* uart1 rts */
  62. ARK_PBANK_1 20 ARK_PVAL_5>; /* uart1 cts_1 */
  63. group-mux = <0x184 2 2 1>; /* uart1_cts_1*/
  64. };
  65. pinctrl_uart2: uart2-0 {
  66. ark,pins =
  67. <ARK_PBANK_2 2 ARK_PVAL_5 /* uart2 rx */
  68. ARK_PBANK_2 3 ARK_PVAL_5 /* uart2 tx */
  69. ARK_PBANK_1 21 ARK_PVAL_5 /* uart2 rts */
  70. ARK_PBANK_1 22 ARK_PVAL_5>; /* uart2 cts_1 */
  71. group-mux = <0x184 4 2 1>; /* uart2_cts_1*/
  72. };
  73. pinctrl_uart3: uart3-0 {
  74. ark,pins =
  75. <ARK_PBANK_2 4 ARK_PVAL_5 /* uart3 rx */
  76. ARK_PBANK_2 5 ARK_PVAL_5>; /* uart3 tx */
  77. };
  78. pinctrl_uart4: uart4-0 {
  79. ark,pins =
  80. <ARK_PBANK_3 10 ARK_PVAL_1 /* uart0 rx */
  81. ARK_PBANK_3 11 ARK_PVAL_1 /* uart0 tx */
  82. ARK_PBANK_3 16 ARK_PVAL_1 /* uart0 rts */
  83. ARK_PBANK_3 17 ARK_PVAL_1>; /* uart0 cts */
  84. };
  85. pinctrl_uart5: uart5-0 {
  86. ark,pins =
  87. <ARK_PBANK_2 8 ARK_PVAL_5 /* uart5 rx */
  88. ARK_PBANK_2 9 ARK_PVAL_5>; /* uart5 tx */
  89. group-mux = <0x184 12 1 0>; /* uart5_rxd_0*/
  90. };
  91. };
  92. lcd {
  93. pinctrl_lcd_rgb888: lcd-rgb-0 {
  94. ark,pins =
  95. <ARK_PBANK_0 8 ARK_PVAL_2 /* r0 */
  96. ARK_PBANK_0 9 ARK_PVAL_2 /* r1 */
  97. ARK_PBANK_0 10 ARK_PVAL_2 /* r2 */
  98. ARK_PBANK_0 11 ARK_PVAL_2 /* r3 */
  99. ARK_PBANK_0 12 ARK_PVAL_2 /* r4 */
  100. ARK_PBANK_0 13 ARK_PVAL_2 /* r5 */
  101. ARK_PBANK_0 14 ARK_PVAL_2 /* r6 */
  102. ARK_PBANK_0 15 ARK_PVAL_2 /* r7 */
  103. ARK_PBANK_0 16 ARK_PVAL_2 /* g0 */
  104. ARK_PBANK_0 17 ARK_PVAL_2 /* g1 */
  105. ARK_PBANK_0 18 ARK_PVAL_2 /* g2 */
  106. ARK_PBANK_0 19 ARK_PVAL_2 /* g3 */
  107. ARK_PBANK_0 20 ARK_PVAL_2 /* g4 */
  108. ARK_PBANK_0 21 ARK_PVAL_2 /* g5 */
  109. ARK_PBANK_0 22 ARK_PVAL_2 /* g6 */
  110. ARK_PBANK_0 23 ARK_PVAL_2 /* g7 */
  111. ARK_PBANK_0 24 ARK_PVAL_2 /* b0 */
  112. ARK_PBANK_0 25 ARK_PVAL_2 /* b1 */
  113. ARK_PBANK_0 26 ARK_PVAL_2 /* b2 */
  114. ARK_PBANK_0 27 ARK_PVAL_2 /* b3 */
  115. ARK_PBANK_0 28 ARK_PVAL_2 /* b4 */
  116. ARK_PBANK_0 29 ARK_PVAL_2 /* b5 */
  117. ARK_PBANK_0 30 ARK_PVAL_2 /* b6 */
  118. ARK_PBANK_0 31 ARK_PVAL_2 /* b7 */
  119. ARK_PBANK_1 0 ARK_PVAL_2 /* de */
  120. ARK_PBANK_1 1 ARK_PVAL_2 /* clk */
  121. ARK_PBANK_1 2 ARK_PVAL_2 /* vsync */
  122. ARK_PBANK_1 3 ARK_PVAL_2>; /* hsync */
  123. };
  124. pinctrl_lcd_dlvds: lcd-dlvds-0 {
  125. ark,pins =
  126. <ARK_PBANK_1 30 ARK_PVAL_1 /* odd_TA_OUTP */
  127. ARK_PBANK_1 31 ARK_PVAL_1 /* odd_TA_OUTN */
  128. ARK_PBANK_2 0 ARK_PVAL_1 /* odd_TB_OUTP */
  129. ARK_PBANK_2 1 ARK_PVAL_1 /* odd_TB_OUTN */
  130. ARK_PBANK_2 2 ARK_PVAL_1 /* odd_TC_OUTP */
  131. ARK_PBANK_2 3 ARK_PVAL_1 /* odd_TC_OUTN */
  132. ARK_PBANK_2 4 ARK_PVAL_1 /* odd_TD_OUTP */
  133. ARK_PBANK_2 5 ARK_PVAL_1 /* odd_TD_OUTN */
  134. ARK_PBANK_2 6 ARK_PVAL_1 /* even_TA_OUTP */
  135. ARK_PBANK_2 7 ARK_PVAL_1 /* even_TA_OUTN */
  136. ARK_PBANK_2 8 ARK_PVAL_1 /* even_TB_OUTP */
  137. ARK_PBANK_2 9 ARK_PVAL_1 /* even_TB_OUTN */
  138. ARK_PBANK_2 10 ARK_PVAL_1 /* even_TC_OUTP */
  139. ARK_PBANK_2 11 ARK_PVAL_1 /* even_TC_OUTN */
  140. ARK_PBANK_2 12 ARK_PVAL_1 /* even_TD_OUTP */
  141. ARK_PBANK_2 13 ARK_PVAL_1 /* even_TD_OUTN */
  142. ARK_PBANK_2 14 ARK_PVAL_1 /* odd_TCLK_OUTP */
  143. ARK_PBANK_2 15 ARK_PVAL_1 /* odd_TCLK_OUTN */
  144. ARK_PBANK_2 16 ARK_PVAL_1 /* even_TCLK_OUTP */
  145. ARK_PBANK_2 17 ARK_PVAL_1>; /* even_TCLK_OUTN */
  146. };
  147. };
  148. i2s {
  149. /*i2s0_out_pad*/
  150. pinctrl_i2s0dac_sadata_out0: i2s0-sadata-out0 {
  151. ark,pins =
  152. <ARK_PBANK_2 17 ARK_PVAL_4>; /* i2s0 sadata out0*/
  153. group-mux = <0x214 2 2 0>; /*PAD_PUD*/
  154. };
  155. pinctrl_i2s0dac_sadata_out1: i2s0-sadata-out1 {
  156. ark,pins =
  157. <ARK_PBANK_2 18 ARK_PVAL_4>; /* i2s0 sadata out1*/
  158. group-mux = <0x214 4 2 0>; /*PAD_PUD*/
  159. };
  160. pinctrl_i2s0dac_sadata_out2: i2s0-sadata-out2 {
  161. ark,pins =
  162. <ARK_PBANK_2 19 ARK_PVAL_4>; /* i2s0 sadata out2*/
  163. group-mux = <0x214 6 2 0>; /*PAD_PUD*/
  164. };
  165. pinctrl_i2s0dac_sync: i2s0-sync {
  166. ark,pins =
  167. <ARK_PBANK_2 14 ARK_PVAL_4>; /* i2s0 syncin/i2s0 syncout */
  168. };
  169. pinctrl_i2s0dac_mclk: i2s0-mclk {
  170. ark,pins =
  171. <ARK_PBANK_2 15 ARK_PVAL_4>; /* i2s0 mclk */
  172. group-mux = <0x210 30 2 0 /*PAD_PUD*/
  173. 0x60 11 1 1>; /*EN*/
  174. };
  175. pinctrl_i2s0dac_bclk: i2s0-bclk {
  176. ark,pins =
  177. <ARK_PBANK_2 16 ARK_PVAL_4>; /* i2s_codec_bclkin/i2s0_bitclk */
  178. group-mux = <0x214 0 2 0 /*PAD_PUD*/
  179. 0x60 12 1 1>; /*EN*/
  180. };
  181. /*i2s0_in_pad*/
  182. pinctrl_i2s0adc_sadata_in0: i2s0-sadata-in0 {
  183. ark,pins =
  184. <ARK_PBANK_2 20 ARK_PVAL_4>; /* i2s0 sadata in0*/
  185. group-mux = <0x214 8 2 0>; /*PAD_PUD*/
  186. };
  187. pinctrl_i2s0adc_sadata_in1: i2s0-sadata-in1 {
  188. ark,pins =
  189. <ARK_PBANK_2 21 ARK_PVAL_4>; /* i2s0 sadata in1*/
  190. group-mux = <0x214 10 2 0>; /*PAD_PUD*/
  191. };
  192. pinctrl_i2s0adc_sync: i2s0-adc-sync {
  193. ark,pins =
  194. <ARK_PBANK_2 22 ARK_PVAL_4>; /* i2s0_adc_syncin/i2s0_adc_syncout */
  195. group-mux = <0x180 4 1 0 /*0:i2s_adc_syncin 1:i2s_adc_syncout*/
  196. 0x214 12 2 0>; /*PAD_PUD*/
  197. };
  198. pinctrl_i2s0adc_mclk: i2s0-adc-mclk {
  199. ark,pins =
  200. <ARK_PBANK_2 23 ARK_PVAL_4>; /* i2s0 adc mclk */
  201. group-mux = <0x214 14 2 0 /*PAD_PUD*/
  202. 0x60 13 1 1>; /*EN*/
  203. };
  204. pinctrl_i2s0adc_bclk: i2s0-adc-bclk {
  205. ark,pins =
  206. <ARK_PBANK_2 24 ARK_PVAL_4>; /* i2s_adc_codec_bclkin/i2s0_adc_bitclk */
  207. group-mux = <0x180 5 1 1
  208. 0x214 16 2 0 /*PAD_PUD*/
  209. 0x60 14 1 1>; /*EN*/
  210. };
  211. /*i2s1_out_pad*/
  212. pinctrl_i2s1dac_sadata_out0: i2s1-sadata-out0 {
  213. ark,pins =
  214. <ARK_PBANK_4 22 ARK_PVAL_4>; /* i2s1 sadata out0*/
  215. group-mux = <0x224 12 2 0>; /*PAD_PUD*/
  216. };
  217. pinctrl_i2s1dac_sadata_out1: i2s1-sadata-out1 {
  218. ark,pins =
  219. <ARK_PBANK_4 23 ARK_PVAL_4>; /* i2s1 sadata out1*/
  220. group-mux = <0x224 14 2 0>; /*PAD_PUD*/
  221. };
  222. pinctrl_i2s1dac_sadata_out2: i2s1-sadata-out2 {
  223. ark,pins =
  224. <ARK_PBANK_4 24 ARK_PVAL_4>; /* i2s1 sadata out2*/
  225. group-mux = <0x224 16 2 0>; /*PAD_PUD*/
  226. };
  227. pinctrl_i2s1dac_sync: i2s1-sync {
  228. ark,pins =
  229. <ARK_PBANK_4 19 ARK_PVAL_4>; /* i2s1 syncin/i2s1 syncout */
  230. group-mux = <0x224 6 2 0>; /*PAD_PUD*/
  231. };
  232. pinctrl_i2s1dac_mclk: i2s1-mclk {
  233. ark,pins =
  234. <ARK_PBANK_4 20 ARK_PVAL_4>; /* i2s1 mclk */
  235. group-mux = <0x224 8 2 0 /*PAD_PUD*/
  236. 0x60 29 1 1>; /*EN*/
  237. };
  238. pinctrl_i2s1dac_bclk: i2s1-bclk {
  239. ark,pins =
  240. <ARK_PBANK_4 21 ARK_PVAL_4>; /* i2s_codec_bclkin/i2s1_bitclk */
  241. group-mux = <0x224 10 2 0 /*PAD_PUD*/
  242. 0x60 30 1 1>; /*EN*/
  243. };
  244. /*i2s1_in_pad*/
  245. pinctrl_i2s1adc_sadata_in0: i2s1-sadata-in0 {
  246. ark,pins =
  247. <ARK_PBANK_4 25 ARK_PVAL_4>; /* i2s1 sadata in0*/
  248. group-mux = <0x184 22 1 1
  249. 0x224 18 2 0>; /*PAD_PUD*/
  250. };
  251. pinctrl_i2s1adc_sadata_in1: i2s1-sadata-in1 {
  252. ark,pins =
  253. <ARK_PBANK_4 26 ARK_PVAL_4>; /* i2s1 sadata in1*/
  254. group-mux = <0x184 22 1 1
  255. 0x224 20 2 0>; /*PAD_PUD*/
  256. };
  257. pinctrl_i2s1adc_sync: i2s1-adc-sync {
  258. ark,pins =
  259. <ARK_PBANK_4 27 ARK_PVAL_4>; /* i2s1_adc_syncin/i2s1_adc_syncout */
  260. group-mux = <0x180 16 1 1 /*0:i2s_adc_syncin 1:i2s_adc_syncout*/
  261. 0x184 20 1 1
  262. 0x224 22 2 0>; /*PAD_PUD*/
  263. };
  264. pinctrl_i2s1adc_mclk: i2s1-adc-mclk {
  265. ark,pins =
  266. <ARK_PBANK_4 28 ARK_PVAL_4>; /* i2s1 adc mclk */
  267. group-mux = <0x224 24 2 0 /*PAD_PUD*/
  268. 0x60 31 1 1>; /*EN*/
  269. };
  270. pinctrl_i2s1adc_bclk: i2s1-adc-bclk {
  271. ark,pins =
  272. <ARK_PBANK_4 29 ARK_PVAL_4>; /* i2s_adc_codec_bclkin/i2s1_adc_bitclk */
  273. group-mux = <0x180 17 1 1
  274. 0x184 21 1 1
  275. 0x224 26 2 0 /*PAD_PUD*/
  276. 0x64 0 1 1>; /*EN*/
  277. };
  278. /*i2s2_audio_codec_pad*/
  279. };
  280. mmc1{
  281. pinctrl_mmc1: mmc1{
  282. ark,pins =
  283. <ARK_PBANK_3 7 ARK_PVAL_1 /* sdmmc1_cmd*/
  284. ARK_PBANK_3 8 ARK_PVAL_1 /* sdmmc1_clk */
  285. ARK_PBANK_3 9 ARK_PVAL_1 /* sdmmc1_ard_detect_n*/
  286. ARK_PBANK_3 10 ARK_PVAL_1 /* sdmmc1_data_in_0*/
  287. ARK_PBANK_3 11 ARK_PVAL_1 /* sdmmc1_data_in_1*/
  288. ARK_PBANK_3 12 ARK_PVAL_1 /* sdmmc1_data_in_2*/
  289. ARK_PBANK_3 13 ARK_PVAL_1>; /* sdmmc1_data_in_3*/
  290. };
  291. };
  292. };