armada-3720-espressobin-ultra.dts 3.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Device Tree file for ESPRESSObin-Ultra board.
  4. * Copyright (C) 2019 Globalscale technologies, Inc.
  5. *
  6. * Jason Hung <jhung@globalscaletechnologies.com>
  7. */
  8. /dts-v1/;
  9. #include "armada-3720-espressobin.dtsi"
  10. / {
  11. model = "Globalscale Marvell ESPRESSOBin Ultra Board";
  12. compatible = "globalscale,espressobin-ultra", "globalscale,espressobin",
  13. "marvell,armada3720", "marvell,armada3700";
  14. aliases {
  15. /* ethernet1 is WAN port */
  16. ethernet1 = &switch0port5;
  17. ethernet2 = &switch0port1;
  18. ethernet3 = &switch0port2;
  19. ethernet4 = &switch0port3;
  20. ethernet5 = &switch0port4;
  21. };
  22. /delete-node/ regulator;
  23. reg_usb3_vbus: usb3-vbus {
  24. compatible = "regulator-fixed";
  25. regulator-name = "usb3-vbus";
  26. regulator-min-microvolt = <5000000>;
  27. regulator-max-microvolt = <5000000>;
  28. enable-active-high;
  29. gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
  30. };
  31. usb3_phy: usb3-phy {
  32. compatible = "usb-nop-xceiv";
  33. vcc-supply = <&reg_usb3_vbus>;
  34. };
  35. gpio-leds {
  36. pinctrl-names = "default";
  37. compatible = "gpio-leds";
  38. /* No assigned functions to the LEDs by default */
  39. led1 {
  40. label = "ebin-ultra:blue:led1";
  41. gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
  42. };
  43. led2 {
  44. label = "ebin-ultra:green:led2";
  45. gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
  46. };
  47. led3 {
  48. label = "ebin-ultra:red:led3";
  49. gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
  50. };
  51. led4 {
  52. label = "ebin-ultra:yellow:led4";
  53. gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
  54. };
  55. };
  56. };
  57. &sdhci0 {
  58. status = "okay";
  59. };
  60. &sdhci1 {
  61. /delete-property/ vqmmc-supply;
  62. status = "disabled";
  63. };
  64. &spi0 {
  65. flash@0 {
  66. partitions {
  67. compatible = "fixed-partitions";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. partition@0 {
  71. label = "firmware";
  72. reg = <0x0 0x3e0000>;
  73. };
  74. partition@3e0000 {
  75. label = "hw-info";
  76. reg = <0x3e0000 0x10000>;
  77. read-only;
  78. };
  79. partition@3f0000 {
  80. label = "u-boot-env";
  81. reg = <0x3f0000 0x10000>;
  82. };
  83. };
  84. };
  85. };
  86. &i2c0 {
  87. status = "okay";
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&i2c1_pins>;
  90. clock-frequency = <100000>;
  91. rtc@51 {
  92. compatible = "nxp,pcf8563";
  93. reg = <0x51>;
  94. };
  95. };
  96. &usb3 {
  97. usb-phy = <&usb3_phy>;
  98. };
  99. &mdio {
  100. /* Switch is @3, not @1 */
  101. /delete-node/ ethernet-switch@1;
  102. extphy: ethernet-phy@1 {
  103. reg = <1>;
  104. reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
  105. };
  106. switch0: ethernet-switch@3 {
  107. compatible = "marvell,mv88e6085";
  108. reg = <3>;
  109. reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
  110. dsa,member = <0 0>;
  111. ethernet-ports {
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. switch0port0: ethernet-port@0 {
  115. reg = <0>;
  116. label = "cpu";
  117. ethernet = <&eth0>;
  118. phy-mode = "rgmii-id";
  119. fixed-link {
  120. speed = <1000>;
  121. full-duplex;
  122. };
  123. };
  124. switch0port1: ethernet-port@1 {
  125. reg = <1>;
  126. label = "lan0";
  127. phy-handle = <&switch0phy0>;
  128. };
  129. switch0port2: ethernet-port@2 {
  130. reg = <2>;
  131. label = "lan1";
  132. phy-handle = <&switch0phy1>;
  133. };
  134. switch0port3: ethernet-port@3 {
  135. reg = <3>;
  136. label = "lan2";
  137. phy-handle = <&switch0phy2>;
  138. };
  139. switch0port4: ethernet-port@4 {
  140. reg = <4>;
  141. label = "lan3";
  142. phy-handle = <&switch0phy3>;
  143. };
  144. switch0port5: ethernet-port@5 {
  145. reg = <5>;
  146. label = "wan";
  147. phy-handle = <&extphy>;
  148. phy-mode = "sgmii";
  149. };
  150. };
  151. mdio {
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. switch0phy0: ethernet-phy@11 {
  155. reg = <0x11>;
  156. };
  157. switch0phy1: ethernet-phy@12 {
  158. reg = <0x12>;
  159. };
  160. switch0phy2: ethernet-phy@13 {
  161. reg = <0x13>;
  162. };
  163. switch0phy3: ethernet-phy@14 {
  164. reg = <0x14>;
  165. };
  166. };
  167. };
  168. };