tegra210-p2371-2180.dts 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. #include "tegra210-p2180.dtsi"
  4. #include "tegra210-p2597.dtsi"
  5. / {
  6. model = "NVIDIA Jetson TX1 Developer Kit";
  7. compatible = "nvidia,p2371-2180", "nvidia,tegra210";
  8. pcie@1003000 {
  9. status = "okay";
  10. hvddio-pex-supply = <&vdd_1v8>;
  11. dvddio-pex-supply = <&vdd_pex_1v05>;
  12. vddio-pex-ctl-supply = <&vdd_1v8>;
  13. pci@1,0 {
  14. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
  15. <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
  16. <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
  17. <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
  18. phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
  19. status = "okay";
  20. };
  21. pci@2,0 {
  22. phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
  23. phy-names = "pcie-0";
  24. status = "okay";
  25. };
  26. };
  27. host1x@50000000 {
  28. dsi@54300000 {
  29. status = "okay";
  30. avdd-dsi-csi-supply = <&vdd_dsi_csi>;
  31. panel@0 {
  32. compatible = "auo,b080uan01";
  33. reg = <0>;
  34. enable-gpios = <&gpio TEGRA_GPIO(V, 2)
  35. GPIO_ACTIVE_HIGH>;
  36. power-supply = <&vdd_5v0_io>;
  37. backlight = <&backlight>;
  38. };
  39. };
  40. };
  41. i2c@7000c400 {
  42. backlight: backlight@2c {
  43. compatible = "ti,lp8557";
  44. reg = <0x2c>;
  45. power-supply = <&vdd_3v3_sys>;
  46. dev-ctrl = /bits/ 8 <0x80>;
  47. init-brt = /bits/ 8 <0xff>;
  48. pwms = <&pwm 0 29334>;
  49. pwm-names = "lp8557";
  50. /* boost frequency 1 MHz */
  51. rom-13h {
  52. rom-addr = /bits/ 8 <0x13>;
  53. rom-val = /bits/ 8 <0x01>;
  54. };
  55. /* 3 LED string */
  56. rom-14h {
  57. rom-addr = /bits/ 8 <0x14>;
  58. rom-val = /bits/ 8 <0x87>;
  59. };
  60. };
  61. };
  62. i2c@7000c500 {
  63. /* carrier board ID EEPROM */
  64. eeprom@57 {
  65. compatible = "atmel,24c02";
  66. reg = <0x57>;
  67. label = "system";
  68. vcc-supply = <&vdd_1v8>;
  69. address-width = <8>;
  70. pagesize = <8>;
  71. size = <256>;
  72. read-only;
  73. };
  74. };
  75. clock@70110000 {
  76. status = "okay";
  77. nvidia,cf = <6>;
  78. nvidia,ci = <0>;
  79. nvidia,cg = <2>;
  80. nvidia,droop-ctrl = <0x00000f00>;
  81. nvidia,force-mode = <1>;
  82. nvidia,sample-rate = <25000>;
  83. nvidia,pwm-min-microvolts = <708000>;
  84. nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
  85. nvidia,pwm-to-pmic;
  86. nvidia,pwm-tristate-microvolts = <1000000>;
  87. nvidia,pwm-voltage-step-microvolts = <19200>;
  88. pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
  89. pinctrl-0 = <&dvfs_pwm_active_state>;
  90. pinctrl-1 = <&dvfs_pwm_inactive_state>;
  91. };
  92. aconnect@702c0000 {
  93. status = "okay";
  94. ahub@702d0800 {
  95. status = "okay";
  96. admaif@702d0000 {
  97. status = "okay";
  98. };
  99. i2s@702d1000 {
  100. status = "okay";
  101. ports {
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. port@0 {
  105. reg = <0>;
  106. i2s1_cif_ep: endpoint {
  107. remote-endpoint = <&xbar_i2s1_ep>;
  108. };
  109. };
  110. i2s1_port: port@1 {
  111. reg = <1>;
  112. i2s1_dap_ep: endpoint {
  113. dai-format = "i2s";
  114. /* Placeholder for external Codec */
  115. };
  116. };
  117. };
  118. };
  119. i2s@702d1100 {
  120. status = "okay";
  121. ports {
  122. #address-cells = <1>;
  123. #size-cells = <0>;
  124. port@0 {
  125. reg = <0>;
  126. i2s2_cif_ep: endpoint {
  127. remote-endpoint = <&xbar_i2s2_ep>;
  128. };
  129. };
  130. i2s2_port: port@1 {
  131. reg = <1>;
  132. i2s2_dap_ep: endpoint {
  133. dai-format = "i2s";
  134. /* Placeholder for external Codec */
  135. };
  136. };
  137. };
  138. };
  139. i2s@702d1200 {
  140. status = "okay";
  141. ports {
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. port@0 {
  145. reg = <0>;
  146. i2s3_cif_ep: endpoint {
  147. remote-endpoint = <&xbar_i2s3_ep>;
  148. };
  149. };
  150. i2s3_port: port@1 {
  151. reg = <1>;
  152. i2s3_dap_ep: endpoint {
  153. dai-format = "i2s";
  154. /* Placeholder for external Codec */
  155. };
  156. };
  157. };
  158. };
  159. i2s@702d1300 {
  160. status = "okay";
  161. ports {
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. port@0 {
  165. reg = <0>;
  166. i2s4_cif_ep: endpoint {
  167. remote-endpoint = <&xbar_i2s4_ep>;
  168. };
  169. };
  170. i2s4_port: port@1 {
  171. reg = <1>;
  172. i2s4_dap_ep: endpoint {
  173. dai-format = "i2s";
  174. /* Placeholder for external Codec */
  175. };
  176. };
  177. };
  178. };
  179. i2s@702d1400 {
  180. status = "okay";
  181. ports {
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. port@0 {
  185. reg = <0>;
  186. i2s5_cif_ep: endpoint {
  187. remote-endpoint = <&xbar_i2s5_ep>;
  188. };
  189. };
  190. i2s5_port: port@1 {
  191. reg = <1>;
  192. i2s5_dap_ep: endpoint {
  193. dai-format = "i2s";
  194. /* Placeholder for external Codec */
  195. };
  196. };
  197. };
  198. };
  199. sfc@702d2000 {
  200. status = "okay";
  201. ports {
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. port@0 {
  205. reg = <0>;
  206. sfc1_cif_in_ep: endpoint {
  207. remote-endpoint = <&xbar_sfc1_in_ep>;
  208. };
  209. };
  210. sfc1_out_port: port@1 {
  211. reg = <1>;
  212. sfc1_cif_out_ep: endpoint {
  213. remote-endpoint = <&xbar_sfc1_out_ep>;
  214. };
  215. };
  216. };
  217. };
  218. sfc@702d2200 {
  219. status = "okay";
  220. ports {
  221. #address-cells = <1>;
  222. #size-cells = <0>;
  223. port@0 {
  224. reg = <0>;
  225. sfc2_cif_in_ep: endpoint {
  226. remote-endpoint = <&xbar_sfc2_in_ep>;
  227. };
  228. };
  229. sfc2_out_port: port@1 {
  230. reg = <1>;
  231. sfc2_cif_out_ep: endpoint {
  232. remote-endpoint = <&xbar_sfc2_out_ep>;
  233. };
  234. };
  235. };
  236. };
  237. sfc@702d2400 {
  238. status = "okay";
  239. ports {
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. port@0 {
  243. reg = <0>;
  244. sfc3_cif_in_ep: endpoint {
  245. remote-endpoint = <&xbar_sfc3_in_ep>;
  246. };
  247. };
  248. sfc3_out_port: port@1 {
  249. reg = <1>;
  250. sfc3_cif_out_ep: endpoint {
  251. remote-endpoint = <&xbar_sfc3_out_ep>;
  252. };
  253. };
  254. };
  255. };
  256. sfc@702d2600 {
  257. status = "okay";
  258. ports {
  259. #address-cells = <1>;
  260. #size-cells = <0>;
  261. port@0 {
  262. reg = <0>;
  263. sfc4_cif_in_ep: endpoint {
  264. remote-endpoint = <&xbar_sfc4_in_ep>;
  265. };
  266. };
  267. sfc4_out_port: port@1 {
  268. reg = <1>;
  269. sfc4_cif_out_ep: endpoint {
  270. remote-endpoint = <&xbar_sfc4_out_ep>;
  271. };
  272. };
  273. };
  274. };
  275. amx@702d3000 {
  276. status = "okay";
  277. ports {
  278. #address-cells = <1>;
  279. #size-cells = <0>;
  280. port@0 {
  281. reg = <0>;
  282. amx1_in1_ep: endpoint {
  283. remote-endpoint = <&xbar_amx1_in1_ep>;
  284. };
  285. };
  286. port@1 {
  287. reg = <1>;
  288. amx1_in2_ep: endpoint {
  289. remote-endpoint = <&xbar_amx1_in2_ep>;
  290. };
  291. };
  292. port@2 {
  293. reg = <2>;
  294. amx1_in3_ep: endpoint {
  295. remote-endpoint = <&xbar_amx1_in3_ep>;
  296. };
  297. };
  298. port@3 {
  299. reg = <3>;
  300. amx1_in4_ep: endpoint {
  301. remote-endpoint = <&xbar_amx1_in4_ep>;
  302. };
  303. };
  304. amx1_out_port: port@4 {
  305. reg = <4>;
  306. amx1_out_ep: endpoint {
  307. remote-endpoint = <&xbar_amx1_out_ep>;
  308. };
  309. };
  310. };
  311. };
  312. amx@702d3100 {
  313. status = "okay";
  314. ports {
  315. #address-cells = <1>;
  316. #size-cells = <0>;
  317. port@0 {
  318. reg = <0>;
  319. amx2_in1_ep: endpoint {
  320. remote-endpoint = <&xbar_amx2_in1_ep>;
  321. };
  322. };
  323. port@1 {
  324. reg = <1>;
  325. amx2_in2_ep: endpoint {
  326. remote-endpoint = <&xbar_amx2_in2_ep>;
  327. };
  328. };
  329. amx2_in3_port: port@2 {
  330. reg = <2>;
  331. amx2_in3_ep: endpoint {
  332. remote-endpoint = <&xbar_amx2_in3_ep>;
  333. };
  334. };
  335. amx2_in4_port: port@3 {
  336. reg = <3>;
  337. amx2_in4_ep: endpoint {
  338. remote-endpoint = <&xbar_amx2_in4_ep>;
  339. };
  340. };
  341. amx2_out_port: port@4 {
  342. reg = <4>;
  343. amx2_out_ep: endpoint {
  344. remote-endpoint = <&xbar_amx2_out_ep>;
  345. };
  346. };
  347. };
  348. };
  349. adx@702d3800 {
  350. status = "okay";
  351. ports {
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354. port@0 {
  355. reg = <0>;
  356. adx1_in_ep: endpoint {
  357. remote-endpoint = <&xbar_adx1_in_ep>;
  358. };
  359. };
  360. adx1_out1_port: port@1 {
  361. reg = <1>;
  362. adx1_out1_ep: endpoint {
  363. remote-endpoint = <&xbar_adx1_out1_ep>;
  364. };
  365. };
  366. adx1_out2_port: port@2 {
  367. reg = <2>;
  368. adx1_out2_ep: endpoint {
  369. remote-endpoint = <&xbar_adx1_out2_ep>;
  370. };
  371. };
  372. adx1_out3_port: port@3 {
  373. reg = <3>;
  374. adx1_out3_ep: endpoint {
  375. remote-endpoint = <&xbar_adx1_out3_ep>;
  376. };
  377. };
  378. adx1_out4_port: port@4 {
  379. reg = <4>;
  380. adx1_out4_ep: endpoint {
  381. remote-endpoint = <&xbar_adx1_out4_ep>;
  382. };
  383. };
  384. };
  385. };
  386. adx@702d3900 {
  387. status = "okay";
  388. ports {
  389. #address-cells = <1>;
  390. #size-cells = <0>;
  391. port@0 {
  392. reg = <0>;
  393. adx2_in_ep: endpoint {
  394. remote-endpoint = <&xbar_adx2_in_ep>;
  395. };
  396. };
  397. adx2_out1_port: port@1 {
  398. reg = <1>;
  399. adx2_out1_ep: endpoint {
  400. remote-endpoint = <&xbar_adx2_out1_ep>;
  401. };
  402. };
  403. adx2_out2_port: port@2 {
  404. reg = <2>;
  405. adx2_out2_ep: endpoint {
  406. remote-endpoint = <&xbar_adx2_out2_ep>;
  407. };
  408. };
  409. adx2_out3_port: port@3 {
  410. reg = <3>;
  411. adx2_out3_ep: endpoint {
  412. remote-endpoint = <&xbar_adx2_out3_ep>;
  413. };
  414. };
  415. adx2_out4_port: port@4 {
  416. reg = <4>;
  417. adx2_out4_ep: endpoint {
  418. remote-endpoint = <&xbar_adx2_out4_ep>;
  419. };
  420. };
  421. };
  422. };
  423. dmic@702d4000 {
  424. status = "okay";
  425. ports {
  426. #address-cells = <1>;
  427. #size-cells = <0>;
  428. port@0 {
  429. reg = <0>;
  430. dmic1_cif_ep: endpoint {
  431. remote-endpoint = <&xbar_dmic1_ep>;
  432. };
  433. };
  434. dmic1_port: port@1 {
  435. reg = <1>;
  436. dmic1_dap_ep: endpoint {
  437. /* Placeholder for external Codec */
  438. };
  439. };
  440. };
  441. };
  442. dmic@702d4100 {
  443. status = "okay";
  444. ports {
  445. #address-cells = <1>;
  446. #size-cells = <0>;
  447. port@0 {
  448. reg = <0>;
  449. dmic2_cif_ep: endpoint {
  450. remote-endpoint = <&xbar_dmic2_ep>;
  451. };
  452. };
  453. dmic2_port: port@1 {
  454. reg = <1>;
  455. dmic2_dap_ep: endpoint {
  456. /* Placeholder for external Codec */
  457. };
  458. };
  459. };
  460. };
  461. dmic@702d4200 {
  462. status = "okay";
  463. ports {
  464. #address-cells = <1>;
  465. #size-cells = <0>;
  466. port@0 {
  467. reg = <0>;
  468. dmic3_cif_ep: endpoint {
  469. remote-endpoint = <&xbar_dmic3_ep>;
  470. };
  471. };
  472. dmic3_port: port@1 {
  473. reg = <1>;
  474. dmic3_dap_ep: endpoint {
  475. /* Placeholder for external Codec */
  476. };
  477. };
  478. };
  479. };
  480. processing-engine@702d8000 {
  481. status = "okay";
  482. ports {
  483. #address-cells = <1>;
  484. #size-cells = <0>;
  485. port@0 {
  486. reg = <0x0>;
  487. ope1_cif_in_ep: endpoint {
  488. remote-endpoint = <&xbar_ope1_in_ep>;
  489. };
  490. };
  491. ope1_out_port: port@1 {
  492. reg = <0x1>;
  493. ope1_cif_out_ep: endpoint {
  494. remote-endpoint = <&xbar_ope1_out_ep>;
  495. };
  496. };
  497. };
  498. };
  499. processing-engine@702d8400 {
  500. status = "okay";
  501. ports {
  502. #address-cells = <1>;
  503. #size-cells = <0>;
  504. port@0 {
  505. reg = <0x0>;
  506. ope2_cif_in_ep: endpoint {
  507. remote-endpoint = <&xbar_ope2_in_ep>;
  508. };
  509. };
  510. ope2_out_port: port@1 {
  511. reg = <0x1>;
  512. ope2_cif_out_ep: endpoint {
  513. remote-endpoint = <&xbar_ope2_out_ep>;
  514. };
  515. };
  516. };
  517. };
  518. mvc@702da000 {
  519. status = "okay";
  520. ports {
  521. #address-cells = <1>;
  522. #size-cells = <0>;
  523. port@0 {
  524. reg = <0>;
  525. mvc1_cif_in_ep: endpoint {
  526. remote-endpoint = <&xbar_mvc1_in_ep>;
  527. };
  528. };
  529. mvc1_out_port: port@1 {
  530. reg = <1>;
  531. mvc1_cif_out_ep: endpoint {
  532. remote-endpoint = <&xbar_mvc1_out_ep>;
  533. };
  534. };
  535. };
  536. };
  537. mvc@702da200 {
  538. status = "okay";
  539. ports {
  540. #address-cells = <1>;
  541. #size-cells = <0>;
  542. port@0 {
  543. reg = <0>;
  544. mvc2_cif_in_ep: endpoint {
  545. remote-endpoint = <&xbar_mvc2_in_ep>;
  546. };
  547. };
  548. mvc2_out_port: port@1 {
  549. reg = <1>;
  550. mvc2_cif_out_ep: endpoint {
  551. remote-endpoint = <&xbar_mvc2_out_ep>;
  552. };
  553. };
  554. };
  555. };
  556. amixer@702dbb00 {
  557. status = "okay";
  558. ports {
  559. #address-cells = <1>;
  560. #size-cells = <0>;
  561. port@0 {
  562. reg = <0x0>;
  563. mixer_in1_ep: endpoint {
  564. remote-endpoint = <&xbar_mixer_in1_ep>;
  565. };
  566. };
  567. port@1 {
  568. reg = <0x1>;
  569. mixer_in2_ep: endpoint {
  570. remote-endpoint = <&xbar_mixer_in2_ep>;
  571. };
  572. };
  573. port@2 {
  574. reg = <0x2>;
  575. mixer_in3_ep: endpoint {
  576. remote-endpoint = <&xbar_mixer_in3_ep>;
  577. };
  578. };
  579. port@3 {
  580. reg = <0x3>;
  581. mixer_in4_ep: endpoint {
  582. remote-endpoint = <&xbar_mixer_in4_ep>;
  583. };
  584. };
  585. port@4 {
  586. reg = <0x4>;
  587. mixer_in5_ep: endpoint {
  588. remote-endpoint = <&xbar_mixer_in5_ep>;
  589. };
  590. };
  591. port@5 {
  592. reg = <0x5>;
  593. mixer_in6_ep: endpoint {
  594. remote-endpoint = <&xbar_mixer_in6_ep>;
  595. };
  596. };
  597. port@6 {
  598. reg = <0x6>;
  599. mixer_in7_ep: endpoint {
  600. remote-endpoint = <&xbar_mixer_in7_ep>;
  601. };
  602. };
  603. port@7 {
  604. reg = <0x7>;
  605. mixer_in8_ep: endpoint {
  606. remote-endpoint = <&xbar_mixer_in8_ep>;
  607. };
  608. };
  609. port@8 {
  610. reg = <0x8>;
  611. mixer_in9_ep: endpoint {
  612. remote-endpoint = <&xbar_mixer_in9_ep>;
  613. };
  614. };
  615. port@9 {
  616. reg = <0x9>;
  617. mixer_in10_ep: endpoint {
  618. remote-endpoint = <&xbar_mixer_in10_ep>;
  619. };
  620. };
  621. mixer_out1_port: port@a {
  622. reg = <0xa>;
  623. mixer_out1_ep: endpoint {
  624. remote-endpoint = <&xbar_mixer_out1_ep>;
  625. };
  626. };
  627. mixer_out2_port: port@b {
  628. reg = <0xb>;
  629. mixer_out2_ep: endpoint {
  630. remote-endpoint = <&xbar_mixer_out2_ep>;
  631. };
  632. };
  633. mixer_out3_port: port@c {
  634. reg = <0xc>;
  635. mixer_out3_ep: endpoint {
  636. remote-endpoint = <&xbar_mixer_out3_ep>;
  637. };
  638. };
  639. mixer_out4_port: port@d {
  640. reg = <0xd>;
  641. mixer_out4_ep: endpoint {
  642. remote-endpoint = <&xbar_mixer_out4_ep>;
  643. };
  644. };
  645. mixer_out5_port: port@e {
  646. reg = <0xe>;
  647. mixer_out5_ep: endpoint {
  648. remote-endpoint = <&xbar_mixer_out5_ep>;
  649. };
  650. };
  651. };
  652. };
  653. ports {
  654. xbar_i2s1_port: port@a {
  655. reg = <0xa>;
  656. xbar_i2s1_ep: endpoint {
  657. remote-endpoint = <&i2s1_cif_ep>;
  658. };
  659. };
  660. xbar_i2s2_port: port@b {
  661. reg = <0xb>;
  662. xbar_i2s2_ep: endpoint {
  663. remote-endpoint = <&i2s2_cif_ep>;
  664. };
  665. };
  666. xbar_i2s3_port: port@c {
  667. reg = <0xc>;
  668. xbar_i2s3_ep: endpoint {
  669. remote-endpoint = <&i2s3_cif_ep>;
  670. };
  671. };
  672. xbar_i2s4_port: port@d {
  673. reg = <0xd>;
  674. xbar_i2s4_ep: endpoint {
  675. remote-endpoint = <&i2s4_cif_ep>;
  676. };
  677. };
  678. xbar_i2s5_port: port@e {
  679. reg = <0xe>;
  680. xbar_i2s5_ep: endpoint {
  681. remote-endpoint = <&i2s5_cif_ep>;
  682. };
  683. };
  684. xbar_dmic1_port: port@f {
  685. reg = <0xf>;
  686. xbar_dmic1_ep: endpoint {
  687. remote-endpoint = <&dmic1_cif_ep>;
  688. };
  689. };
  690. xbar_dmic2_port: port@10 {
  691. reg = <0x10>;
  692. xbar_dmic2_ep: endpoint {
  693. remote-endpoint = <&dmic2_cif_ep>;
  694. };
  695. };
  696. xbar_dmic3_port: port@11 {
  697. reg = <0x11>;
  698. xbar_dmic3_ep: endpoint {
  699. remote-endpoint = <&dmic3_cif_ep>;
  700. };
  701. };
  702. xbar_sfc1_in_port: port@12 {
  703. reg = <0x12>;
  704. xbar_sfc1_in_ep: endpoint {
  705. remote-endpoint = <&sfc1_cif_in_ep>;
  706. };
  707. };
  708. port@13 {
  709. reg = <0x13>;
  710. xbar_sfc1_out_ep: endpoint {
  711. remote-endpoint = <&sfc1_cif_out_ep>;
  712. };
  713. };
  714. xbar_sfc2_in_port: port@14 {
  715. reg = <0x14>;
  716. xbar_sfc2_in_ep: endpoint {
  717. remote-endpoint = <&sfc2_cif_in_ep>;
  718. };
  719. };
  720. port@15 {
  721. reg = <0x15>;
  722. xbar_sfc2_out_ep: endpoint {
  723. remote-endpoint = <&sfc2_cif_out_ep>;
  724. };
  725. };
  726. xbar_sfc3_in_port: port@16 {
  727. reg = <0x16>;
  728. xbar_sfc3_in_ep: endpoint {
  729. remote-endpoint = <&sfc3_cif_in_ep>;
  730. };
  731. };
  732. port@17 {
  733. reg = <0x17>;
  734. xbar_sfc3_out_ep: endpoint {
  735. remote-endpoint = <&sfc3_cif_out_ep>;
  736. };
  737. };
  738. xbar_sfc4_in_port: port@18 {
  739. reg = <0x18>;
  740. xbar_sfc4_in_ep: endpoint {
  741. remote-endpoint = <&sfc4_cif_in_ep>;
  742. };
  743. };
  744. port@19 {
  745. reg = <0x19>;
  746. xbar_sfc4_out_ep: endpoint {
  747. remote-endpoint = <&sfc4_cif_out_ep>;
  748. };
  749. };
  750. xbar_mvc1_in_port: port@1a {
  751. reg = <0x1a>;
  752. xbar_mvc1_in_ep: endpoint {
  753. remote-endpoint = <&mvc1_cif_in_ep>;
  754. };
  755. };
  756. port@1b {
  757. reg = <0x1b>;
  758. xbar_mvc1_out_ep: endpoint {
  759. remote-endpoint = <&mvc1_cif_out_ep>;
  760. };
  761. };
  762. xbar_mvc2_in_port: port@1c {
  763. reg = <0x1c>;
  764. xbar_mvc2_in_ep: endpoint {
  765. remote-endpoint = <&mvc2_cif_in_ep>;
  766. };
  767. };
  768. port@1d {
  769. reg = <0x1d>;
  770. xbar_mvc2_out_ep: endpoint {
  771. remote-endpoint = <&mvc2_cif_out_ep>;
  772. };
  773. };
  774. xbar_amx1_in1_port: port@1e {
  775. reg = <0x1e>;
  776. xbar_amx1_in1_ep: endpoint {
  777. remote-endpoint = <&amx1_in1_ep>;
  778. };
  779. };
  780. xbar_amx1_in2_port: port@1f {
  781. reg = <0x1f>;
  782. xbar_amx1_in2_ep: endpoint {
  783. remote-endpoint = <&amx1_in2_ep>;
  784. };
  785. };
  786. xbar_amx1_in3_port: port@20 {
  787. reg = <0x20>;
  788. xbar_amx1_in3_ep: endpoint {
  789. remote-endpoint = <&amx1_in3_ep>;
  790. };
  791. };
  792. xbar_amx1_in4_port: port@21 {
  793. reg = <0x21>;
  794. xbar_amx1_in4_ep: endpoint {
  795. remote-endpoint = <&amx1_in4_ep>;
  796. };
  797. };
  798. port@22 {
  799. reg = <0x22>;
  800. xbar_amx1_out_ep: endpoint {
  801. remote-endpoint = <&amx1_out_ep>;
  802. };
  803. };
  804. xbar_amx2_in1_port: port@23 {
  805. reg = <0x23>;
  806. xbar_amx2_in1_ep: endpoint {
  807. remote-endpoint = <&amx2_in1_ep>;
  808. };
  809. };
  810. xbar_amx2_in2_port: port@24 {
  811. reg = <0x24>;
  812. xbar_amx2_in2_ep: endpoint {
  813. remote-endpoint = <&amx2_in2_ep>;
  814. };
  815. };
  816. xbar_amx2_in3_port: port@25 {
  817. reg = <0x25>;
  818. xbar_amx2_in3_ep: endpoint {
  819. remote-endpoint = <&amx2_in3_ep>;
  820. };
  821. };
  822. xbar_amx2_in4_port: port@26 {
  823. reg = <0x26>;
  824. xbar_amx2_in4_ep: endpoint {
  825. remote-endpoint = <&amx2_in4_ep>;
  826. };
  827. };
  828. port@27 {
  829. reg = <0x27>;
  830. xbar_amx2_out_ep: endpoint {
  831. remote-endpoint = <&amx2_out_ep>;
  832. };
  833. };
  834. xbar_adx1_in_port: port@28 {
  835. reg = <0x28>;
  836. xbar_adx1_in_ep: endpoint {
  837. remote-endpoint = <&adx1_in_ep>;
  838. };
  839. };
  840. port@29 {
  841. reg = <0x29>;
  842. xbar_adx1_out1_ep: endpoint {
  843. remote-endpoint = <&adx1_out1_ep>;
  844. };
  845. };
  846. port@2a {
  847. reg = <0x2a>;
  848. xbar_adx1_out2_ep: endpoint {
  849. remote-endpoint = <&adx1_out2_ep>;
  850. };
  851. };
  852. port@2b {
  853. reg = <0x2b>;
  854. xbar_adx1_out3_ep: endpoint {
  855. remote-endpoint = <&adx1_out3_ep>;
  856. };
  857. };
  858. port@2c {
  859. reg = <0x2c>;
  860. xbar_adx1_out4_ep: endpoint {
  861. remote-endpoint = <&adx1_out4_ep>;
  862. };
  863. };
  864. xbar_adx2_in_port: port@2d {
  865. reg = <0x2d>;
  866. xbar_adx2_in_ep: endpoint {
  867. remote-endpoint = <&adx2_in_ep>;
  868. };
  869. };
  870. port@2e {
  871. reg = <0x2e>;
  872. xbar_adx2_out1_ep: endpoint {
  873. remote-endpoint = <&adx2_out1_ep>;
  874. };
  875. };
  876. port@2f {
  877. reg = <0x2f>;
  878. xbar_adx2_out2_ep: endpoint {
  879. remote-endpoint = <&adx2_out2_ep>;
  880. };
  881. };
  882. port@30 {
  883. reg = <0x30>;
  884. xbar_adx2_out3_ep: endpoint {
  885. remote-endpoint = <&adx2_out3_ep>;
  886. };
  887. };
  888. port@31 {
  889. reg = <0x31>;
  890. xbar_adx2_out4_ep: endpoint {
  891. remote-endpoint = <&adx2_out4_ep>;
  892. };
  893. };
  894. xbar_mixer_in1_port: port@32 {
  895. reg = <0x32>;
  896. xbar_mixer_in1_ep: endpoint {
  897. remote-endpoint = <&mixer_in1_ep>;
  898. };
  899. };
  900. xbar_mixer_in2_port: port@33 {
  901. reg = <0x33>;
  902. xbar_mixer_in2_ep: endpoint {
  903. remote-endpoint = <&mixer_in2_ep>;
  904. };
  905. };
  906. xbar_mixer_in3_port: port@34 {
  907. reg = <0x34>;
  908. xbar_mixer_in3_ep: endpoint {
  909. remote-endpoint = <&mixer_in3_ep>;
  910. };
  911. };
  912. xbar_mixer_in4_port: port@35 {
  913. reg = <0x35>;
  914. xbar_mixer_in4_ep: endpoint {
  915. remote-endpoint = <&mixer_in4_ep>;
  916. };
  917. };
  918. xbar_mixer_in5_port: port@36 {
  919. reg = <0x36>;
  920. xbar_mixer_in5_ep: endpoint {
  921. remote-endpoint = <&mixer_in5_ep>;
  922. };
  923. };
  924. xbar_mixer_in6_port: port@37 {
  925. reg = <0x37>;
  926. xbar_mixer_in6_ep: endpoint {
  927. remote-endpoint = <&mixer_in6_ep>;
  928. };
  929. };
  930. xbar_mixer_in7_port: port@38 {
  931. reg = <0x38>;
  932. xbar_mixer_in7_ep: endpoint {
  933. remote-endpoint = <&mixer_in7_ep>;
  934. };
  935. };
  936. xbar_mixer_in8_port: port@39 {
  937. reg = <0x39>;
  938. xbar_mixer_in8_ep: endpoint {
  939. remote-endpoint = <&mixer_in8_ep>;
  940. };
  941. };
  942. xbar_mixer_in9_port: port@3a {
  943. reg = <0x3a>;
  944. xbar_mixer_in9_ep: endpoint {
  945. remote-endpoint = <&mixer_in9_ep>;
  946. };
  947. };
  948. xbar_mixer_in10_port: port@3b {
  949. reg = <0x3b>;
  950. xbar_mixer_in10_ep: endpoint {
  951. remote-endpoint = <&mixer_in10_ep>;
  952. };
  953. };
  954. port@3c {
  955. reg = <0x3c>;
  956. xbar_mixer_out1_ep: endpoint {
  957. remote-endpoint = <&mixer_out1_ep>;
  958. };
  959. };
  960. port@3d {
  961. reg = <0x3d>;
  962. xbar_mixer_out2_ep: endpoint {
  963. remote-endpoint = <&mixer_out2_ep>;
  964. };
  965. };
  966. port@3e {
  967. reg = <0x3e>;
  968. xbar_mixer_out3_ep: endpoint {
  969. remote-endpoint = <&mixer_out3_ep>;
  970. };
  971. };
  972. port@3f {
  973. reg = <0x3f>;
  974. xbar_mixer_out4_ep: endpoint {
  975. remote-endpoint = <&mixer_out4_ep>;
  976. };
  977. };
  978. port@40 {
  979. reg = <0x40>;
  980. xbar_mixer_out5_ep: endpoint {
  981. remote-endpoint = <&mixer_out5_ep>;
  982. };
  983. };
  984. xbar_ope1_in_port: port@41 {
  985. reg = <0x41>;
  986. xbar_ope1_in_ep: endpoint {
  987. remote-endpoint = <&ope1_cif_in_ep>;
  988. };
  989. };
  990. port@42 {
  991. reg = <0x42>;
  992. xbar_ope1_out_ep: endpoint {
  993. remote-endpoint = <&ope1_cif_out_ep>;
  994. };
  995. };
  996. xbar_ope2_in_port: port@43 {
  997. reg = <0x43>;
  998. xbar_ope2_in_ep: endpoint {
  999. remote-endpoint = <&ope2_cif_in_ep>;
  1000. };
  1001. };
  1002. port@44 {
  1003. reg = <0x44>;
  1004. xbar_ope2_out_ep: endpoint {
  1005. remote-endpoint = <&ope2_cif_out_ep>;
  1006. };
  1007. };
  1008. };
  1009. };
  1010. dma-controller@702e2000 {
  1011. status = "okay";
  1012. };
  1013. interrupt-controller@702f9000 {
  1014. status = "okay";
  1015. };
  1016. };
  1017. sound {
  1018. compatible = "nvidia,tegra210-audio-graph-card";
  1019. status = "okay";
  1020. dais = /* FE */
  1021. <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
  1022. <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
  1023. <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
  1024. <&admaif10_port>,
  1025. /* Router */
  1026. <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>,
  1027. <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>,
  1028. <&xbar_dmic2_port>, <&xbar_dmic3_port>,
  1029. <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
  1030. <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
  1031. <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
  1032. <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
  1033. <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
  1034. <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
  1035. <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
  1036. <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
  1037. <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
  1038. <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
  1039. <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
  1040. <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
  1041. <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
  1042. <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
  1043. /* HW accelerators */
  1044. <&sfc1_out_port>, <&sfc2_out_port>,
  1045. <&sfc3_out_port>, <&sfc4_out_port>,
  1046. <&mvc1_out_port>, <&mvc2_out_port>,
  1047. <&amx1_out_port>, <&amx2_out_port>,
  1048. <&adx1_out1_port>, <&adx1_out2_port>,
  1049. <&adx1_out3_port>, <&adx1_out4_port>,
  1050. <&adx2_out1_port>, <&adx2_out2_port>,
  1051. <&adx2_out3_port>, <&adx2_out4_port>,
  1052. <&mixer_out1_port>, <&mixer_out2_port>,
  1053. <&mixer_out3_port>, <&mixer_out4_port>,
  1054. <&mixer_out5_port>,
  1055. <&ope1_out_port>, <&ope2_out_port>,
  1056. /* I/O DAP Ports */
  1057. <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
  1058. <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
  1059. label = "NVIDIA Jetson TX1 APE";
  1060. };
  1061. };