tegra210-p2595.dtsi 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/pinctrl/pinctrl-tegra.h>
  3. / {
  4. model = "NVIDIA Tegra210 P2595 I/O board";
  5. compatible = "nvidia,p2595", "nvidia,tegra210";
  6. pinmux: pinmux@700008d4 {
  7. pinctrl-names = "boot";
  8. pinctrl-0 = <&state_boot>;
  9. state_boot: pinmux {
  10. pex_l0_rst_n_pa0 {
  11. nvidia,pins = "pex_l0_rst_n_pa0";
  12. nvidia,function = "pe0";
  13. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  14. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  15. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  16. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  17. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  18. };
  19. pex_l0_clkreq_n_pa1 {
  20. nvidia,pins = "pex_l0_clkreq_n_pa1";
  21. nvidia,function = "pe0";
  22. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  23. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  24. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  25. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  26. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  27. };
  28. pex_wake_n_pa2 {
  29. nvidia,pins = "pex_wake_n_pa2";
  30. nvidia,function = "pe";
  31. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  32. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  33. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  34. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  35. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  36. };
  37. pex_l1_rst_n_pa3 {
  38. nvidia,pins = "pex_l1_rst_n_pa3";
  39. nvidia,function = "pe1";
  40. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  41. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  42. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  43. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  44. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  45. };
  46. pex_l1_clkreq_n_pa4 {
  47. nvidia,pins = "pex_l1_clkreq_n_pa4";
  48. nvidia,function = "pe1";
  49. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  50. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  51. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  52. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  53. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  54. };
  55. sata_led_active_pa5 {
  56. nvidia,pins = "sata_led_active_pa5";
  57. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  58. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  59. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  60. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  61. };
  62. pa6 {
  63. nvidia,pins = "pa6";
  64. nvidia,function = "rsvd1";
  65. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  66. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  67. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  68. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  69. };
  70. dap1_fs_pb0 {
  71. nvidia,pins = "dap1_fs_pb0";
  72. nvidia,function = "i2s1";
  73. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  74. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  75. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  76. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  77. };
  78. dap1_din_pb1 {
  79. nvidia,pins = "dap1_din_pb1";
  80. nvidia,function = "i2s1";
  81. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  82. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  84. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  85. };
  86. dap1_dout_pb2 {
  87. nvidia,pins = "dap1_dout_pb2";
  88. nvidia,function = "i2s1";
  89. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  92. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  93. };
  94. dap1_sclk_pb3 {
  95. nvidia,pins = "dap1_sclk_pb3";
  96. nvidia,function = "i2s1";
  97. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  98. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  99. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  100. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  101. };
  102. spi2_mosi_pb4 {
  103. nvidia,pins = "spi2_mosi_pb4";
  104. nvidia,function = "rsvd2";
  105. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  106. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  107. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  108. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  109. };
  110. spi2_miso_pb5 {
  111. nvidia,pins = "spi2_miso_pb5";
  112. nvidia,function = "rsvd2";
  113. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  114. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  115. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  116. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  117. };
  118. spi2_sck_pb6 {
  119. nvidia,pins = "spi2_sck_pb6";
  120. nvidia,function = "rsvd2";
  121. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  122. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  123. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  124. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  125. };
  126. spi2_cs0_pb7 {
  127. nvidia,pins = "spi2_cs0_pb7";
  128. nvidia,function = "rsvd2";
  129. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  130. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  131. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  132. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  133. };
  134. spi1_mosi_pc0 {
  135. nvidia,pins = "spi1_mosi_pc0";
  136. nvidia,function = "spi1";
  137. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  138. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  139. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  141. };
  142. spi1_miso_pc1 {
  143. nvidia,pins = "spi1_miso_pc1";
  144. nvidia,function = "spi1";
  145. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  147. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  148. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  149. };
  150. spi1_sck_pc2 {
  151. nvidia,pins = "spi1_sck_pc2";
  152. nvidia,function = "spi1";
  153. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  154. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  155. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  156. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  157. };
  158. spi1_cs0_pc3 {
  159. nvidia,pins = "spi1_cs0_pc3";
  160. nvidia,function = "spi1";
  161. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  162. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  163. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  164. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  165. };
  166. spi1_cs1_pc4 {
  167. nvidia,pins = "spi1_cs1_pc4";
  168. nvidia,function = "spi1";
  169. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  170. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  171. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  172. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  173. };
  174. spi4_sck_pc5 {
  175. nvidia,pins = "spi4_sck_pc5";
  176. nvidia,function = "spi4";
  177. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  178. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  180. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  181. };
  182. spi4_cs0_pc6 {
  183. nvidia,pins = "spi4_cs0_pc6";
  184. nvidia,function = "spi4";
  185. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  186. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  187. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  188. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  189. };
  190. spi4_mosi_pc7 {
  191. nvidia,pins = "spi4_mosi_pc7";
  192. nvidia,function = "spi4";
  193. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  194. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  195. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  196. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  197. };
  198. spi4_miso_pd0 {
  199. nvidia,pins = "spi4_miso_pd0";
  200. nvidia,function = "spi4";
  201. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  202. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  203. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  204. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  205. };
  206. uart3_tx_pd1 {
  207. nvidia,pins = "uart3_tx_pd1";
  208. nvidia,function = "uartc";
  209. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  210. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  212. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  213. };
  214. uart3_rx_pd2 {
  215. nvidia,pins = "uart3_rx_pd2";
  216. nvidia,function = "uartc";
  217. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  219. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  220. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  221. };
  222. uart3_rts_pd3 {
  223. nvidia,pins = "uart3_rts_pd3";
  224. nvidia,function = "uartc";
  225. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  226. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  227. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  228. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  229. };
  230. uart3_cts_pd4 {
  231. nvidia,pins = "uart3_cts_pd4";
  232. nvidia,function = "uartc";
  233. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  235. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  236. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  237. };
  238. dmic1_clk_pe0 {
  239. nvidia,pins = "dmic1_clk_pe0";
  240. nvidia,function = "dmic1";
  241. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  243. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  244. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  245. };
  246. dmic1_dat_pe1 {
  247. nvidia,pins = "dmic1_dat_pe1";
  248. nvidia,function = "dmic1";
  249. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  250. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  251. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  252. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  253. };
  254. dmic2_clk_pe2 {
  255. nvidia,pins = "dmic2_clk_pe2";
  256. nvidia,function = "dmic2";
  257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  259. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  260. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  261. };
  262. dmic2_dat_pe3 {
  263. nvidia,pins = "dmic2_dat_pe3";
  264. nvidia,function = "dmic2";
  265. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  268. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  269. };
  270. dmic3_clk_pe4 {
  271. nvidia,pins = "dmic3_clk_pe4";
  272. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  273. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  274. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  275. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  276. };
  277. dmic3_dat_pe5 {
  278. nvidia,pins = "dmic3_dat_pe5";
  279. nvidia,function = "rsvd2";
  280. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  281. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  282. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  283. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  284. };
  285. pe6 {
  286. nvidia,pins = "pe6";
  287. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  288. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  289. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  290. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  291. };
  292. pe7 {
  293. nvidia,pins = "pe7";
  294. nvidia,function = "pwm3";
  295. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  296. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  297. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  298. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  299. };
  300. gen3_i2c_scl_pf0 {
  301. nvidia,pins = "gen3_i2c_scl_pf0";
  302. nvidia,function = "i2c3";
  303. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  304. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  305. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  306. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  307. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  308. };
  309. gen3_i2c_sda_pf1 {
  310. nvidia,pins = "gen3_i2c_sda_pf1";
  311. nvidia,function = "i2c3";
  312. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  313. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  314. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  315. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  316. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  317. };
  318. uart2_tx_pg0 {
  319. nvidia,pins = "uart2_tx_pg0";
  320. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  321. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  322. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  323. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  324. };
  325. uart2_rx_pg1 {
  326. nvidia,pins = "uart2_rx_pg1";
  327. nvidia,function = "uartb";
  328. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  329. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  330. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  331. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  332. };
  333. uart2_rts_pg2 {
  334. nvidia,pins = "uart2_rts_pg2";
  335. nvidia,function = "rsvd2";
  336. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  337. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  338. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  339. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  340. };
  341. uart2_cts_pg3 {
  342. nvidia,pins = "uart2_cts_pg3";
  343. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  344. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  345. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  346. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  347. };
  348. wifi_en_ph0 {
  349. nvidia,pins = "wifi_en_ph0";
  350. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  351. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  352. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  353. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  354. };
  355. wifi_rst_ph1 {
  356. nvidia,pins = "wifi_rst_ph1";
  357. nvidia,function = "rsvd0";
  358. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  359. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  360. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  361. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  362. };
  363. wifi_wake_ap_ph2 {
  364. nvidia,pins = "wifi_wake_ap_ph2";
  365. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  366. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  367. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  368. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  369. };
  370. ap_wake_bt_ph3 {
  371. nvidia,pins = "ap_wake_bt_ph3";
  372. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  373. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  374. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  375. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  376. };
  377. bt_rst_ph4 {
  378. nvidia,pins = "bt_rst_ph4";
  379. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  380. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  381. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  382. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  383. };
  384. bt_wake_ap_ph5 {
  385. nvidia,pins = "bt_wake_ap_ph5";
  386. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  387. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  388. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  389. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  390. };
  391. ph6 {
  392. nvidia,pins = "ph6";
  393. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  395. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  397. };
  398. ap_wake_nfc_ph7 {
  399. nvidia,pins = "ap_wake_nfc_ph7";
  400. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  401. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  402. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  403. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  404. };
  405. nfc_en_pi0 {
  406. nvidia,pins = "nfc_en_pi0";
  407. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  408. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  409. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  410. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  411. };
  412. nfc_int_pi1 {
  413. nvidia,pins = "nfc_int_pi1";
  414. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  415. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  416. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  417. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  418. };
  419. gps_en_pi2 {
  420. nvidia,pins = "gps_en_pi2";
  421. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  422. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  423. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  424. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  425. };
  426. gps_rst_pi3 {
  427. nvidia,pins = "gps_rst_pi3";
  428. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  429. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  430. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  431. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  432. };
  433. uart4_tx_pi4 {
  434. nvidia,pins = "uart4_tx_pi4";
  435. nvidia,function = "uartd";
  436. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  437. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  438. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  439. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  440. };
  441. uart4_rx_pi5 {
  442. nvidia,pins = "uart4_rx_pi5";
  443. nvidia,function = "uartd";
  444. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  445. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  446. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  447. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  448. };
  449. uart4_rts_pi6 {
  450. nvidia,pins = "uart4_rts_pi6";
  451. nvidia,function = "uartd";
  452. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  453. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  454. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  455. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  456. };
  457. uart4_cts_pi7 {
  458. nvidia,pins = "uart4_cts_pi7";
  459. nvidia,function = "uartd";
  460. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  461. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  462. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  463. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  464. };
  465. gen1_i2c_sda_pj0 {
  466. nvidia,pins = "gen1_i2c_sda_pj0";
  467. nvidia,function = "i2c1";
  468. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  469. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  470. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  471. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  472. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  473. };
  474. gen1_i2c_scl_pj1 {
  475. nvidia,pins = "gen1_i2c_scl_pj1";
  476. nvidia,function = "i2c1";
  477. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  478. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  479. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  480. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  481. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  482. };
  483. gen2_i2c_scl_pj2 {
  484. nvidia,pins = "gen2_i2c_scl_pj2";
  485. nvidia,function = "i2c2";
  486. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  487. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  488. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  489. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  490. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  491. };
  492. gen2_i2c_sda_pj3 {
  493. nvidia,pins = "gen2_i2c_sda_pj3";
  494. nvidia,function = "i2c2";
  495. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  496. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  497. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  498. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  499. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  500. };
  501. dap4_fs_pj4 {
  502. nvidia,pins = "dap4_fs_pj4";
  503. nvidia,function = "i2s4b";
  504. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  505. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  506. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  507. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  508. };
  509. dap4_din_pj5 {
  510. nvidia,pins = "dap4_din_pj5";
  511. nvidia,function = "i2s4b";
  512. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  513. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  514. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  515. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  516. };
  517. dap4_dout_pj6 {
  518. nvidia,pins = "dap4_dout_pj6";
  519. nvidia,function = "i2s4b";
  520. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  521. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  522. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  523. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  524. };
  525. dap4_sclk_pj7 {
  526. nvidia,pins = "dap4_sclk_pj7";
  527. nvidia,function = "i2s4b";
  528. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  529. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  530. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  531. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  532. };
  533. pk0 {
  534. nvidia,pins = "pk0";
  535. nvidia,function = "i2s5b";
  536. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  537. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  538. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  539. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  540. };
  541. pk1 {
  542. nvidia,pins = "pk1";
  543. nvidia,function = "i2s5b";
  544. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  545. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  546. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  547. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  548. };
  549. pk2 {
  550. nvidia,pins = "pk2";
  551. nvidia,function = "i2s5b";
  552. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  553. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  554. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  555. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  556. };
  557. pk3 {
  558. nvidia,pins = "pk3";
  559. nvidia,function = "i2s5b";
  560. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  561. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  562. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  563. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  564. };
  565. pk4 {
  566. nvidia,pins = "pk4";
  567. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  568. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  569. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  570. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  571. };
  572. pk5 {
  573. nvidia,pins = "pk5";
  574. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  575. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  576. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  577. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  578. };
  579. pk6 {
  580. nvidia,pins = "pk6";
  581. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  582. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  583. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  584. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  585. };
  586. pk7 {
  587. nvidia,pins = "pk7";
  588. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  589. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  590. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  591. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  592. };
  593. pl0 {
  594. nvidia,pins = "pl0";
  595. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  596. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  597. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  598. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  599. };
  600. pl1 {
  601. nvidia,pins = "pl1";
  602. nvidia,function = "soc";
  603. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  604. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  605. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  606. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  607. };
  608. sdmmc1_clk_pm0 {
  609. nvidia,pins = "sdmmc1_clk_pm0";
  610. nvidia,function = "sdmmc1";
  611. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  612. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  613. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  614. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  615. };
  616. sdmmc1_cmd_pm1 {
  617. nvidia,pins = "sdmmc1_cmd_pm1";
  618. nvidia,function = "sdmmc1";
  619. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  620. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  621. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  622. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  623. };
  624. sdmmc1_dat3_pm2 {
  625. nvidia,pins = "sdmmc1_dat3_pm2";
  626. nvidia,function = "sdmmc1";
  627. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  628. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  629. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  630. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  631. };
  632. sdmmc1_dat2_pm3 {
  633. nvidia,pins = "sdmmc1_dat2_pm3";
  634. nvidia,function = "sdmmc1";
  635. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  636. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  637. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  638. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  639. };
  640. sdmmc1_dat1_pm4 {
  641. nvidia,pins = "sdmmc1_dat1_pm4";
  642. nvidia,function = "sdmmc1";
  643. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  644. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  645. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  646. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  647. };
  648. sdmmc1_dat0_pm5 {
  649. nvidia,pins = "sdmmc1_dat0_pm5";
  650. nvidia,function = "sdmmc1";
  651. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  652. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  653. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  654. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  655. };
  656. sdmmc3_clk_pp0 {
  657. nvidia,pins = "sdmmc3_clk_pp0";
  658. nvidia,function = "sdmmc3";
  659. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  660. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  661. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  662. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  663. };
  664. sdmmc3_cmd_pp1 {
  665. nvidia,pins = "sdmmc3_cmd_pp1";
  666. nvidia,function = "sdmmc3";
  667. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  668. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  669. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  670. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  671. };
  672. sdmmc3_dat3_pp2 {
  673. nvidia,pins = "sdmmc3_dat3_pp2";
  674. nvidia,function = "sdmmc3";
  675. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  676. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  677. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  678. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  679. };
  680. sdmmc3_dat2_pp3 {
  681. nvidia,pins = "sdmmc3_dat2_pp3";
  682. nvidia,function = "sdmmc3";
  683. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  684. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  685. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  686. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  687. };
  688. sdmmc3_dat1_pp4 {
  689. nvidia,pins = "sdmmc3_dat1_pp4";
  690. nvidia,function = "sdmmc3";
  691. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  692. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  693. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  694. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  695. };
  696. sdmmc3_dat0_pp5 {
  697. nvidia,pins = "sdmmc3_dat0_pp5";
  698. nvidia,function = "sdmmc3";
  699. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  700. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  701. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  702. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  703. };
  704. cam1_mclk_ps0 {
  705. nvidia,pins = "cam1_mclk_ps0";
  706. nvidia,function = "extperiph3";
  707. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  708. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  709. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  710. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  711. };
  712. cam2_mclk_ps1 {
  713. nvidia,pins = "cam2_mclk_ps1";
  714. nvidia,function = "extperiph3";
  715. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  716. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  717. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  718. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  719. };
  720. cam_i2c_scl_ps2 {
  721. nvidia,pins = "cam_i2c_scl_ps2";
  722. nvidia,function = "i2cvi";
  723. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  724. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  725. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  726. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  727. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  728. };
  729. cam_i2c_sda_ps3 {
  730. nvidia,pins = "cam_i2c_sda_ps3";
  731. nvidia,function = "i2cvi";
  732. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  733. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  734. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  735. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  736. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  737. };
  738. cam_rst_ps4 {
  739. nvidia,pins = "cam_rst_ps4";
  740. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  741. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  742. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  743. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  744. };
  745. cam_af_en_ps5 {
  746. nvidia,pins = "cam_af_en_ps5";
  747. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  748. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  749. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  750. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  751. };
  752. cam_flash_en_ps6 {
  753. nvidia,pins = "cam_flash_en_ps6";
  754. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  755. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  756. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  757. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  758. };
  759. cam1_pwdn_ps7 {
  760. nvidia,pins = "cam1_pwdn_ps7";
  761. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  762. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  763. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  764. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  765. };
  766. cam2_pwdn_pt0 {
  767. nvidia,pins = "cam2_pwdn_pt0";
  768. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  769. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  770. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  771. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  772. };
  773. cam1_strobe_pt1 {
  774. nvidia,pins = "cam1_strobe_pt1";
  775. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  776. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  777. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  778. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  779. };
  780. uart1_tx_pu0 {
  781. nvidia,pins = "uart1_tx_pu0";
  782. nvidia,function = "uarta";
  783. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  784. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  785. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  786. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  787. };
  788. uart1_rx_pu1 {
  789. nvidia,pins = "uart1_rx_pu1";
  790. nvidia,function = "uarta";
  791. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  792. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  793. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  794. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  795. };
  796. uart1_rts_pu2 {
  797. nvidia,pins = "uart1_rts_pu2";
  798. nvidia,function = "uarta";
  799. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  800. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  801. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  802. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  803. };
  804. uart1_cts_pu3 {
  805. nvidia,pins = "uart1_cts_pu3";
  806. nvidia,function = "uarta";
  807. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  808. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  809. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  810. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  811. };
  812. lcd_bl_pwm_pv0 {
  813. nvidia,pins = "lcd_bl_pwm_pv0";
  814. nvidia,function = "pwm0";
  815. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  816. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  817. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  818. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  819. };
  820. lcd_bl_en_pv1 {
  821. nvidia,pins = "lcd_bl_en_pv1";
  822. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  823. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  824. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  825. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  826. };
  827. lcd_rst_pv2 {
  828. nvidia,pins = "lcd_rst_pv2";
  829. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  830. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  831. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  832. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  833. };
  834. lcd_gpio1_pv3 {
  835. nvidia,pins = "lcd_gpio1_pv3";
  836. nvidia,function = "rsvd1";
  837. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  838. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  839. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  840. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  841. };
  842. lcd_gpio2_pv4 {
  843. nvidia,pins = "lcd_gpio2_pv4";
  844. nvidia,function = "pwm1";
  845. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  846. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  847. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  848. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  849. };
  850. ap_ready_pv5 {
  851. nvidia,pins = "ap_ready_pv5";
  852. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  853. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  854. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  855. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  856. };
  857. touch_rst_pv6 {
  858. nvidia,pins = "touch_rst_pv6";
  859. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  860. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  861. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  862. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  863. };
  864. touch_clk_pv7 {
  865. nvidia,pins = "touch_clk_pv7";
  866. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  867. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  868. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  869. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  870. };
  871. modem_wake_ap_px0 {
  872. nvidia,pins = "modem_wake_ap_px0";
  873. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  874. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  875. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  876. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  877. };
  878. touch_int_px1 {
  879. nvidia,pins = "touch_int_px1";
  880. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  881. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  882. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  883. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  884. };
  885. motion_int_px2 {
  886. nvidia,pins = "motion_int_px2";
  887. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  888. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  889. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  890. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  891. };
  892. als_prox_int_px3 {
  893. nvidia,pins = "als_prox_int_px3";
  894. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  895. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  896. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  897. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  898. };
  899. temp_alert_px4 {
  900. nvidia,pins = "temp_alert_px4";
  901. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  902. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  903. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  904. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  905. };
  906. button_power_on_px5 {
  907. nvidia,pins = "button_power_on_px5";
  908. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  909. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  910. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  911. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  912. };
  913. button_vol_up_px6 {
  914. nvidia,pins = "button_vol_up_px6";
  915. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  916. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  917. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  918. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  919. };
  920. button_vol_down_px7 {
  921. nvidia,pins = "button_vol_down_px7";
  922. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  923. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  924. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  925. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  926. };
  927. button_slide_sw_py0 {
  928. nvidia,pins = "button_slide_sw_py0";
  929. nvidia,function = "rsvd0";
  930. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  931. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  932. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  933. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  934. };
  935. button_home_py1 {
  936. nvidia,pins = "button_home_py1";
  937. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  938. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  939. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  940. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  941. };
  942. lcd_te_py2 {
  943. nvidia,pins = "lcd_te_py2";
  944. nvidia,function = "displaya";
  945. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  946. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  947. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  948. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  949. };
  950. pwr_i2c_scl_py3 {
  951. nvidia,pins = "pwr_i2c_scl_py3";
  952. nvidia,function = "i2cpmu";
  953. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  954. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  955. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  956. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  957. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  958. };
  959. pwr_i2c_sda_py4 {
  960. nvidia,pins = "pwr_i2c_sda_py4";
  961. nvidia,function = "i2cpmu";
  962. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  963. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  964. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  965. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  966. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  967. };
  968. clk_32k_out_py5 {
  969. nvidia,pins = "clk_32k_out_py5";
  970. nvidia,function = "soc";
  971. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  972. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  973. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  974. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  975. };
  976. pz0 {
  977. nvidia,pins = "pz0";
  978. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  979. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  980. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  981. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  982. };
  983. pz1 {
  984. nvidia,pins = "pz1";
  985. nvidia,function = "sdmmc1";
  986. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  987. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  988. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  989. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  990. };
  991. pz2 {
  992. nvidia,pins = "pz2";
  993. nvidia,function = "rsvd2";
  994. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  995. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  996. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  997. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  998. };
  999. pz3 {
  1000. nvidia,pins = "pz3";
  1001. nvidia,function = "rsvd1";
  1002. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1003. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1004. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1005. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1006. };
  1007. pz4 {
  1008. nvidia,pins = "pz4";
  1009. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1010. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1011. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1012. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1013. };
  1014. pz5 {
  1015. nvidia,pins = "pz5";
  1016. nvidia,function = "soc";
  1017. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1018. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1019. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1020. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1021. };
  1022. dap2_fs_paa0 {
  1023. nvidia,pins = "dap2_fs_paa0";
  1024. nvidia,function = "i2s2";
  1025. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1026. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1027. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1028. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1029. };
  1030. dap2_sclk_paa1 {
  1031. nvidia,pins = "dap2_sclk_paa1";
  1032. nvidia,function = "i2s2";
  1033. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1034. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1035. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1036. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1037. };
  1038. dap2_din_paa2 {
  1039. nvidia,pins = "dap2_din_paa2";
  1040. nvidia,function = "i2s2";
  1041. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1042. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1043. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1044. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1045. };
  1046. dap2_dout_paa3 {
  1047. nvidia,pins = "dap2_dout_paa3";
  1048. nvidia,function = "i2s2";
  1049. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1050. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1051. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1052. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1053. };
  1054. aud_mclk_pbb0 {
  1055. nvidia,pins = "aud_mclk_pbb0";
  1056. nvidia,function = "aud";
  1057. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1058. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1059. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1060. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1061. };
  1062. dvfs_pwm_pbb1 {
  1063. nvidia,pins = "dvfs_pwm_pbb1";
  1064. nvidia,function = "cldvfs";
  1065. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1066. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1067. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1068. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1069. };
  1070. dvfs_clk_pbb2 {
  1071. nvidia,pins = "dvfs_clk_pbb2";
  1072. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1073. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1074. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1075. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1076. };
  1077. gpio_x1_aud_pbb3 {
  1078. nvidia,pins = "gpio_x1_aud_pbb3";
  1079. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1080. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1081. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1082. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1083. };
  1084. gpio_x3_aud_pbb4 {
  1085. nvidia,pins = "gpio_x3_aud_pbb4";
  1086. nvidia,function = "rsvd0";
  1087. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1088. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1089. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1090. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1091. };
  1092. hdmi_cec_pcc0 {
  1093. nvidia,pins = "hdmi_cec_pcc0";
  1094. nvidia,function = "cec";
  1095. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1096. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1097. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1098. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1099. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1100. };
  1101. hdmi_int_dp_hpd_pcc1 {
  1102. nvidia,pins = "hdmi_int_dp_hpd_pcc1";
  1103. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1104. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1105. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1106. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1107. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1108. };
  1109. spdif_out_pcc2 {
  1110. nvidia,pins = "spdif_out_pcc2";
  1111. nvidia,function = "rsvd1";
  1112. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1113. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1114. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1115. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1116. };
  1117. spdif_in_pcc3 {
  1118. nvidia,pins = "spdif_in_pcc3";
  1119. nvidia,function = "rsvd1";
  1120. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1121. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1122. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1123. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1124. };
  1125. usb_vbus_en0_pcc4 {
  1126. nvidia,pins = "usb_vbus_en0_pcc4";
  1127. nvidia,function = "usb";
  1128. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1129. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1130. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1131. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1132. nvidia,io-hv = <TEGRA_PIN_ENABLE>;
  1133. };
  1134. usb_vbus_en1_pcc5 {
  1135. nvidia,pins = "usb_vbus_en1_pcc5";
  1136. nvidia,function = "rsvd1";
  1137. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1138. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1139. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1140. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1141. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1142. };
  1143. dp_hpd0_pcc6 {
  1144. nvidia,pins = "dp_hpd0_pcc6";
  1145. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1146. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1147. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1148. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1149. };
  1150. pcc7 {
  1151. nvidia,pins = "pcc7";
  1152. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1153. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1154. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1155. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1156. nvidia,io-hv = <TEGRA_PIN_DISABLE>;
  1157. };
  1158. spi2_cs1_pdd0 {
  1159. nvidia,pins = "spi2_cs1_pdd0";
  1160. nvidia,function = "rsvd1";
  1161. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1162. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1163. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1164. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1165. };
  1166. qspi_sck_pee0 {
  1167. nvidia,pins = "qspi_sck_pee0";
  1168. nvidia,function = "rsvd1";
  1169. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1170. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1171. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1172. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1173. };
  1174. qspi_cs_n_pee1 {
  1175. nvidia,pins = "qspi_cs_n_pee1";
  1176. nvidia,function = "rsvd1";
  1177. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1178. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1179. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1180. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1181. };
  1182. qspi_io0_pee2 {
  1183. nvidia,pins = "qspi_io0_pee2";
  1184. nvidia,function = "rsvd1";
  1185. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1186. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1187. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1188. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1189. };
  1190. qspi_io1_pee3 {
  1191. nvidia,pins = "qspi_io1_pee3";
  1192. nvidia,function = "rsvd1";
  1193. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1194. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1195. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1196. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1197. };
  1198. qspi_io2_pee4 {
  1199. nvidia,pins = "qspi_io2_pee4";
  1200. nvidia,function = "rsvd1";
  1201. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1202. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1203. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1204. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1205. };
  1206. qspi_io3_pee5 {
  1207. nvidia,pins = "qspi_io3_pee5";
  1208. nvidia,function = "rsvd1";
  1209. nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  1210. nvidia,tristate = <TEGRA_PIN_ENABLE>;
  1211. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1212. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1213. };
  1214. core_pwr_req {
  1215. nvidia,pins = "core_pwr_req";
  1216. nvidia,function = "core";
  1217. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1218. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1219. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1220. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1221. };
  1222. cpu_pwr_req {
  1223. nvidia,pins = "cpu_pwr_req";
  1224. nvidia,function = "cpu";
  1225. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1226. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1227. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1228. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1229. };
  1230. pwr_int_n {
  1231. nvidia,pins = "pwr_int_n";
  1232. nvidia,function = "pmi";
  1233. nvidia,pull = <TEGRA_PIN_PULL_UP>;
  1234. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1235. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1236. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1237. };
  1238. clk_32k_in {
  1239. nvidia,pins = "clk_32k_in";
  1240. nvidia,function = "clk";
  1241. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1242. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1243. nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  1244. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1245. };
  1246. jtag_rtck {
  1247. nvidia,pins = "jtag_rtck";
  1248. nvidia,function = "jtag";
  1249. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1250. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1251. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1252. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1253. };
  1254. clk_req {
  1255. nvidia,pins = "clk_req";
  1256. nvidia,function = "sys";
  1257. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1258. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1259. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1260. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1261. };
  1262. shutdown {
  1263. nvidia,pins = "shutdown";
  1264. nvidia,function = "shutdown";
  1265. nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  1266. nvidia,tristate = <TEGRA_PIN_DISABLE>;
  1267. nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  1268. nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  1269. };
  1270. };
  1271. };
  1272. };