alternative.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/mm.h>
  3. #include <linux/module.h>
  4. #include <asm/alternative.h>
  5. #include <asm/cacheflush.h>
  6. #include <asm/inst.h>
  7. #include <asm/sections.h>
  8. int __read_mostly alternatives_patched;
  9. EXPORT_SYMBOL_GPL(alternatives_patched);
  10. #define MAX_PATCH_SIZE (((u8)(-1)) / LOONGARCH_INSN_SIZE)
  11. static int __initdata_or_module debug_alternative;
  12. static int __init debug_alt(char *str)
  13. {
  14. debug_alternative = 1;
  15. return 1;
  16. }
  17. __setup("debug-alternative", debug_alt);
  18. #define DPRINTK(fmt, args...) \
  19. do { \
  20. if (debug_alternative) \
  21. printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
  22. } while (0)
  23. #define DUMP_WORDS(buf, count, fmt, args...) \
  24. do { \
  25. if (unlikely(debug_alternative)) { \
  26. int _j; \
  27. union loongarch_instruction *_buf = buf; \
  28. \
  29. if (!(count)) \
  30. break; \
  31. \
  32. printk(KERN_DEBUG fmt, ##args); \
  33. for (_j = 0; _j < count - 1; _j++) \
  34. printk(KERN_CONT "<%08x> ", _buf[_j].word); \
  35. printk(KERN_CONT "<%08x>\n", _buf[_j].word); \
  36. } \
  37. } while (0)
  38. /* Use this to add nops to a buffer, then text_poke the whole buffer. */
  39. static void __init_or_module add_nops(union loongarch_instruction *insn, int count)
  40. {
  41. while (count--) {
  42. insn->word = INSN_NOP;
  43. insn++;
  44. }
  45. }
  46. /* Is the jump addr in local .altinstructions */
  47. static inline bool in_alt_jump(unsigned long jump, void *start, void *end)
  48. {
  49. return jump >= (unsigned long)start && jump < (unsigned long)end;
  50. }
  51. static void __init_or_module recompute_jump(union loongarch_instruction *buf,
  52. union loongarch_instruction *dest, union loongarch_instruction *src,
  53. void *start, void *end)
  54. {
  55. unsigned int si, si_l, si_h;
  56. unsigned long cur_pc, jump_addr, pc;
  57. long offset;
  58. cur_pc = (unsigned long)src;
  59. pc = (unsigned long)dest;
  60. si_l = src->reg0i26_format.immediate_l;
  61. si_h = src->reg0i26_format.immediate_h;
  62. switch (src->reg0i26_format.opcode) {
  63. case b_op:
  64. case bl_op:
  65. jump_addr = cur_pc + sign_extend64((si_h << 16 | si_l) << 2, 27);
  66. if (in_alt_jump(jump_addr, start, end))
  67. return;
  68. offset = jump_addr - pc;
  69. BUG_ON(offset < -SZ_128M || offset >= SZ_128M);
  70. offset >>= 2;
  71. buf->reg0i26_format.immediate_h = offset >> 16;
  72. buf->reg0i26_format.immediate_l = offset;
  73. return;
  74. }
  75. si_l = src->reg1i21_format.immediate_l;
  76. si_h = src->reg1i21_format.immediate_h;
  77. switch (src->reg1i21_format.opcode) {
  78. case bceqz_op: /* bceqz_op = bcnez_op */
  79. BUG_ON(buf->reg1i21_format.rj & BIT(4));
  80. fallthrough;
  81. case beqz_op:
  82. case bnez_op:
  83. jump_addr = cur_pc + sign_extend64((si_h << 16 | si_l) << 2, 22);
  84. if (in_alt_jump(jump_addr, start, end))
  85. return;
  86. offset = jump_addr - pc;
  87. BUG_ON(offset < -SZ_4M || offset >= SZ_4M);
  88. offset >>= 2;
  89. buf->reg1i21_format.immediate_h = offset >> 16;
  90. buf->reg1i21_format.immediate_l = offset;
  91. return;
  92. }
  93. si = src->reg2i16_format.immediate;
  94. switch (src->reg2i16_format.opcode) {
  95. case beq_op:
  96. case bne_op:
  97. case blt_op:
  98. case bge_op:
  99. case bltu_op:
  100. case bgeu_op:
  101. jump_addr = cur_pc + sign_extend64(si << 2, 17);
  102. if (in_alt_jump(jump_addr, start, end))
  103. return;
  104. offset = jump_addr - pc;
  105. BUG_ON(offset < -SZ_128K || offset >= SZ_128K);
  106. offset >>= 2;
  107. buf->reg2i16_format.immediate = offset;
  108. return;
  109. }
  110. }
  111. static int __init_or_module copy_alt_insns(union loongarch_instruction *buf,
  112. union loongarch_instruction *dest, union loongarch_instruction *src, int nr)
  113. {
  114. int i;
  115. for (i = 0; i < nr; i++) {
  116. buf[i].word = src[i].word;
  117. if (is_pc_ins(&src[i])) {
  118. pr_err("Not support pcrel instruction at present!");
  119. return -EINVAL;
  120. }
  121. if (is_branch_ins(&src[i]) &&
  122. src[i].reg2i16_format.opcode != jirl_op) {
  123. recompute_jump(&buf[i], &dest[i], &src[i], src, src + nr);
  124. }
  125. }
  126. return 0;
  127. }
  128. /*
  129. * text_poke_early - Update instructions on a live kernel at boot time
  130. *
  131. * When you use this code to patch more than one byte of an instruction
  132. * you need to make sure that other CPUs cannot execute this code in parallel.
  133. * Also no thread must be currently preempted in the middle of these
  134. * instructions. And on the local CPU you need to be protected again NMI or MCE
  135. * handlers seeing an inconsistent instruction while you patch.
  136. */
  137. static void *__init_or_module text_poke_early(union loongarch_instruction *insn,
  138. union loongarch_instruction *buf, unsigned int nr)
  139. {
  140. int i;
  141. unsigned long flags;
  142. local_irq_save(flags);
  143. for (i = 0; i < nr; i++)
  144. insn[i].word = buf[i].word;
  145. local_irq_restore(flags);
  146. wbflush();
  147. flush_icache_range((unsigned long)insn, (unsigned long)(insn + nr));
  148. return insn;
  149. }
  150. /*
  151. * Replace instructions with better alternatives for this CPU type. This runs
  152. * before SMP is initialized to avoid SMP problems with self modifying code.
  153. * This implies that asymmetric systems where APs have less capabilities than
  154. * the boot processor are not handled. Tough. Make sure you disable such
  155. * features by hand.
  156. */
  157. void __init_or_module apply_alternatives(struct alt_instr *start, struct alt_instr *end)
  158. {
  159. struct alt_instr *a;
  160. unsigned int nr_instr, nr_repl, nr_insnbuf;
  161. union loongarch_instruction *instr, *replacement;
  162. union loongarch_instruction insnbuf[MAX_PATCH_SIZE];
  163. DPRINTK("alt table %px, -> %px", start, end);
  164. /*
  165. * The scan order should be from start to end. A later scanned
  166. * alternative code can overwrite previously scanned alternative code.
  167. * Some kernel functions (e.g. memcpy, memset, etc) use this order to
  168. * patch code.
  169. *
  170. * So be careful if you want to change the scan order to any other
  171. * order.
  172. */
  173. for (a = start; a < end; a++) {
  174. nr_insnbuf = 0;
  175. instr = (void *)&a->instr_offset + a->instr_offset;
  176. replacement = (void *)&a->replace_offset + a->replace_offset;
  177. BUG_ON(a->instrlen > sizeof(insnbuf));
  178. BUG_ON(a->instrlen & 0x3);
  179. BUG_ON(a->replacementlen & 0x3);
  180. nr_instr = a->instrlen / LOONGARCH_INSN_SIZE;
  181. nr_repl = a->replacementlen / LOONGARCH_INSN_SIZE;
  182. if (!cpu_has(a->feature)) {
  183. DPRINTK("feat not exist: %d, old: (%px len: %d), repl: (%px, len: %d)",
  184. a->feature, instr, a->instrlen,
  185. replacement, a->replacementlen);
  186. continue;
  187. }
  188. DPRINTK("feat: %d, old: (%px len: %d), repl: (%px, len: %d)",
  189. a->feature, instr, a->instrlen,
  190. replacement, a->replacementlen);
  191. DUMP_WORDS(instr, nr_instr, "%px: old_insn: ", instr);
  192. DUMP_WORDS(replacement, nr_repl, "%px: rpl_insn: ", replacement);
  193. copy_alt_insns(insnbuf, instr, replacement, nr_repl);
  194. nr_insnbuf = nr_repl;
  195. if (nr_instr > nr_repl) {
  196. add_nops(insnbuf + nr_repl, nr_instr - nr_repl);
  197. nr_insnbuf += nr_instr - nr_repl;
  198. }
  199. DUMP_WORDS(insnbuf, nr_insnbuf, "%px: final_insn: ", instr);
  200. text_poke_early(instr, insnbuf, nr_insnbuf);
  201. }
  202. }
  203. void __init alternative_instructions(void)
  204. {
  205. apply_alternatives(__alt_instructions, __alt_instructions_end);
  206. alternatives_patched = 1;
  207. }