genex.S 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. *
  5. * Derived from MIPS:
  6. * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
  7. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  8. * Copyright (C) 2002, 2007 Maciej W. Rozycki
  9. * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
  10. */
  11. #include <asm/asm.h>
  12. #include <asm/asmmacro.h>
  13. #include <asm/loongarch.h>
  14. #include <asm/regdef.h>
  15. #include <asm/fpregdef.h>
  16. #include <asm/stackframe.h>
  17. #include <asm/thread_info.h>
  18. .align 5
  19. SYM_FUNC_START(__arch_cpu_idle)
  20. /* start of idle interrupt region */
  21. ori t0, zero, CSR_CRMD_IE
  22. /* idle instruction needs irq enabled */
  23. csrxchg t0, t0, LOONGARCH_CSR_CRMD
  24. /*
  25. * If an interrupt lands here; between enabling interrupts above and
  26. * going idle on the next instruction, we must *NOT* go idle since the
  27. * interrupt could have set TIF_NEED_RESCHED or caused an timer to need
  28. * reprogramming. Fall through -- see handle_vint() below -- and have
  29. * the idle loop take care of things.
  30. */
  31. idle 0
  32. /* end of idle interrupt region */
  33. 1: jr ra
  34. SYM_FUNC_END(__arch_cpu_idle)
  35. SYM_CODE_START(handle_vint)
  36. UNWIND_HINT_UNDEFINED
  37. BACKUP_T0T1
  38. SAVE_ALL
  39. la_abs t1, 1b
  40. LONG_L t0, sp, PT_ERA
  41. /* 3 instructions idle interrupt region */
  42. ori t0, t0, 0b1100
  43. bne t0, t1, 1f
  44. LONG_S t0, sp, PT_ERA
  45. 1: move a0, sp
  46. move a1, sp
  47. la_abs t0, do_vint
  48. jirl ra, t0, 0
  49. RESTORE_ALL_AND_RET
  50. SYM_CODE_END(handle_vint)
  51. SYM_CODE_START(except_vec_cex)
  52. UNWIND_HINT_UNDEFINED
  53. b cache_parity_error
  54. SYM_CODE_END(except_vec_cex)
  55. .macro build_prep_badv
  56. csrrd t0, LOONGARCH_CSR_BADV
  57. PTR_S t0, sp, PT_BVADDR
  58. .endm
  59. .macro build_prep_fcsr
  60. movfcsr2gr a1, fcsr0
  61. .endm
  62. .macro build_prep_none
  63. .endm
  64. .macro BUILD_HANDLER exception handler prep
  65. .align 5
  66. SYM_CODE_START(handle_\exception)
  67. UNWIND_HINT_UNDEFINED
  68. 666:
  69. BACKUP_T0T1
  70. SAVE_ALL
  71. build_prep_\prep
  72. move a0, sp
  73. la_abs t0, do_\handler
  74. jirl ra, t0, 0
  75. 668:
  76. RESTORE_ALL_AND_RET
  77. SYM_CODE_END(handle_\exception)
  78. .pushsection ".data", "aw", %progbits
  79. SYM_DATA(unwind_hint_\exception, .word 668b - 666b)
  80. .popsection
  81. .endm
  82. BUILD_HANDLER ade ade badv
  83. BUILD_HANDLER ale ale badv
  84. BUILD_HANDLER bce bce none
  85. BUILD_HANDLER bp bp none
  86. BUILD_HANDLER fpe fpe fcsr
  87. BUILD_HANDLER fpu fpu none
  88. BUILD_HANDLER lsx lsx none
  89. BUILD_HANDLER lasx lasx none
  90. BUILD_HANDLER lbt lbt none
  91. BUILD_HANDLER ri ri none
  92. BUILD_HANDLER watch watch none
  93. BUILD_HANDLER reserved reserved none /* others */
  94. SYM_CODE_START(handle_sys)
  95. UNWIND_HINT_UNDEFINED
  96. la_abs t0, handle_syscall
  97. jr t0
  98. SYM_CODE_END(handle_sys)