mpfs-m100pfsevp.dts 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Original all-in-one devicetree:
  4. * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
  5. * Rewritten to use includes:
  6. * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
  7. */
  8. /dts-v1/;
  9. #include "mpfs.dtsi"
  10. #include "mpfs-m100pfs-fabric.dtsi"
  11. / {
  12. model = "Aries Embedded M100PFEVPS";
  13. compatible = "aries,m100pfsevp", "microchip,mpfs";
  14. aliases {
  15. ethernet0 = &mac0;
  16. ethernet1 = &mac1;
  17. serial0 = &mmuart0;
  18. serial1 = &mmuart1;
  19. serial2 = &mmuart2;
  20. serial3 = &mmuart3;
  21. serial4 = &mmuart4;
  22. gpio0 = &gpio0;
  23. gpio1 = &gpio2;
  24. };
  25. chosen {
  26. stdout-path = "serial1:115200n8";
  27. };
  28. ddrc_cache_lo: memory@80000000 {
  29. device_type = "memory";
  30. reg = <0x0 0x80000000 0x0 0x40000000>;
  31. };
  32. ddrc_cache_hi: memory@1040000000 {
  33. device_type = "memory";
  34. reg = <0x10 0x40000000 0x0 0x40000000>;
  35. };
  36. };
  37. &can0 {
  38. status = "okay";
  39. };
  40. &i2c0 {
  41. status = "okay";
  42. };
  43. &i2c1 {
  44. status = "okay";
  45. };
  46. &gpio0 {
  47. interrupts = <13>, <14>, <15>, <16>,
  48. <17>, <18>, <19>, <20>,
  49. <21>, <22>, <23>, <24>,
  50. <25>, <26>;
  51. ngpios = <14>;
  52. status = "okay";
  53. pmic-irq-hog {
  54. gpio-hog;
  55. gpios = <13 0>;
  56. input;
  57. };
  58. /* Set to low for eMMC, high for SD-card */
  59. mmc-sel-hog {
  60. gpio-hog;
  61. gpios = <12 0>;
  62. output-high;
  63. };
  64. };
  65. &gpio2 {
  66. interrupts = <13>, <14>, <15>, <16>,
  67. <17>, <18>, <19>, <20>,
  68. <21>, <22>, <23>, <24>,
  69. <25>, <26>, <27>, <28>,
  70. <29>, <30>, <31>, <32>,
  71. <33>, <34>, <35>, <36>,
  72. <37>, <38>, <39>, <40>,
  73. <41>, <42>, <43>, <44>;
  74. status = "okay";
  75. };
  76. &mac0 {
  77. status = "okay";
  78. phy-mode = "gmii";
  79. phy-handle = <&phy0>;
  80. phy0: ethernet-phy@0 {
  81. reg = <0>;
  82. };
  83. };
  84. &mac1 {
  85. status = "okay";
  86. phy-mode = "gmii";
  87. phy-handle = <&phy1>;
  88. phy1: ethernet-phy@0 {
  89. reg = <0>;
  90. };
  91. };
  92. &mbox {
  93. status = "okay";
  94. };
  95. &mmc {
  96. max-frequency = <50000000>;
  97. bus-width = <4>;
  98. cap-mmc-highspeed;
  99. cap-sd-highspeed;
  100. no-1-8-v;
  101. sd-uhs-sdr12;
  102. sd-uhs-sdr25;
  103. sd-uhs-sdr50;
  104. sd-uhs-sdr104;
  105. disable-wp;
  106. status = "okay";
  107. };
  108. &mmuart1 {
  109. status = "okay";
  110. };
  111. &mmuart2 {
  112. status = "okay";
  113. };
  114. &mmuart3 {
  115. status = "okay";
  116. };
  117. &mmuart4 {
  118. status = "okay";
  119. };
  120. &pcie {
  121. status = "okay";
  122. };
  123. &qspi {
  124. status = "okay";
  125. };
  126. &refclk {
  127. clock-frequency = <125000000>;
  128. };
  129. &rtc {
  130. status = "okay";
  131. };
  132. &spi0 {
  133. status = "okay";
  134. };
  135. &spi1 {
  136. status = "okay";
  137. };
  138. &syscontroller {
  139. status = "okay";
  140. };
  141. &usb {
  142. status = "okay";
  143. dr_mode = "host";
  144. };