spcr.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012, Intel Corporation
  4. * Copyright (c) 2015, Red Hat, Inc.
  5. * Copyright (c) 2015, 2016 Linaro Ltd.
  6. */
  7. #define pr_fmt(fmt) "ACPI: SPCR: " fmt
  8. #include <linux/acpi.h>
  9. #include <linux/console.h>
  10. #include <linux/kernel.h>
  11. #include <linux/serial_core.h>
  12. /*
  13. * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
  14. * occasionally getting stuck as 1. To avoid the potential for a hang, check
  15. * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
  16. * implementations, so only do so if an affected platform is detected in
  17. * acpi_parse_spcr().
  18. */
  19. bool qdf2400_e44_present;
  20. EXPORT_SYMBOL(qdf2400_e44_present);
  21. /*
  22. * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
  23. * Detect them by examining the OEM fields in the SPCR header, similar to PCI
  24. * quirk detection in pci_mcfg.c.
  25. */
  26. static bool qdf2400_erratum_44_present(struct acpi_table_header *h)
  27. {
  28. if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE))
  29. return false;
  30. if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE))
  31. return true;
  32. if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) &&
  33. h->oem_revision == 1)
  34. return true;
  35. return false;
  36. }
  37. /*
  38. * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
  39. * register aligned to 32-bit. In addition, the BIOS also encoded the
  40. * access width to be 8 bits. This function detects this errata condition.
  41. */
  42. static bool xgene_8250_erratum_present(struct acpi_table_spcr *tb)
  43. {
  44. bool xgene_8250 = false;
  45. if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE)
  46. return false;
  47. if (memcmp(tb->header.oem_id, "APMC0D", ACPI_OEM_ID_SIZE) &&
  48. memcmp(tb->header.oem_id, "HPE ", ACPI_OEM_ID_SIZE))
  49. return false;
  50. if (!memcmp(tb->header.oem_table_id, "XGENESPC",
  51. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 0)
  52. xgene_8250 = true;
  53. if (!memcmp(tb->header.oem_table_id, "ProLiant",
  54. ACPI_OEM_TABLE_ID_SIZE) && tb->header.oem_revision == 1)
  55. xgene_8250 = true;
  56. return xgene_8250;
  57. }
  58. /**
  59. * acpi_parse_spcr() - parse ACPI SPCR table and add preferred console
  60. * @enable_earlycon: set up earlycon for the console specified by the table
  61. * @enable_console: setup the console specified by the table.
  62. *
  63. * For the architectures with support for ACPI, CONFIG_ACPI_SPCR_TABLE may be
  64. * defined to parse ACPI SPCR table. As a result of the parsing preferred
  65. * console is registered and if @enable_earlycon is true, earlycon is set up.
  66. * If @enable_console is true the system console is also configured.
  67. *
  68. * When CONFIG_ACPI_SPCR_TABLE is defined, this function should be called
  69. * from arch initialization code as soon as the DT/ACPI decision is made.
  70. */
  71. int __init acpi_parse_spcr(bool enable_earlycon, bool enable_console)
  72. {
  73. static char opts[64];
  74. struct acpi_table_spcr *table;
  75. acpi_status status;
  76. char *uart;
  77. char *iotype;
  78. int baud_rate;
  79. int err;
  80. if (acpi_disabled)
  81. return -ENODEV;
  82. status = acpi_get_table(ACPI_SIG_SPCR, 0, (struct acpi_table_header **)&table);
  83. if (ACPI_FAILURE(status))
  84. return -ENOENT;
  85. if (table->header.revision < 2)
  86. pr_info("SPCR table version %d\n", table->header.revision);
  87. if (table->serial_port.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
  88. u32 bit_width = table->serial_port.access_width;
  89. if (bit_width > ACPI_ACCESS_BIT_MAX) {
  90. pr_err(FW_BUG "Unacceptable wide SPCR Access Width. Defaulting to byte size\n");
  91. bit_width = ACPI_ACCESS_BIT_DEFAULT;
  92. }
  93. switch (ACPI_ACCESS_BIT_WIDTH((bit_width))) {
  94. default:
  95. pr_err(FW_BUG "Unexpected SPCR Access Width. Defaulting to byte size\n");
  96. fallthrough;
  97. case 8:
  98. iotype = "mmio";
  99. break;
  100. case 16:
  101. iotype = "mmio16";
  102. break;
  103. case 32:
  104. iotype = "mmio32";
  105. break;
  106. }
  107. } else
  108. iotype = "io";
  109. switch (table->interface_type) {
  110. case ACPI_DBG2_ARM_SBSA_32BIT:
  111. iotype = "mmio32";
  112. fallthrough;
  113. case ACPI_DBG2_ARM_PL011:
  114. case ACPI_DBG2_ARM_SBSA_GENERIC:
  115. case ACPI_DBG2_BCM2835:
  116. uart = "pl011";
  117. break;
  118. case ACPI_DBG2_16550_COMPATIBLE:
  119. case ACPI_DBG2_16550_SUBSET:
  120. case ACPI_DBG2_16550_WITH_GAS:
  121. case ACPI_DBG2_16550_NVIDIA:
  122. uart = "uart";
  123. break;
  124. default:
  125. err = -ENOENT;
  126. goto done;
  127. }
  128. switch (table->baud_rate) {
  129. case 0:
  130. /*
  131. * SPCR 1.04 defines 0 as a preconfigured state of UART.
  132. * Assume firmware or bootloader configures console correctly.
  133. */
  134. baud_rate = 0;
  135. break;
  136. case 3:
  137. baud_rate = 9600;
  138. break;
  139. case 4:
  140. baud_rate = 19200;
  141. break;
  142. case 6:
  143. baud_rate = 57600;
  144. break;
  145. case 7:
  146. baud_rate = 115200;
  147. break;
  148. default:
  149. err = -ENOENT;
  150. goto done;
  151. }
  152. /*
  153. * If the E44 erratum is required, then we need to tell the pl011
  154. * driver to implement the work-around.
  155. *
  156. * The global variable is used by the probe function when it
  157. * creates the UARTs, whether or not they're used as a console.
  158. *
  159. * If the user specifies "traditional" earlycon, the qdf2400_e44
  160. * console name matches the EARLYCON_DECLARE() statement, and
  161. * SPCR is not used. Parameter "earlycon" is false.
  162. *
  163. * If the user specifies "SPCR" earlycon, then we need to update
  164. * the console name so that it also says "qdf2400_e44". Parameter
  165. * "earlycon" is true.
  166. *
  167. * For consistency, if we change the console name, then we do it
  168. * for everyone, not just earlycon.
  169. */
  170. if (qdf2400_erratum_44_present(&table->header)) {
  171. qdf2400_e44_present = true;
  172. if (enable_earlycon)
  173. uart = "qdf2400_e44";
  174. }
  175. if (xgene_8250_erratum_present(table)) {
  176. iotype = "mmio32";
  177. /*
  178. * For xgene v1 and v2 we don't know the clock rate of the
  179. * UART so don't attempt to change to the baud rate state
  180. * in the table because driver cannot calculate the dividers
  181. */
  182. baud_rate = 0;
  183. }
  184. if (!baud_rate) {
  185. snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
  186. table->serial_port.address);
  187. } else {
  188. snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
  189. table->serial_port.address, baud_rate);
  190. }
  191. pr_info("console: %s\n", opts);
  192. if (enable_earlycon)
  193. setup_earlycon(opts);
  194. if (enable_console)
  195. err = add_preferred_console(uart, 0, opts + strlen(uart) + 1);
  196. else
  197. err = 0;
  198. done:
  199. acpi_put_table((struct acpi_table_header *)table);
  200. return err;
  201. }