btqca.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Bluetooth supports for Qualcomm Atheros chips
  4. *
  5. * Copyright (c) 2015 The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/firmware.h>
  9. #include <linux/vmalloc.h>
  10. #include <net/bluetooth/bluetooth.h>
  11. #include <net/bluetooth/hci_core.h>
  12. #include "btqca.h"
  13. int qca_read_soc_version(struct hci_dev *hdev, struct qca_btsoc_version *ver,
  14. enum qca_btsoc_type soc_type)
  15. {
  16. struct sk_buff *skb;
  17. struct edl_event_hdr *edl;
  18. char cmd;
  19. int err = 0;
  20. u8 event_type = HCI_EV_VENDOR;
  21. u8 rlen = sizeof(*edl) + sizeof(*ver);
  22. u8 rtype = EDL_APP_VER_RES_EVT;
  23. bt_dev_dbg(hdev, "QCA Version Request");
  24. /* Unlike other SoC's sending version command response as payload to
  25. * VSE event. WCN3991 sends version command response as a payload to
  26. * command complete event.
  27. */
  28. if (soc_type >= QCA_WCN3991) {
  29. event_type = 0;
  30. rlen += 1;
  31. rtype = EDL_PATCH_VER_REQ_CMD;
  32. }
  33. cmd = EDL_PATCH_VER_REQ_CMD;
  34. skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, EDL_PATCH_CMD_LEN,
  35. &cmd, event_type, HCI_INIT_TIMEOUT);
  36. if (IS_ERR(skb)) {
  37. err = PTR_ERR(skb);
  38. bt_dev_err(hdev, "Reading QCA version information failed (%d)",
  39. err);
  40. return err;
  41. }
  42. if (skb->len != rlen) {
  43. bt_dev_err(hdev, "QCA Version size mismatch len %d", skb->len);
  44. err = -EILSEQ;
  45. goto out;
  46. }
  47. edl = (struct edl_event_hdr *)(skb->data);
  48. if (edl->cresp != EDL_CMD_REQ_RES_EVT ||
  49. edl->rtype != rtype) {
  50. bt_dev_err(hdev, "QCA Wrong packet received %d %d", edl->cresp,
  51. edl->rtype);
  52. err = -EIO;
  53. goto out;
  54. }
  55. if (soc_type >= QCA_WCN3991)
  56. memcpy(ver, edl->data + 1, sizeof(*ver));
  57. else
  58. memcpy(ver, &edl->data, sizeof(*ver));
  59. bt_dev_info(hdev, "QCA Product ID :0x%08x",
  60. le32_to_cpu(ver->product_id));
  61. bt_dev_info(hdev, "QCA SOC Version :0x%08x",
  62. le32_to_cpu(ver->soc_id));
  63. bt_dev_info(hdev, "QCA ROM Version :0x%08x",
  64. le16_to_cpu(ver->rom_ver));
  65. bt_dev_info(hdev, "QCA Patch Version:0x%08x",
  66. le16_to_cpu(ver->patch_ver));
  67. if (ver->soc_id == 0 || ver->rom_ver == 0)
  68. err = -EILSEQ;
  69. out:
  70. kfree_skb(skb);
  71. if (err)
  72. bt_dev_err(hdev, "QCA Failed to get version (%d)", err);
  73. return err;
  74. }
  75. EXPORT_SYMBOL_GPL(qca_read_soc_version);
  76. static int qca_read_fw_build_info(struct hci_dev *hdev)
  77. {
  78. struct sk_buff *skb;
  79. struct edl_event_hdr *edl;
  80. char *build_label;
  81. char cmd;
  82. int build_lbl_len, err = 0;
  83. bt_dev_dbg(hdev, "QCA read fw build info");
  84. cmd = EDL_GET_BUILD_INFO_CMD;
  85. skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, EDL_PATCH_CMD_LEN,
  86. &cmd, 0, HCI_INIT_TIMEOUT);
  87. if (IS_ERR(skb)) {
  88. err = PTR_ERR(skb);
  89. bt_dev_err(hdev, "Reading QCA fw build info failed (%d)",
  90. err);
  91. return err;
  92. }
  93. if (skb->len < sizeof(*edl)) {
  94. err = -EILSEQ;
  95. goto out;
  96. }
  97. edl = (struct edl_event_hdr *)(skb->data);
  98. if (edl->cresp != EDL_CMD_REQ_RES_EVT ||
  99. edl->rtype != EDL_GET_BUILD_INFO_CMD) {
  100. bt_dev_err(hdev, "QCA Wrong packet received %d %d", edl->cresp,
  101. edl->rtype);
  102. err = -EIO;
  103. goto out;
  104. }
  105. if (skb->len < sizeof(*edl) + 1) {
  106. err = -EILSEQ;
  107. goto out;
  108. }
  109. build_lbl_len = edl->data[0];
  110. if (skb->len < sizeof(*edl) + 1 + build_lbl_len) {
  111. err = -EILSEQ;
  112. goto out;
  113. }
  114. build_label = kstrndup(&edl->data[1], build_lbl_len, GFP_KERNEL);
  115. if (!build_label) {
  116. err = -ENOMEM;
  117. goto out;
  118. }
  119. hci_set_fw_info(hdev, "%s", build_label);
  120. kfree(build_label);
  121. out:
  122. kfree_skb(skb);
  123. return err;
  124. }
  125. static int qca_send_patch_config_cmd(struct hci_dev *hdev)
  126. {
  127. const u8 cmd[] = { EDL_PATCH_CONFIG_CMD, 0x01, 0, 0, 0 };
  128. struct sk_buff *skb;
  129. struct edl_event_hdr *edl;
  130. int err;
  131. bt_dev_dbg(hdev, "QCA Patch config");
  132. skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, sizeof(cmd),
  133. cmd, 0, HCI_INIT_TIMEOUT);
  134. if (IS_ERR(skb)) {
  135. err = PTR_ERR(skb);
  136. bt_dev_err(hdev, "Sending QCA Patch config failed (%d)", err);
  137. return err;
  138. }
  139. if (skb->len != 2) {
  140. bt_dev_err(hdev, "QCA Patch config cmd size mismatch len %d", skb->len);
  141. err = -EILSEQ;
  142. goto out;
  143. }
  144. edl = (struct edl_event_hdr *)(skb->data);
  145. if (edl->cresp != EDL_PATCH_CONFIG_RES_EVT || edl->rtype != EDL_PATCH_CONFIG_CMD) {
  146. bt_dev_err(hdev, "QCA Wrong packet received %d %d", edl->cresp,
  147. edl->rtype);
  148. err = -EIO;
  149. goto out;
  150. }
  151. err = 0;
  152. out:
  153. kfree_skb(skb);
  154. return err;
  155. }
  156. static int qca_send_reset(struct hci_dev *hdev)
  157. {
  158. struct sk_buff *skb;
  159. int err;
  160. bt_dev_dbg(hdev, "QCA HCI_RESET");
  161. skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
  162. if (IS_ERR(skb)) {
  163. err = PTR_ERR(skb);
  164. bt_dev_err(hdev, "QCA Reset failed (%d)", err);
  165. return err;
  166. }
  167. kfree_skb(skb);
  168. return 0;
  169. }
  170. static int qca_read_fw_board_id(struct hci_dev *hdev, u16 *bid)
  171. {
  172. u8 cmd;
  173. struct sk_buff *skb;
  174. struct edl_event_hdr *edl;
  175. int err = 0;
  176. cmd = EDL_GET_BID_REQ_CMD;
  177. skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, EDL_PATCH_CMD_LEN,
  178. &cmd, 0, HCI_INIT_TIMEOUT);
  179. if (IS_ERR(skb)) {
  180. err = PTR_ERR(skb);
  181. bt_dev_err(hdev, "Reading QCA board ID failed (%d)", err);
  182. return err;
  183. }
  184. edl = skb_pull_data(skb, sizeof(*edl));
  185. if (!edl) {
  186. bt_dev_err(hdev, "QCA read board ID with no header");
  187. err = -EILSEQ;
  188. goto out;
  189. }
  190. if (edl->cresp != EDL_CMD_REQ_RES_EVT ||
  191. edl->rtype != EDL_GET_BID_REQ_CMD) {
  192. bt_dev_err(hdev, "QCA Wrong packet: %d %d", edl->cresp, edl->rtype);
  193. err = -EIO;
  194. goto out;
  195. }
  196. if (skb->len < 3) {
  197. err = -EILSEQ;
  198. goto out;
  199. }
  200. *bid = (edl->data[1] << 8) + edl->data[2];
  201. bt_dev_dbg(hdev, "%s: bid = %x", __func__, *bid);
  202. out:
  203. kfree_skb(skb);
  204. return err;
  205. }
  206. int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
  207. {
  208. struct sk_buff *skb;
  209. int err;
  210. bt_dev_dbg(hdev, "QCA pre shutdown cmd");
  211. skb = __hci_cmd_sync_ev(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
  212. NULL, HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
  213. if (IS_ERR(skb)) {
  214. err = PTR_ERR(skb);
  215. bt_dev_err(hdev, "QCA preshutdown_cmd failed (%d)", err);
  216. return err;
  217. }
  218. kfree_skb(skb);
  219. return 0;
  220. }
  221. EXPORT_SYMBOL_GPL(qca_send_pre_shutdown_cmd);
  222. static int qca_tlv_check_data(struct hci_dev *hdev,
  223. struct qca_fw_config *config,
  224. u8 *fw_data, size_t fw_size,
  225. enum qca_btsoc_type soc_type)
  226. {
  227. const u8 *data;
  228. u32 type_len;
  229. u16 tag_id, tag_len;
  230. int idx, length;
  231. struct tlv_type_hdr *tlv;
  232. struct tlv_type_patch *tlv_patch;
  233. struct tlv_type_nvm *tlv_nvm;
  234. uint8_t nvm_baud_rate = config->user_baud_rate;
  235. u8 type;
  236. config->dnld_mode = QCA_SKIP_EVT_NONE;
  237. config->dnld_type = QCA_SKIP_EVT_NONE;
  238. switch (config->type) {
  239. case ELF_TYPE_PATCH:
  240. if (fw_size < 7)
  241. return -EINVAL;
  242. config->dnld_mode = QCA_SKIP_EVT_VSE_CC;
  243. config->dnld_type = QCA_SKIP_EVT_VSE_CC;
  244. bt_dev_dbg(hdev, "File Class : 0x%x", fw_data[4]);
  245. bt_dev_dbg(hdev, "Data Encoding : 0x%x", fw_data[5]);
  246. bt_dev_dbg(hdev, "File version : 0x%x", fw_data[6]);
  247. break;
  248. case TLV_TYPE_PATCH:
  249. if (fw_size < sizeof(struct tlv_type_hdr) + sizeof(struct tlv_type_patch))
  250. return -EINVAL;
  251. tlv = (struct tlv_type_hdr *)fw_data;
  252. type_len = le32_to_cpu(tlv->type_len);
  253. tlv_patch = (struct tlv_type_patch *)tlv->data;
  254. /* For Rome version 1.1 to 3.1, all segment commands
  255. * are acked by a vendor specific event (VSE).
  256. * For Rome >= 3.2, the download mode field indicates
  257. * if VSE is skipped by the controller.
  258. * In case VSE is skipped, only the last segment is acked.
  259. */
  260. config->dnld_mode = tlv_patch->download_mode;
  261. config->dnld_type = config->dnld_mode;
  262. BT_DBG("TLV Type\t\t : 0x%x", type_len & 0x000000ff);
  263. BT_DBG("Total Length : %d bytes",
  264. le32_to_cpu(tlv_patch->total_size));
  265. BT_DBG("Patch Data Length : %d bytes",
  266. le32_to_cpu(tlv_patch->data_length));
  267. BT_DBG("Signing Format Version : 0x%x",
  268. tlv_patch->format_version);
  269. BT_DBG("Signature Algorithm : 0x%x",
  270. tlv_patch->signature);
  271. BT_DBG("Download mode : 0x%x",
  272. tlv_patch->download_mode);
  273. BT_DBG("Reserved : 0x%x",
  274. tlv_patch->reserved1);
  275. BT_DBG("Product ID : 0x%04x",
  276. le16_to_cpu(tlv_patch->product_id));
  277. BT_DBG("Rom Build Version : 0x%04x",
  278. le16_to_cpu(tlv_patch->rom_build));
  279. BT_DBG("Patch Version : 0x%04x",
  280. le16_to_cpu(tlv_patch->patch_version));
  281. BT_DBG("Reserved : 0x%x",
  282. le16_to_cpu(tlv_patch->reserved2));
  283. BT_DBG("Patch Entry Address : 0x%x",
  284. le32_to_cpu(tlv_patch->entry));
  285. break;
  286. case TLV_TYPE_NVM:
  287. if (fw_size < sizeof(struct tlv_type_hdr))
  288. return -EINVAL;
  289. tlv = (struct tlv_type_hdr *)fw_data;
  290. type_len = le32_to_cpu(tlv->type_len);
  291. length = type_len >> 8;
  292. type = type_len & 0xff;
  293. /* Some NVM files have more than one set of tags, only parse
  294. * the first set when it has type 2 for now. When there is
  295. * more than one set there is an enclosing header of type 4.
  296. */
  297. if (type == 4) {
  298. if (fw_size < 2 * sizeof(struct tlv_type_hdr))
  299. return -EINVAL;
  300. tlv++;
  301. type_len = le32_to_cpu(tlv->type_len);
  302. length = type_len >> 8;
  303. type = type_len & 0xff;
  304. }
  305. BT_DBG("TLV Type\t\t : 0x%x", type);
  306. BT_DBG("Length\t\t : %d bytes", length);
  307. if (type != 2)
  308. break;
  309. if (fw_size < length + (tlv->data - fw_data))
  310. return -EINVAL;
  311. idx = 0;
  312. data = tlv->data;
  313. while (idx < length - sizeof(struct tlv_type_nvm)) {
  314. tlv_nvm = (struct tlv_type_nvm *)(data + idx);
  315. tag_id = le16_to_cpu(tlv_nvm->tag_id);
  316. tag_len = le16_to_cpu(tlv_nvm->tag_len);
  317. if (length < idx + sizeof(struct tlv_type_nvm) + tag_len)
  318. return -EINVAL;
  319. /* Update NVM tags as needed */
  320. switch (tag_id) {
  321. case EDL_TAG_ID_BD_ADDR:
  322. if (tag_len != sizeof(bdaddr_t))
  323. return -EINVAL;
  324. memcpy(&config->bdaddr, tlv_nvm->data, sizeof(bdaddr_t));
  325. break;
  326. case EDL_TAG_ID_HCI:
  327. if (tag_len < 3)
  328. return -EINVAL;
  329. /* HCI transport layer parameters
  330. * enabling software inband sleep
  331. * onto controller side.
  332. */
  333. tlv_nvm->data[0] |= 0x80;
  334. /* UART Baud Rate */
  335. if (soc_type >= QCA_WCN3991)
  336. tlv_nvm->data[1] = nvm_baud_rate;
  337. else
  338. tlv_nvm->data[2] = nvm_baud_rate;
  339. break;
  340. case EDL_TAG_ID_DEEP_SLEEP:
  341. if (tag_len < 1)
  342. return -EINVAL;
  343. /* Sleep enable mask
  344. * enabling deep sleep feature on controller.
  345. */
  346. tlv_nvm->data[0] |= 0x01;
  347. break;
  348. }
  349. idx += sizeof(struct tlv_type_nvm) + tag_len;
  350. }
  351. break;
  352. default:
  353. BT_ERR("Unknown TLV type %d", config->type);
  354. return -EINVAL;
  355. }
  356. return 0;
  357. }
  358. static int qca_tlv_send_segment(struct hci_dev *hdev, int seg_size,
  359. const u8 *data, enum qca_tlv_dnld_mode mode,
  360. enum qca_btsoc_type soc_type)
  361. {
  362. struct sk_buff *skb;
  363. struct edl_event_hdr *edl;
  364. struct tlv_seg_resp *tlv_resp;
  365. u8 cmd[MAX_SIZE_PER_TLV_SEGMENT + 2];
  366. int err = 0;
  367. u8 event_type = HCI_EV_VENDOR;
  368. u8 rlen = (sizeof(*edl) + sizeof(*tlv_resp));
  369. u8 rtype = EDL_TVL_DNLD_RES_EVT;
  370. cmd[0] = EDL_PATCH_TLV_REQ_CMD;
  371. cmd[1] = seg_size;
  372. memcpy(cmd + 2, data, seg_size);
  373. if (mode == QCA_SKIP_EVT_VSE_CC || mode == QCA_SKIP_EVT_VSE)
  374. return __hci_cmd_send(hdev, EDL_PATCH_CMD_OPCODE, seg_size + 2,
  375. cmd);
  376. /* Unlike other SoC's sending version command response as payload to
  377. * VSE event. WCN3991 sends version command response as a payload to
  378. * command complete event.
  379. */
  380. if (soc_type >= QCA_WCN3991) {
  381. event_type = 0;
  382. rlen = sizeof(*edl);
  383. rtype = EDL_PATCH_TLV_REQ_CMD;
  384. }
  385. skb = __hci_cmd_sync_ev(hdev, EDL_PATCH_CMD_OPCODE, seg_size + 2, cmd,
  386. event_type, HCI_INIT_TIMEOUT);
  387. if (IS_ERR(skb)) {
  388. err = PTR_ERR(skb);
  389. bt_dev_err(hdev, "QCA Failed to send TLV segment (%d)", err);
  390. return err;
  391. }
  392. if (skb->len != rlen) {
  393. bt_dev_err(hdev, "QCA TLV response size mismatch");
  394. err = -EILSEQ;
  395. goto out;
  396. }
  397. edl = (struct edl_event_hdr *)(skb->data);
  398. if (edl->cresp != EDL_CMD_REQ_RES_EVT || edl->rtype != rtype) {
  399. bt_dev_err(hdev, "QCA TLV with error stat 0x%x rtype 0x%x",
  400. edl->cresp, edl->rtype);
  401. err = -EIO;
  402. }
  403. if (soc_type >= QCA_WCN3991)
  404. goto out;
  405. tlv_resp = (struct tlv_seg_resp *)(edl->data);
  406. if (tlv_resp->result) {
  407. bt_dev_err(hdev, "QCA TLV with error stat 0x%x rtype 0x%x (0x%x)",
  408. edl->cresp, edl->rtype, tlv_resp->result);
  409. }
  410. out:
  411. kfree_skb(skb);
  412. return err;
  413. }
  414. static int qca_inject_cmd_complete_event(struct hci_dev *hdev)
  415. {
  416. struct hci_event_hdr *hdr;
  417. struct hci_ev_cmd_complete *evt;
  418. struct sk_buff *skb;
  419. skb = bt_skb_alloc(sizeof(*hdr) + sizeof(*evt) + 1, GFP_KERNEL);
  420. if (!skb)
  421. return -ENOMEM;
  422. hdr = skb_put(skb, sizeof(*hdr));
  423. hdr->evt = HCI_EV_CMD_COMPLETE;
  424. hdr->plen = sizeof(*evt) + 1;
  425. evt = skb_put(skb, sizeof(*evt));
  426. evt->ncmd = 1;
  427. evt->opcode = cpu_to_le16(QCA_HCI_CC_OPCODE);
  428. skb_put_u8(skb, QCA_HCI_CC_SUCCESS);
  429. hci_skb_pkt_type(skb) = HCI_EVENT_PKT;
  430. return hci_recv_frame(hdev, skb);
  431. }
  432. static int qca_download_firmware(struct hci_dev *hdev,
  433. struct qca_fw_config *config,
  434. enum qca_btsoc_type soc_type,
  435. u8 rom_ver)
  436. {
  437. const struct firmware *fw;
  438. u8 *data;
  439. const u8 *segment;
  440. int ret, size, remain, i = 0;
  441. bt_dev_info(hdev, "QCA Downloading %s", config->fwname);
  442. ret = request_firmware(&fw, config->fwname, &hdev->dev);
  443. if (ret) {
  444. /* For WCN6750, if mbn file is not present then check for
  445. * tlv file.
  446. */
  447. if (soc_type == QCA_WCN6750 && config->type == ELF_TYPE_PATCH) {
  448. bt_dev_dbg(hdev, "QCA Failed to request file: %s (%d)",
  449. config->fwname, ret);
  450. config->type = TLV_TYPE_PATCH;
  451. snprintf(config->fwname, sizeof(config->fwname),
  452. "qca/msbtfw%02x.tlv", rom_ver);
  453. bt_dev_info(hdev, "QCA Downloading %s", config->fwname);
  454. ret = request_firmware(&fw, config->fwname, &hdev->dev);
  455. if (ret) {
  456. bt_dev_err(hdev, "QCA Failed to request file: %s (%d)",
  457. config->fwname, ret);
  458. return ret;
  459. }
  460. } else {
  461. bt_dev_err(hdev, "QCA Failed to request file: %s (%d)",
  462. config->fwname, ret);
  463. return ret;
  464. }
  465. }
  466. size = fw->size;
  467. data = vmalloc(fw->size);
  468. if (!data) {
  469. bt_dev_err(hdev, "QCA Failed to allocate memory for file: %s",
  470. config->fwname);
  471. release_firmware(fw);
  472. return -ENOMEM;
  473. }
  474. memcpy(data, fw->data, size);
  475. release_firmware(fw);
  476. ret = qca_tlv_check_data(hdev, config, data, size, soc_type);
  477. if (ret)
  478. goto out;
  479. segment = data;
  480. remain = size;
  481. while (remain > 0) {
  482. int segsize = min(MAX_SIZE_PER_TLV_SEGMENT, remain);
  483. bt_dev_dbg(hdev, "Send segment %d, size %d", i++, segsize);
  484. remain -= segsize;
  485. /* The last segment is always acked regardless download mode */
  486. if (!remain || segsize < MAX_SIZE_PER_TLV_SEGMENT)
  487. config->dnld_mode = QCA_SKIP_EVT_NONE;
  488. ret = qca_tlv_send_segment(hdev, segsize, segment,
  489. config->dnld_mode, soc_type);
  490. if (ret)
  491. goto out;
  492. segment += segsize;
  493. }
  494. /* Latest qualcomm chipsets are not sending a command complete event
  495. * for every fw packet sent. They only respond with a vendor specific
  496. * event for the last packet. This optimization in the chip will
  497. * decrease the BT in initialization time. Here we will inject a command
  498. * complete event to avoid a command timeout error message.
  499. */
  500. if (config->dnld_type == QCA_SKIP_EVT_VSE_CC ||
  501. config->dnld_type == QCA_SKIP_EVT_VSE)
  502. ret = qca_inject_cmd_complete_event(hdev);
  503. out:
  504. vfree(data);
  505. return ret;
  506. }
  507. static int qca_disable_soc_logging(struct hci_dev *hdev)
  508. {
  509. struct sk_buff *skb;
  510. u8 cmd[2];
  511. int err;
  512. cmd[0] = QCA_DISABLE_LOGGING_SUB_OP;
  513. cmd[1] = 0x00;
  514. skb = __hci_cmd_sync_ev(hdev, QCA_DISABLE_LOGGING, sizeof(cmd), cmd,
  515. HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
  516. if (IS_ERR(skb)) {
  517. err = PTR_ERR(skb);
  518. bt_dev_err(hdev, "QCA Failed to disable soc logging(%d)", err);
  519. return err;
  520. }
  521. kfree_skb(skb);
  522. return 0;
  523. }
  524. int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
  525. {
  526. struct sk_buff *skb;
  527. u8 cmd[9];
  528. int err;
  529. cmd[0] = EDL_NVM_ACCESS_SET_REQ_CMD;
  530. cmd[1] = 0x02; /* TAG ID */
  531. cmd[2] = sizeof(bdaddr_t); /* size */
  532. memcpy(cmd + 3, bdaddr, sizeof(bdaddr_t));
  533. skb = __hci_cmd_sync_ev(hdev, EDL_NVM_ACCESS_OPCODE, sizeof(cmd), cmd,
  534. HCI_EV_VENDOR, HCI_INIT_TIMEOUT);
  535. if (IS_ERR(skb)) {
  536. err = PTR_ERR(skb);
  537. bt_dev_err(hdev, "QCA Change address command failed (%d)", err);
  538. return err;
  539. }
  540. kfree_skb(skb);
  541. return 0;
  542. }
  543. EXPORT_SYMBOL_GPL(qca_set_bdaddr_rome);
  544. static int qca_check_bdaddr(struct hci_dev *hdev, const struct qca_fw_config *config)
  545. {
  546. struct hci_rp_read_bd_addr *bda;
  547. struct sk_buff *skb;
  548. int err;
  549. if (bacmp(&hdev->public_addr, BDADDR_ANY))
  550. return 0;
  551. skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL,
  552. HCI_INIT_TIMEOUT);
  553. if (IS_ERR(skb)) {
  554. err = PTR_ERR(skb);
  555. bt_dev_err(hdev, "Failed to read device address (%d)", err);
  556. return err;
  557. }
  558. if (skb->len != sizeof(*bda)) {
  559. bt_dev_err(hdev, "Device address length mismatch");
  560. kfree_skb(skb);
  561. return -EIO;
  562. }
  563. bda = (struct hci_rp_read_bd_addr *)skb->data;
  564. if (!bacmp(&bda->bdaddr, &config->bdaddr))
  565. set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks);
  566. kfree_skb(skb);
  567. return 0;
  568. }
  569. static void qca_generate_hsp_nvm_name(char *fwname, size_t max_size,
  570. struct qca_btsoc_version ver, u8 rom_ver, u16 bid)
  571. {
  572. const char *variant;
  573. /* hsp gf chip */
  574. if ((le32_to_cpu(ver.soc_id) & QCA_HSP_GF_SOC_MASK) == QCA_HSP_GF_SOC_ID)
  575. variant = "g";
  576. else
  577. variant = "";
  578. if (bid == 0x0)
  579. snprintf(fwname, max_size, "qca/hpnv%02x%s.bin", rom_ver, variant);
  580. else
  581. snprintf(fwname, max_size, "qca/hpnv%02x%s.%x", rom_ver, variant, bid);
  582. }
  583. static inline void qca_get_nvm_name_generic(struct qca_fw_config *cfg,
  584. const char *stem, u8 rom_ver, u16 bid)
  585. {
  586. if (bid == 0x0)
  587. snprintf(cfg->fwname, sizeof(cfg->fwname), "qca/%snv%02x.bin", stem, rom_ver);
  588. else if (bid & 0xff00)
  589. snprintf(cfg->fwname, sizeof(cfg->fwname),
  590. "qca/%snv%02x.b%x", stem, rom_ver, bid);
  591. else
  592. snprintf(cfg->fwname, sizeof(cfg->fwname),
  593. "qca/%snv%02x.b%02x", stem, rom_ver, bid);
  594. }
  595. int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
  596. enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
  597. const char *firmware_name)
  598. {
  599. struct qca_fw_config config = {};
  600. int err;
  601. u8 rom_ver = 0;
  602. u32 soc_ver;
  603. u16 boardid = 0;
  604. bt_dev_dbg(hdev, "QCA setup on UART");
  605. soc_ver = get_soc_ver(ver.soc_id, ver.rom_ver);
  606. bt_dev_info(hdev, "QCA controller version 0x%08x", soc_ver);
  607. config.user_baud_rate = baudrate;
  608. /* Firmware files to download are based on ROM version.
  609. * ROM version is derived from last two bytes of soc_ver.
  610. */
  611. if (soc_type == QCA_WCN3988)
  612. rom_ver = ((soc_ver & 0x00000f00) >> 0x05) | (soc_ver & 0x0000000f);
  613. else
  614. rom_ver = ((soc_ver & 0x00000f00) >> 0x04) | (soc_ver & 0x0000000f);
  615. if (soc_type == QCA_WCN6750)
  616. qca_send_patch_config_cmd(hdev);
  617. /* Download rampatch file */
  618. config.type = TLV_TYPE_PATCH;
  619. switch (soc_type) {
  620. case QCA_WCN3990:
  621. case QCA_WCN3991:
  622. case QCA_WCN3998:
  623. snprintf(config.fwname, sizeof(config.fwname),
  624. "qca/crbtfw%02x.tlv", rom_ver);
  625. break;
  626. case QCA_WCN3988:
  627. snprintf(config.fwname, sizeof(config.fwname),
  628. "qca/apbtfw%02x.tlv", rom_ver);
  629. break;
  630. case QCA_QCA2066:
  631. snprintf(config.fwname, sizeof(config.fwname),
  632. "qca/hpbtfw%02x.tlv", rom_ver);
  633. break;
  634. case QCA_QCA6390:
  635. snprintf(config.fwname, sizeof(config.fwname),
  636. "qca/htbtfw%02x.tlv", rom_ver);
  637. break;
  638. case QCA_WCN6750:
  639. /* Choose mbn file by default.If mbn file is not found
  640. * then choose tlv file
  641. */
  642. config.type = ELF_TYPE_PATCH;
  643. snprintf(config.fwname, sizeof(config.fwname),
  644. "qca/msbtfw%02x.mbn", rom_ver);
  645. break;
  646. case QCA_WCN6855:
  647. snprintf(config.fwname, sizeof(config.fwname),
  648. "qca/hpbtfw%02x.tlv", rom_ver);
  649. break;
  650. case QCA_WCN7850:
  651. snprintf(config.fwname, sizeof(config.fwname),
  652. "qca/hmtbtfw%02x.tlv", rom_ver);
  653. break;
  654. default:
  655. snprintf(config.fwname, sizeof(config.fwname),
  656. "qca/rampatch_%08x.bin", soc_ver);
  657. }
  658. err = qca_download_firmware(hdev, &config, soc_type, rom_ver);
  659. if (err < 0) {
  660. bt_dev_err(hdev, "QCA Failed to download patch (%d)", err);
  661. return err;
  662. }
  663. /* Give the controller some time to get ready to receive the NVM */
  664. msleep(10);
  665. if (soc_type == QCA_QCA2066 || soc_type == QCA_WCN7850)
  666. qca_read_fw_board_id(hdev, &boardid);
  667. /* Download NVM configuration */
  668. config.type = TLV_TYPE_NVM;
  669. if (firmware_name) {
  670. snprintf(config.fwname, sizeof(config.fwname),
  671. "qca/%s", firmware_name);
  672. } else {
  673. switch (soc_type) {
  674. case QCA_WCN3990:
  675. case QCA_WCN3991:
  676. case QCA_WCN3998:
  677. if (le32_to_cpu(ver.soc_id) == QCA_WCN3991_SOC_ID) {
  678. snprintf(config.fwname, sizeof(config.fwname),
  679. "qca/crnv%02xu.bin", rom_ver);
  680. } else {
  681. snprintf(config.fwname, sizeof(config.fwname),
  682. "qca/crnv%02x.bin", rom_ver);
  683. }
  684. break;
  685. case QCA_WCN3988:
  686. snprintf(config.fwname, sizeof(config.fwname),
  687. "qca/apnv%02x.bin", rom_ver);
  688. break;
  689. case QCA_QCA2066:
  690. qca_generate_hsp_nvm_name(config.fwname,
  691. sizeof(config.fwname), ver, rom_ver, boardid);
  692. break;
  693. case QCA_QCA6390:
  694. snprintf(config.fwname, sizeof(config.fwname),
  695. "qca/htnv%02x.bin", rom_ver);
  696. break;
  697. case QCA_WCN6750:
  698. snprintf(config.fwname, sizeof(config.fwname),
  699. "qca/msnv%02x.bin", rom_ver);
  700. break;
  701. case QCA_WCN6855:
  702. snprintf(config.fwname, sizeof(config.fwname),
  703. "qca/hpnv%02x.bin", rom_ver);
  704. break;
  705. case QCA_WCN7850:
  706. qca_get_nvm_name_generic(&config, "hmt", rom_ver, boardid);
  707. break;
  708. default:
  709. snprintf(config.fwname, sizeof(config.fwname),
  710. "qca/nvm_%08x.bin", soc_ver);
  711. }
  712. }
  713. err = qca_download_firmware(hdev, &config, soc_type, rom_ver);
  714. if (err < 0) {
  715. bt_dev_err(hdev, "QCA Failed to download NVM (%d)", err);
  716. return err;
  717. }
  718. switch (soc_type) {
  719. case QCA_WCN3991:
  720. case QCA_QCA2066:
  721. case QCA_QCA6390:
  722. case QCA_WCN6750:
  723. case QCA_WCN6855:
  724. case QCA_WCN7850:
  725. err = qca_disable_soc_logging(hdev);
  726. if (err < 0)
  727. return err;
  728. break;
  729. default:
  730. break;
  731. }
  732. /* WCN399x and WCN6750 supports the Microsoft vendor extension with 0xFD70 as the
  733. * VsMsftOpCode.
  734. */
  735. switch (soc_type) {
  736. case QCA_WCN3988:
  737. case QCA_WCN3990:
  738. case QCA_WCN3991:
  739. case QCA_WCN3998:
  740. case QCA_WCN6750:
  741. hci_set_msft_opcode(hdev, 0xFD70);
  742. break;
  743. default:
  744. break;
  745. }
  746. /* Perform HCI reset */
  747. err = qca_send_reset(hdev);
  748. if (err < 0) {
  749. bt_dev_err(hdev, "QCA Failed to run HCI_RESET (%d)", err);
  750. return err;
  751. }
  752. switch (soc_type) {
  753. case QCA_WCN3991:
  754. case QCA_WCN6750:
  755. case QCA_WCN6855:
  756. case QCA_WCN7850:
  757. /* get fw build info */
  758. err = qca_read_fw_build_info(hdev);
  759. if (err < 0)
  760. return err;
  761. break;
  762. default:
  763. break;
  764. }
  765. err = qca_check_bdaddr(hdev, &config);
  766. if (err)
  767. return err;
  768. bt_dev_info(hdev, "QCA setup on UART is completed");
  769. return 0;
  770. }
  771. EXPORT_SYMBOL_GPL(qca_uart_setup);
  772. int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
  773. {
  774. bdaddr_t bdaddr_swapped;
  775. struct sk_buff *skb;
  776. int err;
  777. baswap(&bdaddr_swapped, bdaddr);
  778. skb = __hci_cmd_sync_ev(hdev, EDL_WRITE_BD_ADDR_OPCODE, 6,
  779. &bdaddr_swapped, HCI_EV_VENDOR,
  780. HCI_INIT_TIMEOUT);
  781. if (IS_ERR(skb)) {
  782. err = PTR_ERR(skb);
  783. bt_dev_err(hdev, "QCA Change address cmd failed (%d)", err);
  784. return err;
  785. }
  786. kfree_skb(skb);
  787. return 0;
  788. }
  789. EXPORT_SYMBOL_GPL(qca_set_bdaddr);
  790. MODULE_AUTHOR("Ben Young Tae Kim <ytkim@qca.qualcomm.com>");
  791. MODULE_DESCRIPTION("Bluetooth support for Qualcomm Atheros family");
  792. MODULE_LICENSE("GPL");