amd-rng.c 4.8 KB

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  1. /*
  2. * RNG driver for AMD RNGs
  3. *
  4. * Copyright 2005 (c) MontaVista Software, Inc.
  5. *
  6. * with the majority of the code coming from:
  7. *
  8. * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
  9. * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
  10. *
  11. * derived from
  12. *
  13. * Hardware driver for the AMD 768 Random Number Generator (RNG)
  14. * (c) Copyright 2001 Red Hat Inc
  15. *
  16. * derived from
  17. *
  18. * Hardware driver for Intel i810 Random Number Generator (RNG)
  19. * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
  20. * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
  21. *
  22. * This file is licensed under the terms of the GNU General Public
  23. * License version 2. This program is licensed "as is" without any
  24. * warranty of any kind, whether express or implied.
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/hw_random.h>
  28. #include <linux/io.h>
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/pci.h>
  32. #define DRV_NAME "AMD768-HWRNG"
  33. #define RNGDATA 0x00
  34. #define RNGDONE 0x04
  35. #define PMBASE_OFFSET 0xF0
  36. #define PMBASE_SIZE 8
  37. /*
  38. * Data for PCI driver interface
  39. *
  40. * This data only exists for exporting the supported
  41. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  42. * register a pci_driver, because someone else might one day
  43. * want to register another driver on the same PCI id.
  44. */
  45. static const struct pci_device_id pci_tbl[] = {
  46. { PCI_VDEVICE(AMD, 0x7443), 0, },
  47. { PCI_VDEVICE(AMD, 0x746b), 0, },
  48. { 0, }, /* terminate list */
  49. };
  50. MODULE_DEVICE_TABLE(pci, pci_tbl);
  51. struct amd768_priv {
  52. void __iomem *iobase;
  53. struct pci_dev *pcidev;
  54. u32 pmbase;
  55. };
  56. static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
  57. {
  58. u32 *data = buf;
  59. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  60. size_t read = 0;
  61. /* We will wait at maximum one time per read */
  62. int timeout = max / 4 + 1;
  63. /*
  64. * RNG data is available when RNGDONE is set to 1
  65. * New random numbers are generated approximately 128 microseconds
  66. * after RNGDATA is read
  67. */
  68. while (read < max) {
  69. if (ioread32(priv->iobase + RNGDONE) == 0) {
  70. if (wait) {
  71. /* Delay given by datasheet */
  72. usleep_range(128, 196);
  73. if (timeout-- == 0)
  74. return read;
  75. } else {
  76. return 0;
  77. }
  78. } else {
  79. *data = ioread32(priv->iobase + RNGDATA);
  80. data++;
  81. read += 4;
  82. }
  83. }
  84. return read;
  85. }
  86. static int amd_rng_init(struct hwrng *rng)
  87. {
  88. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  89. u8 rnen;
  90. pci_read_config_byte(priv->pcidev, 0x40, &rnen);
  91. rnen |= BIT(7); /* RNG on */
  92. pci_write_config_byte(priv->pcidev, 0x40, rnen);
  93. pci_read_config_byte(priv->pcidev, 0x41, &rnen);
  94. rnen |= BIT(7); /* PMIO enable */
  95. pci_write_config_byte(priv->pcidev, 0x41, rnen);
  96. return 0;
  97. }
  98. static void amd_rng_cleanup(struct hwrng *rng)
  99. {
  100. struct amd768_priv *priv = (struct amd768_priv *)rng->priv;
  101. u8 rnen;
  102. pci_read_config_byte(priv->pcidev, 0x40, &rnen);
  103. rnen &= ~BIT(7); /* RNG off */
  104. pci_write_config_byte(priv->pcidev, 0x40, rnen);
  105. }
  106. static struct hwrng amd_rng = {
  107. .name = "amd",
  108. .init = amd_rng_init,
  109. .cleanup = amd_rng_cleanup,
  110. .read = amd_rng_read,
  111. };
  112. static int __init amd_rng_mod_init(void)
  113. {
  114. int err;
  115. struct pci_dev *pdev = NULL;
  116. const struct pci_device_id *ent;
  117. u32 pmbase;
  118. struct amd768_priv *priv;
  119. for_each_pci_dev(pdev) {
  120. ent = pci_match_id(pci_tbl, pdev);
  121. if (ent)
  122. goto found;
  123. }
  124. /* Device not found. */
  125. return -ENODEV;
  126. found:
  127. err = pci_read_config_dword(pdev, 0x58, &pmbase);
  128. if (err) {
  129. err = pcibios_err_to_errno(err);
  130. goto put_dev;
  131. }
  132. pmbase &= 0x0000FF00;
  133. if (pmbase == 0) {
  134. err = -EIO;
  135. goto put_dev;
  136. }
  137. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  138. if (!priv) {
  139. err = -ENOMEM;
  140. goto put_dev;
  141. }
  142. if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
  143. dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
  144. pmbase + 0xF0);
  145. err = -EBUSY;
  146. goto out;
  147. }
  148. priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  149. if (!priv->iobase) {
  150. pr_err(DRV_NAME "Cannot map ioport\n");
  151. err = -EINVAL;
  152. goto err_iomap;
  153. }
  154. amd_rng.priv = (unsigned long)priv;
  155. priv->pmbase = pmbase;
  156. priv->pcidev = pdev;
  157. pr_info(DRV_NAME " detected\n");
  158. err = hwrng_register(&amd_rng);
  159. if (err) {
  160. pr_err(DRV_NAME " registering failed (%d)\n", err);
  161. goto err_hwrng;
  162. }
  163. return 0;
  164. err_hwrng:
  165. ioport_unmap(priv->iobase);
  166. err_iomap:
  167. release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  168. out:
  169. kfree(priv);
  170. put_dev:
  171. pci_dev_put(pdev);
  172. return err;
  173. }
  174. static void __exit amd_rng_mod_exit(void)
  175. {
  176. struct amd768_priv *priv;
  177. priv = (struct amd768_priv *)amd_rng.priv;
  178. hwrng_unregister(&amd_rng);
  179. ioport_unmap(priv->iobase);
  180. release_region(priv->pmbase + PMBASE_OFFSET, PMBASE_SIZE);
  181. pci_dev_put(priv->pcidev);
  182. kfree(priv);
  183. }
  184. module_init(amd_rng_mod_init);
  185. module_exit(amd_rng_mod_exit);
  186. MODULE_AUTHOR("The Linux Kernel team");
  187. MODULE_DESCRIPTION("H/W RNG driver for AMD chipsets");
  188. MODULE_LICENSE("GPL");