tlclk.c 23 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/init.h>
  31. #include <linux/kernel.h> /* printk() */
  32. #include <linux/fs.h> /* everything... */
  33. #include <linux/errno.h> /* error codes */
  34. #include <linux/sched.h>
  35. #include <linux/slab.h>
  36. #include <linux/ioport.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/mutex.h>
  40. #include <linux/timer.h>
  41. #include <linux/sysfs.h>
  42. #include <linux/device.h>
  43. #include <linux/miscdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <asm/io.h> /* inb/outb */
  46. #include <linux/uaccess.h>
  47. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  48. MODULE_DESCRIPTION("Telecom Clock driver for Intel NetStructure(tm) MPCBL0010");
  49. MODULE_LICENSE("GPL");
  50. /*Hardware Reset of the PLL */
  51. #define RESET_ON 0x00
  52. #define RESET_OFF 0x01
  53. /* MODE SELECT */
  54. #define NORMAL_MODE 0x00
  55. #define HOLDOVER_MODE 0x10
  56. #define FREERUN_MODE 0x20
  57. /* FILTER SELECT */
  58. #define FILTER_6HZ 0x04
  59. #define FILTER_12HZ 0x00
  60. /* SELECT REFERENCE FREQUENCY */
  61. #define REF_CLK1_8kHz 0x00
  62. #define REF_CLK2_19_44MHz 0x02
  63. /* Select primary or secondary redundant clock */
  64. #define PRIMARY_CLOCK 0x00
  65. #define SECONDARY_CLOCK 0x01
  66. /* CLOCK TRANSMISSION DEFINE */
  67. #define CLK_8kHz 0xff
  68. #define CLK_16_384MHz 0xfb
  69. #define CLK_1_544MHz 0x00
  70. #define CLK_2_048MHz 0x01
  71. #define CLK_4_096MHz 0x02
  72. #define CLK_6_312MHz 0x03
  73. #define CLK_8_192MHz 0x04
  74. #define CLK_19_440MHz 0x06
  75. #define CLK_8_592MHz 0x08
  76. #define CLK_11_184MHz 0x09
  77. #define CLK_34_368MHz 0x0b
  78. #define CLK_44_736MHz 0x0a
  79. /* RECEIVED REFERENCE */
  80. #define AMC_B1 0
  81. #define AMC_B2 1
  82. /* HARDWARE SWITCHING DEFINE */
  83. #define HW_ENABLE 0x80
  84. #define HW_DISABLE 0x00
  85. /* HARDWARE SWITCHING MODE DEFINE */
  86. #define PLL_HOLDOVER 0x40
  87. #define LOST_CLOCK 0x00
  88. /* ALARMS DEFINE */
  89. #define UNLOCK_MASK 0x10
  90. #define HOLDOVER_MASK 0x20
  91. #define SEC_LOST_MASK 0x40
  92. #define PRI_LOST_MASK 0x80
  93. /* INTERRUPT CAUSE DEFINE */
  94. #define PRI_LOS_01_MASK 0x01
  95. #define PRI_LOS_10_MASK 0x02
  96. #define SEC_LOS_01_MASK 0x04
  97. #define SEC_LOS_10_MASK 0x08
  98. #define HOLDOVER_01_MASK 0x10
  99. #define HOLDOVER_10_MASK 0x20
  100. #define UNLOCK_01_MASK 0x40
  101. #define UNLOCK_10_MASK 0x80
  102. struct tlclk_alarms {
  103. __u32 lost_clocks;
  104. __u32 lost_primary_clock;
  105. __u32 lost_secondary_clock;
  106. __u32 primary_clock_back;
  107. __u32 secondary_clock_back;
  108. __u32 switchover_primary;
  109. __u32 switchover_secondary;
  110. __u32 pll_holdover;
  111. __u32 pll_end_holdover;
  112. __u32 pll_lost_sync;
  113. __u32 pll_sync;
  114. };
  115. /* Telecom clock I/O register definition */
  116. #define TLCLK_BASE 0xa08
  117. #define TLCLK_REG0 TLCLK_BASE
  118. #define TLCLK_REG1 (TLCLK_BASE+1)
  119. #define TLCLK_REG2 (TLCLK_BASE+2)
  120. #define TLCLK_REG3 (TLCLK_BASE+3)
  121. #define TLCLK_REG4 (TLCLK_BASE+4)
  122. #define TLCLK_REG5 (TLCLK_BASE+5)
  123. #define TLCLK_REG6 (TLCLK_BASE+6)
  124. #define TLCLK_REG7 (TLCLK_BASE+7)
  125. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  126. /* 0 = Dynamic allocation of the major device number */
  127. #define TLCLK_MAJOR 0
  128. /* sysfs interface definition:
  129. Upon loading the driver will create a sysfs directory under
  130. /sys/devices/platform/telco_clock.
  131. This directory exports the following interfaces. There operation is
  132. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  133. alarms :
  134. current_ref :
  135. received_ref_clk3a :
  136. received_ref_clk3b :
  137. enable_clk3a_output :
  138. enable_clk3b_output :
  139. enable_clka0_output :
  140. enable_clka1_output :
  141. enable_clkb0_output :
  142. enable_clkb1_output :
  143. filter_select :
  144. hardware_switching :
  145. hardware_switching_mode :
  146. telclock_version :
  147. mode_select :
  148. refalign :
  149. reset :
  150. select_amcb1_transmit_clock :
  151. select_amcb2_transmit_clock :
  152. select_redundant_clock :
  153. select_ref_frequency :
  154. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  155. has the same effect as echo 0x99 > refalign.
  156. */
  157. static unsigned int telclk_interrupt;
  158. static int int_events; /* Event that generate a interrupt */
  159. static int got_event; /* if events processing have been done */
  160. static void switchover_timeout(struct timer_list *t);
  161. static struct timer_list switchover_timer;
  162. static unsigned long tlclk_timer_data;
  163. static struct tlclk_alarms *alarm_events;
  164. static DEFINE_SPINLOCK(event_lock);
  165. static int tlclk_major = TLCLK_MAJOR;
  166. static irqreturn_t tlclk_interrupt(int irq, void *dev_id);
  167. static DECLARE_WAIT_QUEUE_HEAD(wq);
  168. static unsigned long useflags;
  169. static DEFINE_MUTEX(tlclk_mutex);
  170. static int tlclk_open(struct inode *inode, struct file *filp)
  171. {
  172. int result;
  173. mutex_lock(&tlclk_mutex);
  174. if (test_and_set_bit(0, &useflags)) {
  175. result = -EBUSY;
  176. /* this legacy device is always one per system and it doesn't
  177. * know how to handle multiple concurrent clients.
  178. */
  179. goto out;
  180. }
  181. /* Make sure there is no interrupt pending while
  182. * initialising interrupt handler */
  183. inb(TLCLK_REG6);
  184. /* This device is wired through the FPGA IO space of the ATCA blade
  185. * we can't share this IRQ */
  186. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  187. 0, "telco_clock", tlclk_interrupt);
  188. if (result == -EBUSY)
  189. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  190. else
  191. inb(TLCLK_REG6); /* Clear interrupt events */
  192. out:
  193. mutex_unlock(&tlclk_mutex);
  194. return result;
  195. }
  196. static int tlclk_release(struct inode *inode, struct file *filp)
  197. {
  198. free_irq(telclk_interrupt, tlclk_interrupt);
  199. clear_bit(0, &useflags);
  200. return 0;
  201. }
  202. static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  203. loff_t *f_pos)
  204. {
  205. if (count < sizeof(struct tlclk_alarms))
  206. return -EIO;
  207. if (mutex_lock_interruptible(&tlclk_mutex))
  208. return -EINTR;
  209. wait_event_interruptible(wq, got_event);
  210. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms))) {
  211. mutex_unlock(&tlclk_mutex);
  212. return -EFAULT;
  213. }
  214. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  215. got_event = 0;
  216. mutex_unlock(&tlclk_mutex);
  217. return sizeof(struct tlclk_alarms);
  218. }
  219. static const struct file_operations tlclk_fops = {
  220. .read = tlclk_read,
  221. .open = tlclk_open,
  222. .release = tlclk_release,
  223. .llseek = noop_llseek,
  224. };
  225. static struct miscdevice tlclk_miscdev = {
  226. .minor = MISC_DYNAMIC_MINOR,
  227. .name = "telco_clock",
  228. .fops = &tlclk_fops,
  229. };
  230. static ssize_t show_current_ref(struct device *d,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. unsigned long ret_val;
  234. unsigned long flags;
  235. spin_lock_irqsave(&event_lock, flags);
  236. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  237. spin_unlock_irqrestore(&event_lock, flags);
  238. return sprintf(buf, "0x%lX\n", ret_val);
  239. }
  240. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  241. static ssize_t show_telclock_version(struct device *d,
  242. struct device_attribute *attr, char *buf)
  243. {
  244. unsigned long ret_val;
  245. unsigned long flags;
  246. spin_lock_irqsave(&event_lock, flags);
  247. ret_val = inb(TLCLK_REG5);
  248. spin_unlock_irqrestore(&event_lock, flags);
  249. return sprintf(buf, "0x%lX\n", ret_val);
  250. }
  251. static DEVICE_ATTR(telclock_version, S_IRUGO,
  252. show_telclock_version, NULL);
  253. static ssize_t show_alarms(struct device *d,
  254. struct device_attribute *attr, char *buf)
  255. {
  256. unsigned long ret_val;
  257. unsigned long flags;
  258. spin_lock_irqsave(&event_lock, flags);
  259. ret_val = (inb(TLCLK_REG2) & 0xf0);
  260. spin_unlock_irqrestore(&event_lock, flags);
  261. return sprintf(buf, "0x%lX\n", ret_val);
  262. }
  263. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  264. static ssize_t store_received_ref_clk3a(struct device *d,
  265. struct device_attribute *attr, const char *buf, size_t count)
  266. {
  267. unsigned long tmp;
  268. unsigned char val;
  269. unsigned long flags;
  270. sscanf(buf, "%lX", &tmp);
  271. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  272. val = (unsigned char)tmp;
  273. spin_lock_irqsave(&event_lock, flags);
  274. SET_PORT_BITS(TLCLK_REG1, 0xef, val);
  275. spin_unlock_irqrestore(&event_lock, flags);
  276. return strnlen(buf, count);
  277. }
  278. static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
  279. store_received_ref_clk3a);
  280. static ssize_t store_received_ref_clk3b(struct device *d,
  281. struct device_attribute *attr, const char *buf, size_t count)
  282. {
  283. unsigned long tmp;
  284. unsigned char val;
  285. unsigned long flags;
  286. sscanf(buf, "%lX", &tmp);
  287. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  288. val = (unsigned char)tmp;
  289. spin_lock_irqsave(&event_lock, flags);
  290. SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);
  291. spin_unlock_irqrestore(&event_lock, flags);
  292. return strnlen(buf, count);
  293. }
  294. static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
  295. store_received_ref_clk3b);
  296. static ssize_t store_enable_clk3b_output(struct device *d,
  297. struct device_attribute *attr, const char *buf, size_t count)
  298. {
  299. unsigned long tmp;
  300. unsigned char val;
  301. unsigned long flags;
  302. sscanf(buf, "%lX", &tmp);
  303. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  304. val = (unsigned char)tmp;
  305. spin_lock_irqsave(&event_lock, flags);
  306. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  307. spin_unlock_irqrestore(&event_lock, flags);
  308. return strnlen(buf, count);
  309. }
  310. static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
  311. store_enable_clk3b_output);
  312. static ssize_t store_enable_clk3a_output(struct device *d,
  313. struct device_attribute *attr, const char *buf, size_t count)
  314. {
  315. unsigned long flags;
  316. unsigned long tmp;
  317. unsigned char val;
  318. sscanf(buf, "%lX", &tmp);
  319. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  320. val = (unsigned char)tmp;
  321. spin_lock_irqsave(&event_lock, flags);
  322. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  323. spin_unlock_irqrestore(&event_lock, flags);
  324. return strnlen(buf, count);
  325. }
  326. static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
  327. store_enable_clk3a_output);
  328. static ssize_t store_enable_clkb1_output(struct device *d,
  329. struct device_attribute *attr, const char *buf, size_t count)
  330. {
  331. unsigned long flags;
  332. unsigned long tmp;
  333. unsigned char val;
  334. sscanf(buf, "%lX", &tmp);
  335. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  336. val = (unsigned char)tmp;
  337. spin_lock_irqsave(&event_lock, flags);
  338. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  339. spin_unlock_irqrestore(&event_lock, flags);
  340. return strnlen(buf, count);
  341. }
  342. static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
  343. store_enable_clkb1_output);
  344. static ssize_t store_enable_clka1_output(struct device *d,
  345. struct device_attribute *attr, const char *buf, size_t count)
  346. {
  347. unsigned long flags;
  348. unsigned long tmp;
  349. unsigned char val;
  350. sscanf(buf, "%lX", &tmp);
  351. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  352. val = (unsigned char)tmp;
  353. spin_lock_irqsave(&event_lock, flags);
  354. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  355. spin_unlock_irqrestore(&event_lock, flags);
  356. return strnlen(buf, count);
  357. }
  358. static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
  359. store_enable_clka1_output);
  360. static ssize_t store_enable_clkb0_output(struct device *d,
  361. struct device_attribute *attr, const char *buf, size_t count)
  362. {
  363. unsigned long flags;
  364. unsigned long tmp;
  365. unsigned char val;
  366. sscanf(buf, "%lX", &tmp);
  367. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  368. val = (unsigned char)tmp;
  369. spin_lock_irqsave(&event_lock, flags);
  370. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  371. spin_unlock_irqrestore(&event_lock, flags);
  372. return strnlen(buf, count);
  373. }
  374. static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
  375. store_enable_clkb0_output);
  376. static ssize_t store_enable_clka0_output(struct device *d,
  377. struct device_attribute *attr, const char *buf, size_t count)
  378. {
  379. unsigned long flags;
  380. unsigned long tmp;
  381. unsigned char val;
  382. sscanf(buf, "%lX", &tmp);
  383. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  384. val = (unsigned char)tmp;
  385. spin_lock_irqsave(&event_lock, flags);
  386. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  387. spin_unlock_irqrestore(&event_lock, flags);
  388. return strnlen(buf, count);
  389. }
  390. static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
  391. store_enable_clka0_output);
  392. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  393. struct device_attribute *attr, const char *buf, size_t count)
  394. {
  395. unsigned long flags;
  396. unsigned long tmp;
  397. unsigned char val;
  398. sscanf(buf, "%lX", &tmp);
  399. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  400. val = (unsigned char)tmp;
  401. spin_lock_irqsave(&event_lock, flags);
  402. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  403. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  404. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  405. } else if (val >= CLK_8_592MHz) {
  406. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  407. switch (val) {
  408. case CLK_8_592MHz:
  409. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  410. break;
  411. case CLK_11_184MHz:
  412. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  413. break;
  414. case CLK_34_368MHz:
  415. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  416. break;
  417. case CLK_44_736MHz:
  418. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  419. break;
  420. }
  421. } else {
  422. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  423. }
  424. spin_unlock_irqrestore(&event_lock, flags);
  425. return strnlen(buf, count);
  426. }
  427. static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  428. store_select_amcb2_transmit_clock);
  429. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  430. struct device_attribute *attr, const char *buf, size_t count)
  431. {
  432. unsigned long tmp;
  433. unsigned char val;
  434. unsigned long flags;
  435. sscanf(buf, "%lX", &tmp);
  436. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  437. val = (unsigned char)tmp;
  438. spin_lock_irqsave(&event_lock, flags);
  439. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  440. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  441. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  442. } else if (val >= CLK_8_592MHz) {
  443. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  444. switch (val) {
  445. case CLK_8_592MHz:
  446. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  447. break;
  448. case CLK_11_184MHz:
  449. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  450. break;
  451. case CLK_34_368MHz:
  452. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  453. break;
  454. case CLK_44_736MHz:
  455. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  456. break;
  457. }
  458. } else {
  459. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  460. }
  461. spin_unlock_irqrestore(&event_lock, flags);
  462. return strnlen(buf, count);
  463. }
  464. static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  465. store_select_amcb1_transmit_clock);
  466. static ssize_t store_select_redundant_clock(struct device *d,
  467. struct device_attribute *attr, const char *buf, size_t count)
  468. {
  469. unsigned long tmp;
  470. unsigned char val;
  471. unsigned long flags;
  472. sscanf(buf, "%lX", &tmp);
  473. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  474. val = (unsigned char)tmp;
  475. spin_lock_irqsave(&event_lock, flags);
  476. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  477. spin_unlock_irqrestore(&event_lock, flags);
  478. return strnlen(buf, count);
  479. }
  480. static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
  481. store_select_redundant_clock);
  482. static ssize_t store_select_ref_frequency(struct device *d,
  483. struct device_attribute *attr, const char *buf, size_t count)
  484. {
  485. unsigned long tmp;
  486. unsigned char val;
  487. unsigned long flags;
  488. sscanf(buf, "%lX", &tmp);
  489. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  490. val = (unsigned char)tmp;
  491. spin_lock_irqsave(&event_lock, flags);
  492. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  493. spin_unlock_irqrestore(&event_lock, flags);
  494. return strnlen(buf, count);
  495. }
  496. static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
  497. store_select_ref_frequency);
  498. static ssize_t store_filter_select(struct device *d,
  499. struct device_attribute *attr, const char *buf, size_t count)
  500. {
  501. unsigned long tmp;
  502. unsigned char val;
  503. unsigned long flags;
  504. sscanf(buf, "%lX", &tmp);
  505. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  506. val = (unsigned char)tmp;
  507. spin_lock_irqsave(&event_lock, flags);
  508. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  509. spin_unlock_irqrestore(&event_lock, flags);
  510. return strnlen(buf, count);
  511. }
  512. static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
  513. static ssize_t store_hardware_switching_mode(struct device *d,
  514. struct device_attribute *attr, const char *buf, size_t count)
  515. {
  516. unsigned long tmp;
  517. unsigned char val;
  518. unsigned long flags;
  519. sscanf(buf, "%lX", &tmp);
  520. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  521. val = (unsigned char)tmp;
  522. spin_lock_irqsave(&event_lock, flags);
  523. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  524. spin_unlock_irqrestore(&event_lock, flags);
  525. return strnlen(buf, count);
  526. }
  527. static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
  528. store_hardware_switching_mode);
  529. static ssize_t store_hardware_switching(struct device *d,
  530. struct device_attribute *attr, const char *buf, size_t count)
  531. {
  532. unsigned long tmp;
  533. unsigned char val;
  534. unsigned long flags;
  535. sscanf(buf, "%lX", &tmp);
  536. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  537. val = (unsigned char)tmp;
  538. spin_lock_irqsave(&event_lock, flags);
  539. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  540. spin_unlock_irqrestore(&event_lock, flags);
  541. return strnlen(buf, count);
  542. }
  543. static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
  544. store_hardware_switching);
  545. static ssize_t store_refalign (struct device *d,
  546. struct device_attribute *attr, const char *buf, size_t count)
  547. {
  548. unsigned long tmp;
  549. unsigned long flags;
  550. sscanf(buf, "%lX", &tmp);
  551. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  552. spin_lock_irqsave(&event_lock, flags);
  553. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  554. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  555. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  556. spin_unlock_irqrestore(&event_lock, flags);
  557. return strnlen(buf, count);
  558. }
  559. static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
  560. static ssize_t store_mode_select (struct device *d,
  561. struct device_attribute *attr, const char *buf, size_t count)
  562. {
  563. unsigned long tmp;
  564. unsigned char val;
  565. unsigned long flags;
  566. sscanf(buf, "%lX", &tmp);
  567. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  568. val = (unsigned char)tmp;
  569. spin_lock_irqsave(&event_lock, flags);
  570. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  571. spin_unlock_irqrestore(&event_lock, flags);
  572. return strnlen(buf, count);
  573. }
  574. static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
  575. static ssize_t store_reset (struct device *d,
  576. struct device_attribute *attr, const char *buf, size_t count)
  577. {
  578. unsigned long tmp;
  579. unsigned char val;
  580. unsigned long flags;
  581. sscanf(buf, "%lX", &tmp);
  582. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  583. val = (unsigned char)tmp;
  584. spin_lock_irqsave(&event_lock, flags);
  585. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  586. spin_unlock_irqrestore(&event_lock, flags);
  587. return strnlen(buf, count);
  588. }
  589. static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
  590. static struct attribute *tlclk_sysfs_entries[] = {
  591. &dev_attr_current_ref.attr,
  592. &dev_attr_telclock_version.attr,
  593. &dev_attr_alarms.attr,
  594. &dev_attr_received_ref_clk3a.attr,
  595. &dev_attr_received_ref_clk3b.attr,
  596. &dev_attr_enable_clk3a_output.attr,
  597. &dev_attr_enable_clk3b_output.attr,
  598. &dev_attr_enable_clkb1_output.attr,
  599. &dev_attr_enable_clka1_output.attr,
  600. &dev_attr_enable_clkb0_output.attr,
  601. &dev_attr_enable_clka0_output.attr,
  602. &dev_attr_select_amcb1_transmit_clock.attr,
  603. &dev_attr_select_amcb2_transmit_clock.attr,
  604. &dev_attr_select_redundant_clock.attr,
  605. &dev_attr_select_ref_frequency.attr,
  606. &dev_attr_filter_select.attr,
  607. &dev_attr_hardware_switching_mode.attr,
  608. &dev_attr_hardware_switching.attr,
  609. &dev_attr_refalign.attr,
  610. &dev_attr_mode_select.attr,
  611. &dev_attr_reset.attr,
  612. NULL
  613. };
  614. static const struct attribute_group tlclk_attribute_group = {
  615. .name = NULL, /* put in device directory */
  616. .attrs = tlclk_sysfs_entries,
  617. };
  618. static struct platform_device *tlclk_device;
  619. static int __init tlclk_init(void)
  620. {
  621. int ret;
  622. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  623. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  624. if (!alarm_events) {
  625. ret = -ENOMEM;
  626. goto out1;
  627. }
  628. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  629. if (ret < 0) {
  630. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  631. kfree(alarm_events);
  632. return ret;
  633. }
  634. tlclk_major = ret;
  635. /* Read telecom clock IRQ number (Set by BIOS) */
  636. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  637. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  638. TLCLK_BASE);
  639. ret = -EBUSY;
  640. goto out2;
  641. }
  642. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  643. printk(KERN_ERR "telclk_interrupt = 0x%x non-mcpbl0010 hw.\n",
  644. telclk_interrupt);
  645. ret = -ENXIO;
  646. goto out3;
  647. }
  648. timer_setup(&switchover_timer, switchover_timeout, 0);
  649. ret = misc_register(&tlclk_miscdev);
  650. if (ret < 0) {
  651. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  652. goto out3;
  653. }
  654. tlclk_device = platform_device_register_simple("telco_clock",
  655. -1, NULL, 0);
  656. if (IS_ERR(tlclk_device)) {
  657. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  658. ret = PTR_ERR(tlclk_device);
  659. goto out4;
  660. }
  661. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  662. &tlclk_attribute_group);
  663. if (ret) {
  664. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  665. goto out5;
  666. }
  667. return 0;
  668. out5:
  669. platform_device_unregister(tlclk_device);
  670. out4:
  671. misc_deregister(&tlclk_miscdev);
  672. out3:
  673. release_region(TLCLK_BASE, 8);
  674. out2:
  675. kfree(alarm_events);
  676. unregister_chrdev(tlclk_major, "telco_clock");
  677. out1:
  678. return ret;
  679. }
  680. static void __exit tlclk_cleanup(void)
  681. {
  682. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  683. platform_device_unregister(tlclk_device);
  684. misc_deregister(&tlclk_miscdev);
  685. unregister_chrdev(tlclk_major, "telco_clock");
  686. release_region(TLCLK_BASE, 8);
  687. del_timer_sync(&switchover_timer);
  688. kfree(alarm_events);
  689. }
  690. static void switchover_timeout(struct timer_list *unused)
  691. {
  692. unsigned long flags = tlclk_timer_data;
  693. if ((flags & 1)) {
  694. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  695. alarm_events->switchover_primary++;
  696. } else {
  697. if ((inb(TLCLK_REG1) & 0x08) != (flags & 0x08))
  698. alarm_events->switchover_secondary++;
  699. }
  700. /* Alarm processing is done, wake up read task */
  701. del_timer(&switchover_timer);
  702. got_event = 1;
  703. wake_up(&wq);
  704. }
  705. static irqreturn_t tlclk_interrupt(int irq, void *dev_id)
  706. {
  707. unsigned long flags;
  708. spin_lock_irqsave(&event_lock, flags);
  709. /* Read and clear interrupt events */
  710. int_events = inb(TLCLK_REG6);
  711. /* Primary_Los changed from 0 to 1 ? */
  712. if (int_events & PRI_LOS_01_MASK) {
  713. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  714. alarm_events->lost_clocks++;
  715. else
  716. alarm_events->lost_primary_clock++;
  717. }
  718. /* Primary_Los changed from 1 to 0 ? */
  719. if (int_events & PRI_LOS_10_MASK) {
  720. alarm_events->primary_clock_back++;
  721. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  722. }
  723. /* Secondary_Los changed from 0 to 1 ? */
  724. if (int_events & SEC_LOS_01_MASK) {
  725. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  726. alarm_events->lost_clocks++;
  727. else
  728. alarm_events->lost_secondary_clock++;
  729. }
  730. /* Secondary_Los changed from 1 to 0 ? */
  731. if (int_events & SEC_LOS_10_MASK) {
  732. alarm_events->secondary_clock_back++;
  733. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  734. }
  735. if (int_events & HOLDOVER_10_MASK)
  736. alarm_events->pll_end_holdover++;
  737. if (int_events & UNLOCK_01_MASK)
  738. alarm_events->pll_lost_sync++;
  739. if (int_events & UNLOCK_10_MASK)
  740. alarm_events->pll_sync++;
  741. /* Holdover changed from 0 to 1 ? */
  742. if (int_events & HOLDOVER_01_MASK) {
  743. alarm_events->pll_holdover++;
  744. /* TIMEOUT in ~10ms */
  745. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  746. tlclk_timer_data = inb(TLCLK_REG1);
  747. mod_timer(&switchover_timer, switchover_timer.expires);
  748. } else {
  749. got_event = 1;
  750. wake_up(&wq);
  751. }
  752. spin_unlock_irqrestore(&event_lock, flags);
  753. return IRQ_HANDLED;
  754. }
  755. module_init(tlclk_init);
  756. module_exit(tlclk_cleanup);