clk-h32mx.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * clk-h32mx.c
  4. *
  5. * Copyright (C) 2014 Atmel
  6. *
  7. * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/clkdev.h>
  11. #include <linux/clk/at91_pmc.h>
  12. #include <linux/of.h>
  13. #include <linux/regmap.h>
  14. #include <linux/mfd/syscon.h>
  15. #include "pmc.h"
  16. #define H32MX_MAX_FREQ 90000000
  17. struct clk_sama5d4_h32mx {
  18. struct clk_hw hw;
  19. struct regmap *regmap;
  20. };
  21. #define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
  22. static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
  23. unsigned long parent_rate)
  24. {
  25. struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
  26. unsigned int mckr;
  27. regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
  28. if (mckr & AT91_PMC_H32MXDIV)
  29. return parent_rate / 2;
  30. if (parent_rate > H32MX_MAX_FREQ)
  31. pr_warn("H32MX clock is too fast\n");
  32. return parent_rate;
  33. }
  34. static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
  35. unsigned long *parent_rate)
  36. {
  37. unsigned long div;
  38. if (rate > *parent_rate)
  39. return *parent_rate;
  40. div = *parent_rate / 2;
  41. if (rate < div)
  42. return div;
  43. if (rate - div < *parent_rate - rate)
  44. return div;
  45. return *parent_rate;
  46. }
  47. static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
  48. unsigned long parent_rate)
  49. {
  50. struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
  51. u32 mckr = 0;
  52. if (parent_rate != rate && (parent_rate / 2) != rate)
  53. return -EINVAL;
  54. if ((parent_rate / 2) == rate)
  55. mckr = AT91_PMC_H32MXDIV;
  56. regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
  57. AT91_PMC_H32MXDIV, mckr);
  58. return 0;
  59. }
  60. static const struct clk_ops h32mx_ops = {
  61. .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
  62. .round_rate = clk_sama5d4_h32mx_round_rate,
  63. .set_rate = clk_sama5d4_h32mx_set_rate,
  64. };
  65. struct clk_hw * __init
  66. at91_clk_register_h32mx(struct regmap *regmap, const char *name,
  67. const char *parent_name)
  68. {
  69. struct clk_sama5d4_h32mx *h32mxclk;
  70. struct clk_init_data init;
  71. int ret;
  72. h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
  73. if (!h32mxclk)
  74. return ERR_PTR(-ENOMEM);
  75. init.name = name;
  76. init.ops = &h32mx_ops;
  77. init.parent_names = parent_name ? &parent_name : NULL;
  78. init.num_parents = parent_name ? 1 : 0;
  79. init.flags = CLK_SET_RATE_GATE;
  80. h32mxclk->hw.init = &init;
  81. h32mxclk->regmap = regmap;
  82. ret = clk_hw_register(NULL, &h32mxclk->hw);
  83. if (ret) {
  84. kfree(h32mxclk);
  85. return ERR_PTR(ret);
  86. }
  87. return &h32mxclk->hw;
  88. }