clk-twl.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Clock driver for twl device.
  4. *
  5. * inspired by the driver for the Palmas device
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/mfd/twl.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #define VREG_STATE 2
  13. #define TWL6030_CFG_STATE_OFF 0x00
  14. #define TWL6030_CFG_STATE_ON 0x01
  15. #define TWL6030_CFG_STATE_MASK 0x03
  16. struct twl_clock_info {
  17. struct device *dev;
  18. u8 base;
  19. struct clk_hw hw;
  20. };
  21. static inline int
  22. twlclk_read(struct twl_clock_info *info, unsigned int slave_subgp,
  23. unsigned int offset)
  24. {
  25. u8 value;
  26. int status;
  27. status = twl_i2c_read_u8(slave_subgp, &value,
  28. info->base + offset);
  29. return (status < 0) ? status : value;
  30. }
  31. static inline int
  32. twlclk_write(struct twl_clock_info *info, unsigned int slave_subgp,
  33. unsigned int offset, u8 value)
  34. {
  35. return twl_i2c_write_u8(slave_subgp, value,
  36. info->base + offset);
  37. }
  38. static inline struct twl_clock_info *to_twl_clks_info(struct clk_hw *hw)
  39. {
  40. return container_of(hw, struct twl_clock_info, hw);
  41. }
  42. static unsigned long twl_clks_recalc_rate(struct clk_hw *hw,
  43. unsigned long parent_rate)
  44. {
  45. return 32768;
  46. }
  47. static int twl6032_clks_prepare(struct clk_hw *hw)
  48. {
  49. struct twl_clock_info *cinfo = to_twl_clks_info(hw);
  50. int ret;
  51. ret = twlclk_write(cinfo, TWL_MODULE_PM_RECEIVER, VREG_STATE,
  52. TWL6030_CFG_STATE_ON);
  53. if (ret < 0)
  54. dev_err(cinfo->dev, "clk prepare failed\n");
  55. return ret;
  56. }
  57. static void twl6032_clks_unprepare(struct clk_hw *hw)
  58. {
  59. struct twl_clock_info *cinfo = to_twl_clks_info(hw);
  60. int ret;
  61. ret = twlclk_write(cinfo, TWL_MODULE_PM_RECEIVER, VREG_STATE,
  62. TWL6030_CFG_STATE_OFF);
  63. if (ret < 0)
  64. dev_err(cinfo->dev, "clk unprepare failed\n");
  65. }
  66. static int twl6032_clks_is_prepared(struct clk_hw *hw)
  67. {
  68. struct twl_clock_info *cinfo = to_twl_clks_info(hw);
  69. int val;
  70. val = twlclk_read(cinfo, TWL_MODULE_PM_RECEIVER, VREG_STATE);
  71. if (val < 0) {
  72. dev_err(cinfo->dev, "clk read failed\n");
  73. return val;
  74. }
  75. val &= TWL6030_CFG_STATE_MASK;
  76. return val == TWL6030_CFG_STATE_ON;
  77. }
  78. static const struct clk_ops twl6032_clks_ops = {
  79. .prepare = twl6032_clks_prepare,
  80. .unprepare = twl6032_clks_unprepare,
  81. .is_prepared = twl6032_clks_is_prepared,
  82. .recalc_rate = twl_clks_recalc_rate,
  83. };
  84. struct twl_clks_data {
  85. struct clk_init_data init;
  86. u8 base;
  87. };
  88. static const struct twl_clks_data twl6032_clks[] = {
  89. {
  90. .init = {
  91. .name = "clk32kg",
  92. .ops = &twl6032_clks_ops,
  93. .flags = CLK_IGNORE_UNUSED,
  94. },
  95. .base = 0x8C,
  96. },
  97. {
  98. .init = {
  99. .name = "clk32kaudio",
  100. .ops = &twl6032_clks_ops,
  101. .flags = CLK_IGNORE_UNUSED,
  102. },
  103. .base = 0x8F,
  104. },
  105. {
  106. /* sentinel */
  107. }
  108. };
  109. static int twl_clks_probe(struct platform_device *pdev)
  110. {
  111. struct clk_hw_onecell_data *clk_data;
  112. const struct twl_clks_data *hw_data;
  113. struct twl_clock_info *cinfo;
  114. int ret;
  115. int i;
  116. int count;
  117. hw_data = twl6032_clks;
  118. for (count = 0; hw_data[count].init.name; count++)
  119. ;
  120. clk_data = devm_kzalloc(&pdev->dev,
  121. struct_size(clk_data, hws, count),
  122. GFP_KERNEL);
  123. if (!clk_data)
  124. return -ENOMEM;
  125. clk_data->num = count;
  126. cinfo = devm_kcalloc(&pdev->dev, count, sizeof(*cinfo), GFP_KERNEL);
  127. if (!cinfo)
  128. return -ENOMEM;
  129. for (i = 0; i < count; i++) {
  130. cinfo[i].base = hw_data[i].base;
  131. cinfo[i].dev = &pdev->dev;
  132. cinfo[i].hw.init = &hw_data[i].init;
  133. ret = devm_clk_hw_register(&pdev->dev, &cinfo[i].hw);
  134. if (ret) {
  135. return dev_err_probe(&pdev->dev, ret,
  136. "Fail to register clock %s\n",
  137. hw_data[i].init.name);
  138. }
  139. clk_data->hws[i] = &cinfo[i].hw;
  140. }
  141. ret = devm_of_clk_add_hw_provider(&pdev->dev,
  142. of_clk_hw_onecell_get, clk_data);
  143. if (ret < 0)
  144. return dev_err_probe(&pdev->dev, ret,
  145. "Fail to add clock driver\n");
  146. return 0;
  147. }
  148. static const struct platform_device_id twl_clks_id[] = {
  149. {
  150. .name = "twl6032-clk",
  151. }, {
  152. /* sentinel */
  153. }
  154. };
  155. MODULE_DEVICE_TABLE(platform, twl_clks_id);
  156. static struct platform_driver twl_clks_driver = {
  157. .driver = {
  158. .name = "twl-clk",
  159. },
  160. .probe = twl_clks_probe,
  161. .id_table = twl_clks_id,
  162. };
  163. module_platform_driver(twl_clks_driver);
  164. MODULE_DESCRIPTION("Clock driver for TWL Series Devices");
  165. MODULE_LICENSE("GPL");