clk-mt6795-vencsys.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2022 Collabora Ltd.
  4. * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  5. */
  6. #include <dt-bindings/clock/mediatek,mt6795-clk.h>
  7. #include <linux/module.h>
  8. #include <linux/platform_device.h>
  9. #include "clk-gate.h"
  10. #include "clk-mtk.h"
  11. static const struct mtk_gate_regs venc_cg_regs = {
  12. .set_ofs = 0x4,
  13. .clr_ofs = 0x8,
  14. .sta_ofs = 0x0,
  15. };
  16. #define GATE_VENC(_id, _name, _parent, _shift) \
  17. GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
  18. static const struct mtk_gate venc_clks[] = {
  19. GATE_VENC(CLK_VENC_LARB, "venc_larb", "venc_sel", 0),
  20. GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
  21. GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "venc_sel", 8),
  22. GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "venc_sel", 12),
  23. };
  24. static const struct mtk_clk_desc venc_desc = {
  25. .clks = venc_clks,
  26. .num_clks = ARRAY_SIZE(venc_clks),
  27. };
  28. static const struct of_device_id of_match_clk_mt6795_vencsys[] = {
  29. { .compatible = "mediatek,mt6795-vencsys", .data = &venc_desc },
  30. { /* sentinel */ }
  31. };
  32. MODULE_DEVICE_TABLE(of, of_match_clk_mt6795_vencsys);
  33. static struct platform_driver clk_mt6795_vencsys_drv = {
  34. .driver = {
  35. .name = "clk-mt6795-vencsys",
  36. .of_match_table = of_match_clk_mt6795_vencsys,
  37. },
  38. .probe = mtk_clk_simple_probe,
  39. .remove = mtk_clk_simple_remove,
  40. };
  41. module_platform_driver(clk_mt6795_vencsys_drv);
  42. MODULE_DESCRIPTION("MediaTek MT6795 vdecsys clocks driver");
  43. MODULE_LICENSE("GPL");