clk-mt7629-eth.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
  5. * Ryder Lee <ryder.lee@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include "clk-mtk.h"
  11. #include "clk-gate.h"
  12. #include <dt-bindings/clock/mt7629-clk.h>
  13. #define GATE_ETH(_id, _name, _parent, _shift) \
  14. GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
  15. static const struct mtk_gate_regs eth_cg_regs = {
  16. .set_ofs = 0x30,
  17. .clr_ofs = 0x30,
  18. .sta_ofs = 0x30,
  19. };
  20. static const struct mtk_gate eth_clks[] = {
  21. GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "eth2pll", 6),
  22. GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
  23. GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
  24. GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
  25. GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 16),
  26. };
  27. static const struct mtk_gate_regs sgmii_cg_regs = {
  28. .set_ofs = 0xE4,
  29. .clr_ofs = 0xE4,
  30. .sta_ofs = 0xE4,
  31. };
  32. #define GATE_SGMII(_id, _name, _parent, _shift) \
  33. GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
  34. static const struct mtk_gate sgmii_clks[2][4] = {
  35. {
  36. GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en",
  37. "ssusb_tx250m", 2),
  38. GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en",
  39. "ssusb_eq_rx250m", 3),
  40. GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
  41. "ssusb_cdr_ref", 4),
  42. GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
  43. "ssusb_cdr_fb", 5),
  44. }, {
  45. GATE_SGMII(CLK_SGMII_TX_EN, "sgmii_tx_en1",
  46. "ssusb_tx250m", 2),
  47. GATE_SGMII(CLK_SGMII_RX_EN, "sgmii_rx_en1",
  48. "ssusb_eq_rx250m", 3),
  49. GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref1",
  50. "ssusb_cdr_ref", 4),
  51. GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb1",
  52. "ssusb_cdr_fb", 5),
  53. }
  54. };
  55. static u16 rst_ofs[] = { 0x34, };
  56. static const struct mtk_clk_rst_desc clk_rst_desc = {
  57. .version = MTK_RST_SIMPLE,
  58. .rst_bank_ofs = rst_ofs,
  59. .rst_bank_nr = ARRAY_SIZE(rst_ofs),
  60. };
  61. static int clk_mt7629_ethsys_init(struct platform_device *pdev)
  62. {
  63. struct clk_hw_onecell_data *clk_data;
  64. struct device_node *node = pdev->dev.of_node;
  65. int r;
  66. clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
  67. if (!clk_data)
  68. return -ENOMEM;
  69. mtk_clk_register_gates(&pdev->dev, node, eth_clks,
  70. CLK_ETH_NR_CLK, clk_data);
  71. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  72. if (r)
  73. dev_err(&pdev->dev,
  74. "could not register clock provider: %s: %d\n",
  75. pdev->name, r);
  76. mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
  77. return r;
  78. }
  79. static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
  80. {
  81. struct clk_hw_onecell_data *clk_data;
  82. struct device_node *node = pdev->dev.of_node;
  83. static int id;
  84. int r;
  85. clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
  86. if (!clk_data)
  87. return -ENOMEM;
  88. mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++],
  89. CLK_SGMII_NR_CLK, clk_data);
  90. r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
  91. if (r)
  92. dev_err(&pdev->dev,
  93. "could not register clock provider: %s: %d\n",
  94. pdev->name, r);
  95. return r;
  96. }
  97. static const struct of_device_id of_match_clk_mt7629_eth[] = {
  98. {
  99. .compatible = "mediatek,mt7629-ethsys",
  100. .data = clk_mt7629_ethsys_init,
  101. }, {
  102. .compatible = "mediatek,mt7629-sgmiisys",
  103. .data = clk_mt7629_sgmiisys_init,
  104. }, {
  105. /* sentinel */
  106. }
  107. };
  108. MODULE_DEVICE_TABLE(of, of_match_clk_mt7629_eth);
  109. static int clk_mt7629_eth_probe(struct platform_device *pdev)
  110. {
  111. int (*clk_init)(struct platform_device *);
  112. int r;
  113. clk_init = of_device_get_match_data(&pdev->dev);
  114. if (!clk_init)
  115. return -EINVAL;
  116. r = clk_init(pdev);
  117. if (r)
  118. dev_err(&pdev->dev,
  119. "could not register clock provider: %s: %d\n",
  120. pdev->name, r);
  121. return r;
  122. }
  123. static struct platform_driver clk_mt7629_eth_drv = {
  124. .probe = clk_mt7629_eth_probe,
  125. .driver = {
  126. .name = "clk-mt7629-eth",
  127. .of_match_table = of_match_clk_mt7629_eth,
  128. },
  129. };
  130. builtin_platform_driver(clk_mt7629_eth_drv);
  131. MODULE_DESCRIPTION("MediaTek MT7629 Ethernet clocks driver");
  132. MODULE_LICENSE("GPL");