clk-mt8173-vdecsys.c 1.6 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Copyright (c) 2022 Collabora Ltd.
  5. * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  6. */
  7. #include <dt-bindings/clock/mt8173-clk.h>
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include "clk-gate.h"
  11. #include "clk-mtk.h"
  12. #define GATE_VDEC(_id, _name, _parent, _regs) \
  13. GATE_MTK(_id, _name, _parent, _regs, 0, \
  14. &mtk_clk_gate_ops_setclr_inv)
  15. static const struct mtk_gate_regs vdec0_cg_regs = {
  16. .set_ofs = 0x0000,
  17. .clr_ofs = 0x0004,
  18. .sta_ofs = 0x0000,
  19. };
  20. static const struct mtk_gate_regs vdec1_cg_regs = {
  21. .set_ofs = 0x0008,
  22. .clr_ofs = 0x000c,
  23. .sta_ofs = 0x0008,
  24. };
  25. static const struct mtk_gate vdec_clks[] = {
  26. GATE_DUMMY(CLK_DUMMY, "vdec_dummy"),
  27. GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", &vdec0_cg_regs),
  28. GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", &vdec1_cg_regs),
  29. };
  30. static const struct mtk_clk_desc vdec_desc = {
  31. .clks = vdec_clks,
  32. .num_clks = ARRAY_SIZE(vdec_clks),
  33. };
  34. static const struct of_device_id of_match_clk_mt8173_vdecsys[] = {
  35. { .compatible = "mediatek,mt8173-vdecsys", .data = &vdec_desc },
  36. { /* sentinel */ }
  37. };
  38. MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_vdecsys);
  39. static struct platform_driver clk_mt8173_vdecsys_drv = {
  40. .probe = mtk_clk_simple_probe,
  41. .remove = mtk_clk_simple_remove,
  42. .driver = {
  43. .name = "clk-mt8173-vdecsys",
  44. .of_match_table = of_match_clk_mt8173_vdecsys,
  45. },
  46. };
  47. module_platform_driver(clk_mt8173_vdecsys_drv);
  48. MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver");
  49. MODULE_LICENSE("GPL");