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- /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
- /*
- * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved
- * Author: Yu Tu <yu.tu@amlogic.com>
- */
- #ifndef __MESON_S4_PLL_H__
- #define __MESON_S4_PLL_H__
- #define ANACTRL_FIXPLL_CTRL0 0x040
- #define ANACTRL_FIXPLL_CTRL1 0x044
- #define ANACTRL_FIXPLL_CTRL3 0x04c
- #define ANACTRL_GP0PLL_CTRL0 0x080
- #define ANACTRL_GP0PLL_CTRL1 0x084
- #define ANACTRL_GP0PLL_CTRL2 0x088
- #define ANACTRL_GP0PLL_CTRL3 0x08c
- #define ANACTRL_GP0PLL_CTRL4 0x090
- #define ANACTRL_GP0PLL_CTRL5 0x094
- #define ANACTRL_GP0PLL_CTRL6 0x098
- #define ANACTRL_HIFIPLL_CTRL0 0x100
- #define ANACTRL_HIFIPLL_CTRL1 0x104
- #define ANACTRL_HIFIPLL_CTRL2 0x108
- #define ANACTRL_HIFIPLL_CTRL3 0x10c
- #define ANACTRL_HIFIPLL_CTRL4 0x110
- #define ANACTRL_HIFIPLL_CTRL5 0x114
- #define ANACTRL_HIFIPLL_CTRL6 0x118
- #define ANACTRL_MPLL_CTRL0 0x180
- #define ANACTRL_MPLL_CTRL1 0x184
- #define ANACTRL_MPLL_CTRL2 0x188
- #define ANACTRL_MPLL_CTRL3 0x18c
- #define ANACTRL_MPLL_CTRL4 0x190
- #define ANACTRL_MPLL_CTRL5 0x194
- #define ANACTRL_MPLL_CTRL6 0x198
- #define ANACTRL_MPLL_CTRL7 0x19c
- #define ANACTRL_MPLL_CTRL8 0x1a0
- #define ANACTRL_HDMIPLL_CTRL0 0x1c0
- #endif /* __MESON_S4_PLL_H__ */
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