clk.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  4. * Copyright (c) 2013 Linaro Ltd.
  5. * Author: Thomas Abraham <thomas.ab@samsung.com>
  6. *
  7. * This file includes utility functions to register clocks to common
  8. * clock framework for Samsung platforms.
  9. */
  10. #include <linux/slab.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/io.h>
  15. #include <linux/of_address.h>
  16. #include <linux/syscore_ops.h>
  17. #include "clk.h"
  18. static LIST_HEAD(clock_reg_cache_list);
  19. void samsung_clk_save(void __iomem *base,
  20. struct samsung_clk_reg_dump *rd,
  21. unsigned int num_regs)
  22. {
  23. for (; num_regs > 0; --num_regs, ++rd)
  24. rd->value = readl(base + rd->offset);
  25. }
  26. void samsung_clk_restore(void __iomem *base,
  27. const struct samsung_clk_reg_dump *rd,
  28. unsigned int num_regs)
  29. {
  30. for (; num_regs > 0; --num_regs, ++rd)
  31. writel(rd->value, base + rd->offset);
  32. }
  33. struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
  34. const unsigned long *rdump,
  35. unsigned long nr_rdump)
  36. {
  37. struct samsung_clk_reg_dump *rd;
  38. unsigned int i;
  39. rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
  40. if (!rd)
  41. return NULL;
  42. for (i = 0; i < nr_rdump; ++i)
  43. rd[i].offset = rdump[i];
  44. return rd;
  45. }
  46. /**
  47. * samsung_clk_init() - Create and initialize a clock provider object
  48. * @dev: CMU device to enable runtime PM, or NULL if RPM is not needed
  49. * @base: Start address (mapped) of CMU registers
  50. * @nr_clks: Total clock count to allocate in clock provider object
  51. *
  52. * Setup the essentials required to support clock lookup using Common Clock
  53. * Framework.
  54. *
  55. * Return: Allocated and initialized clock provider object.
  56. */
  57. struct samsung_clk_provider * __init samsung_clk_init(struct device *dev,
  58. void __iomem *base, unsigned long nr_clks)
  59. {
  60. struct samsung_clk_provider *ctx;
  61. int i;
  62. ctx = kzalloc(struct_size(ctx, clk_data.hws, nr_clks), GFP_KERNEL);
  63. if (!ctx)
  64. panic("could not allocate clock provider context.\n");
  65. for (i = 0; i < nr_clks; ++i)
  66. ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
  67. ctx->dev = dev;
  68. ctx->reg_base = base;
  69. ctx->clk_data.num = nr_clks;
  70. spin_lock_init(&ctx->lock);
  71. return ctx;
  72. }
  73. void __init samsung_clk_of_add_provider(struct device_node *np,
  74. struct samsung_clk_provider *ctx)
  75. {
  76. if (np) {
  77. if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
  78. &ctx->clk_data))
  79. panic("could not register clk provider\n");
  80. }
  81. }
  82. /* add a clock instance to the clock lookup table used for dt based lookup */
  83. void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
  84. struct clk_hw *clk_hw, unsigned int id)
  85. {
  86. if (id)
  87. ctx->clk_data.hws[id] = clk_hw;
  88. }
  89. /* register a list of aliases */
  90. void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
  91. const struct samsung_clock_alias *list,
  92. unsigned int nr_clk)
  93. {
  94. struct clk_hw *clk_hw;
  95. unsigned int idx, ret;
  96. for (idx = 0; idx < nr_clk; idx++, list++) {
  97. if (!list->id) {
  98. pr_err("%s: clock id missing for index %d\n", __func__,
  99. idx);
  100. continue;
  101. }
  102. clk_hw = ctx->clk_data.hws[list->id];
  103. if (!clk_hw) {
  104. pr_err("%s: failed to find clock %d\n", __func__,
  105. list->id);
  106. continue;
  107. }
  108. ret = clk_hw_register_clkdev(clk_hw, list->alias,
  109. list->dev_name);
  110. if (ret)
  111. pr_err("%s: failed to register lookup %s\n",
  112. __func__, list->alias);
  113. }
  114. }
  115. /* register a list of fixed clocks */
  116. void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
  117. const struct samsung_fixed_rate_clock *list,
  118. unsigned int nr_clk)
  119. {
  120. struct clk_hw *clk_hw;
  121. unsigned int idx;
  122. for (idx = 0; idx < nr_clk; idx++, list++) {
  123. clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
  124. list->parent_name, list->flags, list->fixed_rate);
  125. if (IS_ERR(clk_hw)) {
  126. pr_err("%s: failed to register clock %s\n", __func__,
  127. list->name);
  128. continue;
  129. }
  130. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  131. }
  132. }
  133. /* register a list of fixed factor clocks */
  134. void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
  135. const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
  136. {
  137. struct clk_hw *clk_hw;
  138. unsigned int idx;
  139. for (idx = 0; idx < nr_clk; idx++, list++) {
  140. clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
  141. list->parent_name, list->flags, list->mult, list->div);
  142. if (IS_ERR(clk_hw)) {
  143. pr_err("%s: failed to register clock %s\n", __func__,
  144. list->name);
  145. continue;
  146. }
  147. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  148. }
  149. }
  150. /* register a list of mux clocks */
  151. void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
  152. const struct samsung_mux_clock *list,
  153. unsigned int nr_clk)
  154. {
  155. struct clk_hw *clk_hw;
  156. unsigned int idx;
  157. for (idx = 0; idx < nr_clk; idx++, list++) {
  158. clk_hw = clk_hw_register_mux(ctx->dev, list->name,
  159. list->parent_names, list->num_parents, list->flags,
  160. ctx->reg_base + list->offset,
  161. list->shift, list->width, list->mux_flags, &ctx->lock);
  162. if (IS_ERR(clk_hw)) {
  163. pr_err("%s: failed to register clock %s\n", __func__,
  164. list->name);
  165. continue;
  166. }
  167. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  168. }
  169. }
  170. /* register a list of div clocks */
  171. void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
  172. const struct samsung_div_clock *list,
  173. unsigned int nr_clk)
  174. {
  175. struct clk_hw *clk_hw;
  176. unsigned int idx;
  177. for (idx = 0; idx < nr_clk; idx++, list++) {
  178. if (list->table)
  179. clk_hw = clk_hw_register_divider_table(ctx->dev,
  180. list->name, list->parent_name, list->flags,
  181. ctx->reg_base + list->offset,
  182. list->shift, list->width, list->div_flags,
  183. list->table, &ctx->lock);
  184. else
  185. clk_hw = clk_hw_register_divider(ctx->dev, list->name,
  186. list->parent_name, list->flags,
  187. ctx->reg_base + list->offset, list->shift,
  188. list->width, list->div_flags, &ctx->lock);
  189. if (IS_ERR(clk_hw)) {
  190. pr_err("%s: failed to register clock %s\n", __func__,
  191. list->name);
  192. continue;
  193. }
  194. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  195. }
  196. }
  197. /* register a list of gate clocks */
  198. void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
  199. const struct samsung_gate_clock *list,
  200. unsigned int nr_clk)
  201. {
  202. struct clk_hw *clk_hw;
  203. unsigned int idx;
  204. for (idx = 0; idx < nr_clk; idx++, list++) {
  205. clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
  206. list->flags, ctx->reg_base + list->offset,
  207. list->bit_idx, list->gate_flags, &ctx->lock);
  208. if (IS_ERR(clk_hw)) {
  209. pr_err("%s: failed to register clock %s\n", __func__,
  210. list->name);
  211. continue;
  212. }
  213. samsung_clk_add_lookup(ctx, clk_hw, list->id);
  214. }
  215. }
  216. /*
  217. * obtain the clock speed of all external fixed clock sources from device
  218. * tree and register it
  219. */
  220. void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
  221. struct samsung_fixed_rate_clock *fixed_rate_clk,
  222. unsigned int nr_fixed_rate_clk,
  223. const struct of_device_id *clk_matches)
  224. {
  225. const struct of_device_id *match;
  226. struct device_node *clk_np;
  227. u32 freq;
  228. for_each_matching_node_and_match(clk_np, clk_matches, &match) {
  229. if (of_property_read_u32(clk_np, "clock-frequency", &freq))
  230. continue;
  231. fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
  232. }
  233. samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
  234. }
  235. #ifdef CONFIG_PM_SLEEP
  236. static int samsung_clk_suspend(void)
  237. {
  238. struct samsung_clock_reg_cache *reg_cache;
  239. list_for_each_entry(reg_cache, &clock_reg_cache_list, node) {
  240. samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
  241. reg_cache->rd_num);
  242. samsung_clk_restore(reg_cache->reg_base, reg_cache->rsuspend,
  243. reg_cache->rsuspend_num);
  244. }
  245. return 0;
  246. }
  247. static void samsung_clk_resume(void)
  248. {
  249. struct samsung_clock_reg_cache *reg_cache;
  250. list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
  251. samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
  252. reg_cache->rd_num);
  253. }
  254. static struct syscore_ops samsung_clk_syscore_ops = {
  255. .suspend = samsung_clk_suspend,
  256. .resume = samsung_clk_resume,
  257. };
  258. void samsung_clk_extended_sleep_init(void __iomem *reg_base,
  259. const unsigned long *rdump,
  260. unsigned long nr_rdump,
  261. const struct samsung_clk_reg_dump *rsuspend,
  262. unsigned long nr_rsuspend)
  263. {
  264. struct samsung_clock_reg_cache *reg_cache;
  265. reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
  266. GFP_KERNEL);
  267. if (!reg_cache)
  268. panic("could not allocate register reg_cache.\n");
  269. reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
  270. if (!reg_cache->rdump)
  271. panic("could not allocate register dump storage.\n");
  272. if (list_empty(&clock_reg_cache_list))
  273. register_syscore_ops(&samsung_clk_syscore_ops);
  274. reg_cache->reg_base = reg_base;
  275. reg_cache->rd_num = nr_rdump;
  276. reg_cache->rsuspend = rsuspend;
  277. reg_cache->rsuspend_num = nr_rsuspend;
  278. list_add_tail(&reg_cache->node, &clock_reg_cache_list);
  279. }
  280. #endif
  281. /**
  282. * samsung_cmu_register_clocks() - Register all clocks provided in CMU object
  283. * @ctx: Clock provider object
  284. * @cmu: CMU object with clocks to register
  285. */
  286. void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
  287. const struct samsung_cmu_info *cmu)
  288. {
  289. if (cmu->pll_clks)
  290. samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks);
  291. if (cmu->mux_clks)
  292. samsung_clk_register_mux(ctx, cmu->mux_clks, cmu->nr_mux_clks);
  293. if (cmu->div_clks)
  294. samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
  295. if (cmu->gate_clks)
  296. samsung_clk_register_gate(ctx, cmu->gate_clks,
  297. cmu->nr_gate_clks);
  298. if (cmu->fixed_clks)
  299. samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
  300. cmu->nr_fixed_clks);
  301. if (cmu->fixed_factor_clks)
  302. samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
  303. cmu->nr_fixed_factor_clks);
  304. if (cmu->cpu_clks)
  305. samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
  306. }
  307. /*
  308. * Common function which registers plls, muxes, dividers and gates
  309. * for each CMU. It also add CMU register list to register cache.
  310. */
  311. struct samsung_clk_provider * __init samsung_cmu_register_one(
  312. struct device_node *np,
  313. const struct samsung_cmu_info *cmu)
  314. {
  315. void __iomem *reg_base;
  316. struct samsung_clk_provider *ctx;
  317. reg_base = of_iomap(np, 0);
  318. if (!reg_base) {
  319. panic("%s: failed to map registers\n", __func__);
  320. return NULL;
  321. }
  322. ctx = samsung_clk_init(NULL, reg_base, cmu->nr_clk_ids);
  323. samsung_cmu_register_clocks(ctx, cmu);
  324. if (cmu->clk_regs)
  325. samsung_clk_extended_sleep_init(reg_base,
  326. cmu->clk_regs, cmu->nr_clk_regs,
  327. cmu->suspend_regs, cmu->nr_suspend_regs);
  328. samsung_clk_of_add_provider(np, ctx);
  329. return ctx;
  330. }