clk-sun6i-apb0-gates.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2014 Free Electrons
  4. *
  5. * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
  6. *
  7. * Allwinner A31 APB0 clock gates driver
  8. */
  9. #include <linux/clk-provider.h>
  10. #include <linux/init.h>
  11. #include <linux/of.h>
  12. #include <linux/platform_device.h>
  13. #define SUN6I_APB0_GATES_MAX_SIZE 32
  14. struct gates_data {
  15. DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
  16. };
  17. static const struct gates_data sun6i_a31_apb0_gates __initconst = {
  18. .mask = {0x7F},
  19. };
  20. static const struct gates_data sun8i_a23_apb0_gates __initconst = {
  21. .mask = {0x5D},
  22. };
  23. static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
  24. { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
  25. { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
  26. { /* sentinel */ }
  27. };
  28. static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
  29. {
  30. struct device_node *np = pdev->dev.of_node;
  31. struct clk_onecell_data *clk_data;
  32. const struct gates_data *data;
  33. const char *clk_parent;
  34. const char *clk_name;
  35. void __iomem *reg;
  36. int ngates;
  37. int i;
  38. int j = 0;
  39. if (!np)
  40. return -ENODEV;
  41. data = of_device_get_match_data(&pdev->dev);
  42. if (!data)
  43. return -ENODEV;
  44. reg = devm_platform_ioremap_resource(pdev, 0);
  45. if (IS_ERR(reg))
  46. return PTR_ERR(reg);
  47. clk_parent = of_clk_get_parent_name(np, 0);
  48. if (!clk_parent)
  49. return -EINVAL;
  50. clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
  51. GFP_KERNEL);
  52. if (!clk_data)
  53. return -ENOMEM;
  54. /* Worst-case size approximation and memory allocation */
  55. ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
  56. clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
  57. sizeof(struct clk *), GFP_KERNEL);
  58. if (!clk_data->clks)
  59. return -ENOMEM;
  60. for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
  61. of_property_read_string_index(np, "clock-output-names",
  62. j, &clk_name);
  63. clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
  64. clk_parent, 0, reg, i,
  65. 0, NULL);
  66. WARN_ON(IS_ERR(clk_data->clks[i]));
  67. j++;
  68. }
  69. clk_data->clk_num = ngates + 1;
  70. return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
  71. }
  72. static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
  73. .driver = {
  74. .name = "sun6i-a31-apb0-gates-clk",
  75. .of_match_table = sun6i_a31_apb0_gates_clk_dt_ids,
  76. },
  77. .probe = sun6i_a31_apb0_gates_clk_probe,
  78. };
  79. builtin_platform_driver(sun6i_a31_apb0_gates_clk_driver);