safexcel_hash.c 86 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Marvell
  4. *
  5. * Antoine Tenart <antoine.tenart@free-electrons.com>
  6. */
  7. #include <crypto/aes.h>
  8. #include <crypto/hmac.h>
  9. #include <crypto/md5.h>
  10. #include <crypto/sha1.h>
  11. #include <crypto/sha2.h>
  12. #include <crypto/sha3.h>
  13. #include <crypto/skcipher.h>
  14. #include <crypto/sm3.h>
  15. #include <crypto/internal/cipher.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/dmapool.h>
  19. #include "safexcel.h"
  20. struct safexcel_ahash_ctx {
  21. struct safexcel_context base;
  22. u32 alg;
  23. u8 key_sz;
  24. bool cbcmac;
  25. bool do_fallback;
  26. bool fb_init_done;
  27. bool fb_do_setkey;
  28. struct crypto_aes_ctx *aes;
  29. struct crypto_ahash *fback;
  30. struct crypto_shash *shpre;
  31. struct shash_desc *shdesc;
  32. };
  33. struct safexcel_ahash_req {
  34. bool last_req;
  35. bool finish;
  36. bool hmac;
  37. bool needs_inv;
  38. bool hmac_zlen;
  39. bool len_is_le;
  40. bool not_first;
  41. bool xcbcmac;
  42. int nents;
  43. dma_addr_t result_dma;
  44. u32 digest;
  45. u8 state_sz; /* expected state size, only set once */
  46. u8 block_sz; /* block size, only set once */
  47. u8 digest_sz; /* output digest size, only set once */
  48. __le32 state[SHA3_512_BLOCK_SIZE /
  49. sizeof(__le32)] __aligned(sizeof(__le32));
  50. u64 len;
  51. u64 processed;
  52. u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
  53. dma_addr_t cache_dma;
  54. unsigned int cache_sz;
  55. u8 cache_next[HASH_CACHE_SIZE] __aligned(sizeof(u32));
  56. };
  57. static inline u64 safexcel_queued_len(struct safexcel_ahash_req *req)
  58. {
  59. return req->len - req->processed;
  60. }
  61. static void safexcel_hash_token(struct safexcel_command_desc *cdesc,
  62. u32 input_length, u32 result_length,
  63. bool cbcmac)
  64. {
  65. struct safexcel_token *token =
  66. (struct safexcel_token *)cdesc->control_data.token;
  67. token[0].opcode = EIP197_TOKEN_OPCODE_DIRECTION;
  68. token[0].packet_length = input_length;
  69. token[0].instructions = EIP197_TOKEN_INS_TYPE_HASH;
  70. input_length &= 15;
  71. if (unlikely(cbcmac && input_length)) {
  72. token[0].stat = 0;
  73. token[1].opcode = EIP197_TOKEN_OPCODE_INSERT;
  74. token[1].packet_length = 16 - input_length;
  75. token[1].stat = EIP197_TOKEN_STAT_LAST_HASH;
  76. token[1].instructions = EIP197_TOKEN_INS_TYPE_HASH;
  77. } else {
  78. token[0].stat = EIP197_TOKEN_STAT_LAST_HASH;
  79. eip197_noop_token(&token[1]);
  80. }
  81. token[2].opcode = EIP197_TOKEN_OPCODE_INSERT;
  82. token[2].stat = EIP197_TOKEN_STAT_LAST_HASH |
  83. EIP197_TOKEN_STAT_LAST_PACKET;
  84. token[2].packet_length = result_length;
  85. token[2].instructions = EIP197_TOKEN_INS_TYPE_OUTPUT |
  86. EIP197_TOKEN_INS_INSERT_HASH_DIGEST;
  87. eip197_noop_token(&token[3]);
  88. }
  89. static void safexcel_context_control(struct safexcel_ahash_ctx *ctx,
  90. struct safexcel_ahash_req *req,
  91. struct safexcel_command_desc *cdesc)
  92. {
  93. struct safexcel_crypto_priv *priv = ctx->base.priv;
  94. u64 count = 0;
  95. cdesc->control_data.control0 = ctx->alg;
  96. cdesc->control_data.control1 = 0;
  97. /*
  98. * Copy the input digest if needed, and setup the context
  99. * fields. Do this now as we need it to setup the first command
  100. * descriptor.
  101. */
  102. if (unlikely(req->digest == CONTEXT_CONTROL_DIGEST_XCM)) {
  103. if (req->xcbcmac)
  104. memcpy(ctx->base.ctxr->data, &ctx->base.ipad, ctx->key_sz);
  105. else
  106. memcpy(ctx->base.ctxr->data, req->state, req->state_sz);
  107. if (!req->finish && req->xcbcmac)
  108. cdesc->control_data.control0 |=
  109. CONTEXT_CONTROL_DIGEST_XCM |
  110. CONTEXT_CONTROL_TYPE_HASH_OUT |
  111. CONTEXT_CONTROL_NO_FINISH_HASH |
  112. CONTEXT_CONTROL_SIZE(req->state_sz /
  113. sizeof(u32));
  114. else
  115. cdesc->control_data.control0 |=
  116. CONTEXT_CONTROL_DIGEST_XCM |
  117. CONTEXT_CONTROL_TYPE_HASH_OUT |
  118. CONTEXT_CONTROL_SIZE(req->state_sz /
  119. sizeof(u32));
  120. return;
  121. } else if (!req->processed) {
  122. /* First - and possibly only - block of basic hash only */
  123. if (req->finish)
  124. cdesc->control_data.control0 |= req->digest |
  125. CONTEXT_CONTROL_TYPE_HASH_OUT |
  126. CONTEXT_CONTROL_RESTART_HASH |
  127. /* ensure its not 0! */
  128. CONTEXT_CONTROL_SIZE(1);
  129. else
  130. cdesc->control_data.control0 |= req->digest |
  131. CONTEXT_CONTROL_TYPE_HASH_OUT |
  132. CONTEXT_CONTROL_RESTART_HASH |
  133. CONTEXT_CONTROL_NO_FINISH_HASH |
  134. /* ensure its not 0! */
  135. CONTEXT_CONTROL_SIZE(1);
  136. return;
  137. }
  138. /* Hash continuation or HMAC, setup (inner) digest from state */
  139. memcpy(ctx->base.ctxr->data, req->state, req->state_sz);
  140. if (req->finish) {
  141. /* Compute digest count for hash/HMAC finish operations */
  142. if ((req->digest == CONTEXT_CONTROL_DIGEST_PRECOMPUTED) ||
  143. req->hmac_zlen || (req->processed != req->block_sz)) {
  144. count = req->processed / EIP197_COUNTER_BLOCK_SIZE;
  145. /* This is a hardware limitation, as the
  146. * counter must fit into an u32. This represents
  147. * a fairly big amount of input data, so we
  148. * shouldn't see this.
  149. */
  150. if (unlikely(count & 0xffffffff00000000ULL)) {
  151. dev_warn(priv->dev,
  152. "Input data is too big\n");
  153. return;
  154. }
  155. }
  156. if ((req->digest == CONTEXT_CONTROL_DIGEST_PRECOMPUTED) ||
  157. /* Special case: zero length HMAC */
  158. req->hmac_zlen ||
  159. /* PE HW < 4.4 cannot do HMAC continue, fake using hash */
  160. (req->processed != req->block_sz)) {
  161. /* Basic hash continue operation, need digest + cnt */
  162. cdesc->control_data.control0 |=
  163. CONTEXT_CONTROL_SIZE((req->state_sz >> 2) + 1) |
  164. CONTEXT_CONTROL_TYPE_HASH_OUT |
  165. CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  166. /* For zero-len HMAC, don't finalize, already padded! */
  167. if (req->hmac_zlen)
  168. cdesc->control_data.control0 |=
  169. CONTEXT_CONTROL_NO_FINISH_HASH;
  170. cdesc->control_data.control1 |=
  171. CONTEXT_CONTROL_DIGEST_CNT;
  172. ctx->base.ctxr->data[req->state_sz >> 2] =
  173. cpu_to_le32(count);
  174. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  175. /* Clear zero-length HMAC flag for next operation! */
  176. req->hmac_zlen = false;
  177. } else { /* HMAC */
  178. /* Need outer digest for HMAC finalization */
  179. memcpy(ctx->base.ctxr->data + (req->state_sz >> 2),
  180. &ctx->base.opad, req->state_sz);
  181. /* Single pass HMAC - no digest count */
  182. cdesc->control_data.control0 |=
  183. CONTEXT_CONTROL_SIZE(req->state_sz >> 1) |
  184. CONTEXT_CONTROL_TYPE_HASH_OUT |
  185. CONTEXT_CONTROL_DIGEST_HMAC;
  186. }
  187. } else { /* Hash continuation, do not finish yet */
  188. cdesc->control_data.control0 |=
  189. CONTEXT_CONTROL_SIZE(req->state_sz >> 2) |
  190. CONTEXT_CONTROL_DIGEST_PRECOMPUTED |
  191. CONTEXT_CONTROL_TYPE_HASH_OUT |
  192. CONTEXT_CONTROL_NO_FINISH_HASH;
  193. }
  194. }
  195. static int safexcel_ahash_enqueue(struct ahash_request *areq);
  196. static int safexcel_handle_req_result(struct safexcel_crypto_priv *priv,
  197. int ring,
  198. struct crypto_async_request *async,
  199. bool *should_complete, int *ret)
  200. {
  201. struct safexcel_result_desc *rdesc;
  202. struct ahash_request *areq = ahash_request_cast(async);
  203. struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
  204. struct safexcel_ahash_req *sreq = ahash_request_ctx_dma(areq);
  205. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(ahash);
  206. u64 cache_len;
  207. *ret = 0;
  208. rdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].rdr);
  209. if (IS_ERR(rdesc)) {
  210. dev_err(priv->dev,
  211. "hash: result: could not retrieve the result descriptor\n");
  212. *ret = PTR_ERR(rdesc);
  213. } else {
  214. *ret = safexcel_rdesc_check_errors(priv, rdesc);
  215. }
  216. safexcel_complete(priv, ring);
  217. if (sreq->nents) {
  218. dma_unmap_sg(priv->dev, areq->src, sreq->nents, DMA_TO_DEVICE);
  219. sreq->nents = 0;
  220. }
  221. if (sreq->result_dma) {
  222. dma_unmap_single(priv->dev, sreq->result_dma, sreq->digest_sz,
  223. DMA_FROM_DEVICE);
  224. sreq->result_dma = 0;
  225. }
  226. if (sreq->cache_dma) {
  227. dma_unmap_single(priv->dev, sreq->cache_dma, sreq->cache_sz,
  228. DMA_TO_DEVICE);
  229. sreq->cache_dma = 0;
  230. sreq->cache_sz = 0;
  231. }
  232. if (sreq->finish) {
  233. if (sreq->hmac &&
  234. (sreq->digest != CONTEXT_CONTROL_DIGEST_HMAC)) {
  235. /* Faking HMAC using hash - need to do outer hash */
  236. memcpy(sreq->cache, sreq->state,
  237. crypto_ahash_digestsize(ahash));
  238. memcpy(sreq->state, &ctx->base.opad, sreq->digest_sz);
  239. sreq->len = sreq->block_sz +
  240. crypto_ahash_digestsize(ahash);
  241. sreq->processed = sreq->block_sz;
  242. sreq->hmac = 0;
  243. if (priv->flags & EIP197_TRC_CACHE)
  244. ctx->base.needs_inv = true;
  245. areq->nbytes = 0;
  246. safexcel_ahash_enqueue(areq);
  247. *should_complete = false; /* Not done yet */
  248. return 1;
  249. }
  250. if (unlikely(sreq->digest == CONTEXT_CONTROL_DIGEST_XCM &&
  251. ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_CRC32)) {
  252. /* Undo final XOR with 0xffffffff ...*/
  253. *(__le32 *)areq->result = ~sreq->state[0];
  254. } else {
  255. memcpy(areq->result, sreq->state,
  256. crypto_ahash_digestsize(ahash));
  257. }
  258. }
  259. cache_len = safexcel_queued_len(sreq);
  260. if (cache_len)
  261. memcpy(sreq->cache, sreq->cache_next, cache_len);
  262. *should_complete = true;
  263. return 1;
  264. }
  265. static int safexcel_ahash_send_req(struct crypto_async_request *async, int ring,
  266. int *commands, int *results)
  267. {
  268. struct ahash_request *areq = ahash_request_cast(async);
  269. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  270. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  271. struct safexcel_crypto_priv *priv = ctx->base.priv;
  272. struct safexcel_command_desc *cdesc, *first_cdesc = NULL;
  273. struct safexcel_result_desc *rdesc;
  274. struct scatterlist *sg;
  275. struct safexcel_token *dmmy;
  276. int i, extra = 0, n_cdesc = 0, ret = 0, cache_len, skip = 0;
  277. u64 queued, len;
  278. queued = safexcel_queued_len(req);
  279. if (queued <= HASH_CACHE_SIZE)
  280. cache_len = queued;
  281. else
  282. cache_len = queued - areq->nbytes;
  283. if (!req->finish && !req->last_req) {
  284. /* If this is not the last request and the queued data does not
  285. * fit into full cache blocks, cache it for the next send call.
  286. */
  287. extra = queued & (HASH_CACHE_SIZE - 1);
  288. /* If this is not the last request and the queued data
  289. * is a multiple of a block, cache the last one for now.
  290. */
  291. if (!extra)
  292. extra = HASH_CACHE_SIZE;
  293. sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
  294. req->cache_next, extra,
  295. areq->nbytes - extra);
  296. queued -= extra;
  297. if (!queued) {
  298. *commands = 0;
  299. *results = 0;
  300. return 0;
  301. }
  302. extra = 0;
  303. }
  304. if (unlikely(req->xcbcmac && req->processed > AES_BLOCK_SIZE)) {
  305. if (unlikely(cache_len < AES_BLOCK_SIZE)) {
  306. /*
  307. * Cache contains less than 1 full block, complete.
  308. */
  309. extra = AES_BLOCK_SIZE - cache_len;
  310. if (queued > cache_len) {
  311. /* More data follows: borrow bytes */
  312. u64 tmp = queued - cache_len;
  313. skip = min_t(u64, tmp, extra);
  314. sg_pcopy_to_buffer(areq->src,
  315. sg_nents(areq->src),
  316. req->cache + cache_len,
  317. skip, 0);
  318. }
  319. extra -= skip;
  320. memset(req->cache + cache_len + skip, 0, extra);
  321. if (!ctx->cbcmac && extra) {
  322. // 10- padding for XCBCMAC & CMAC
  323. req->cache[cache_len + skip] = 0x80;
  324. // HW will use K2 iso K3 - compensate!
  325. for (i = 0; i < AES_BLOCK_SIZE / 4; i++) {
  326. u32 *cache = (void *)req->cache;
  327. u32 *ipad = ctx->base.ipad.word;
  328. u32 x;
  329. x = ipad[i] ^ ipad[i + 4];
  330. cache[i] ^= swab32(x);
  331. }
  332. }
  333. cache_len = AES_BLOCK_SIZE;
  334. queued = queued + extra;
  335. }
  336. /* XCBC continue: XOR previous result into 1st word */
  337. crypto_xor(req->cache, (const u8 *)req->state, AES_BLOCK_SIZE);
  338. }
  339. len = queued;
  340. /* Add a command descriptor for the cached data, if any */
  341. if (cache_len) {
  342. req->cache_dma = dma_map_single(priv->dev, req->cache,
  343. cache_len, DMA_TO_DEVICE);
  344. if (dma_mapping_error(priv->dev, req->cache_dma))
  345. return -EINVAL;
  346. req->cache_sz = cache_len;
  347. first_cdesc = safexcel_add_cdesc(priv, ring, 1,
  348. (cache_len == len),
  349. req->cache_dma, cache_len,
  350. len, ctx->base.ctxr_dma,
  351. &dmmy);
  352. if (IS_ERR(first_cdesc)) {
  353. ret = PTR_ERR(first_cdesc);
  354. goto unmap_cache;
  355. }
  356. n_cdesc++;
  357. queued -= cache_len;
  358. if (!queued)
  359. goto send_command;
  360. }
  361. /* Now handle the current ahash request buffer(s) */
  362. req->nents = dma_map_sg(priv->dev, areq->src,
  363. sg_nents_for_len(areq->src,
  364. areq->nbytes),
  365. DMA_TO_DEVICE);
  366. if (!req->nents) {
  367. ret = -ENOMEM;
  368. goto cdesc_rollback;
  369. }
  370. for_each_sg(areq->src, sg, req->nents, i) {
  371. int sglen = sg_dma_len(sg);
  372. if (unlikely(sglen <= skip)) {
  373. skip -= sglen;
  374. continue;
  375. }
  376. /* Do not overflow the request */
  377. if ((queued + skip) <= sglen)
  378. sglen = queued;
  379. else
  380. sglen -= skip;
  381. cdesc = safexcel_add_cdesc(priv, ring, !n_cdesc,
  382. !(queued - sglen),
  383. sg_dma_address(sg) + skip, sglen,
  384. len, ctx->base.ctxr_dma, &dmmy);
  385. if (IS_ERR(cdesc)) {
  386. ret = PTR_ERR(cdesc);
  387. goto unmap_sg;
  388. }
  389. if (!n_cdesc)
  390. first_cdesc = cdesc;
  391. n_cdesc++;
  392. queued -= sglen;
  393. if (!queued)
  394. break;
  395. skip = 0;
  396. }
  397. send_command:
  398. /* Setup the context options */
  399. safexcel_context_control(ctx, req, first_cdesc);
  400. /* Add the token */
  401. safexcel_hash_token(first_cdesc, len, req->digest_sz, ctx->cbcmac);
  402. req->result_dma = dma_map_single(priv->dev, req->state, req->digest_sz,
  403. DMA_FROM_DEVICE);
  404. if (dma_mapping_error(priv->dev, req->result_dma)) {
  405. ret = -EINVAL;
  406. goto unmap_sg;
  407. }
  408. /* Add a result descriptor */
  409. rdesc = safexcel_add_rdesc(priv, ring, 1, 1, req->result_dma,
  410. req->digest_sz);
  411. if (IS_ERR(rdesc)) {
  412. ret = PTR_ERR(rdesc);
  413. goto unmap_result;
  414. }
  415. safexcel_rdr_req_set(priv, ring, rdesc, &areq->base);
  416. req->processed += len - extra;
  417. *commands = n_cdesc;
  418. *results = 1;
  419. return 0;
  420. unmap_result:
  421. dma_unmap_single(priv->dev, req->result_dma, req->digest_sz,
  422. DMA_FROM_DEVICE);
  423. unmap_sg:
  424. if (req->nents) {
  425. dma_unmap_sg(priv->dev, areq->src, req->nents, DMA_TO_DEVICE);
  426. req->nents = 0;
  427. }
  428. cdesc_rollback:
  429. for (i = 0; i < n_cdesc; i++)
  430. safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
  431. unmap_cache:
  432. if (req->cache_dma) {
  433. dma_unmap_single(priv->dev, req->cache_dma, req->cache_sz,
  434. DMA_TO_DEVICE);
  435. req->cache_dma = 0;
  436. req->cache_sz = 0;
  437. }
  438. return ret;
  439. }
  440. static int safexcel_handle_inv_result(struct safexcel_crypto_priv *priv,
  441. int ring,
  442. struct crypto_async_request *async,
  443. bool *should_complete, int *ret)
  444. {
  445. struct safexcel_result_desc *rdesc;
  446. struct ahash_request *areq = ahash_request_cast(async);
  447. struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
  448. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(ahash);
  449. int enq_ret;
  450. *ret = 0;
  451. rdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].rdr);
  452. if (IS_ERR(rdesc)) {
  453. dev_err(priv->dev,
  454. "hash: invalidate: could not retrieve the result descriptor\n");
  455. *ret = PTR_ERR(rdesc);
  456. } else {
  457. *ret = safexcel_rdesc_check_errors(priv, rdesc);
  458. }
  459. safexcel_complete(priv, ring);
  460. if (ctx->base.exit_inv) {
  461. dma_pool_free(priv->context_pool, ctx->base.ctxr,
  462. ctx->base.ctxr_dma);
  463. *should_complete = true;
  464. return 1;
  465. }
  466. ring = safexcel_select_ring(priv);
  467. ctx->base.ring = ring;
  468. spin_lock_bh(&priv->ring[ring].queue_lock);
  469. enq_ret = crypto_enqueue_request(&priv->ring[ring].queue, async);
  470. spin_unlock_bh(&priv->ring[ring].queue_lock);
  471. if (enq_ret != -EINPROGRESS)
  472. *ret = enq_ret;
  473. queue_work(priv->ring[ring].workqueue,
  474. &priv->ring[ring].work_data.work);
  475. *should_complete = false;
  476. return 1;
  477. }
  478. static int safexcel_handle_result(struct safexcel_crypto_priv *priv, int ring,
  479. struct crypto_async_request *async,
  480. bool *should_complete, int *ret)
  481. {
  482. struct ahash_request *areq = ahash_request_cast(async);
  483. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  484. int err;
  485. BUG_ON(!(priv->flags & EIP197_TRC_CACHE) && req->needs_inv);
  486. if (req->needs_inv) {
  487. req->needs_inv = false;
  488. err = safexcel_handle_inv_result(priv, ring, async,
  489. should_complete, ret);
  490. } else {
  491. err = safexcel_handle_req_result(priv, ring, async,
  492. should_complete, ret);
  493. }
  494. return err;
  495. }
  496. static int safexcel_ahash_send_inv(struct crypto_async_request *async,
  497. int ring, int *commands, int *results)
  498. {
  499. struct ahash_request *areq = ahash_request_cast(async);
  500. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  501. int ret;
  502. ret = safexcel_invalidate_cache(async, ctx->base.priv,
  503. ctx->base.ctxr_dma, ring);
  504. if (unlikely(ret))
  505. return ret;
  506. *commands = 1;
  507. *results = 1;
  508. return 0;
  509. }
  510. static int safexcel_ahash_send(struct crypto_async_request *async,
  511. int ring, int *commands, int *results)
  512. {
  513. struct ahash_request *areq = ahash_request_cast(async);
  514. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  515. int ret;
  516. if (req->needs_inv)
  517. ret = safexcel_ahash_send_inv(async, ring, commands, results);
  518. else
  519. ret = safexcel_ahash_send_req(async, ring, commands, results);
  520. return ret;
  521. }
  522. static int safexcel_ahash_exit_inv(struct crypto_tfm *tfm)
  523. {
  524. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  525. struct safexcel_crypto_priv *priv = ctx->base.priv;
  526. EIP197_REQUEST_ON_STACK(req, ahash, EIP197_AHASH_REQ_SIZE);
  527. struct safexcel_ahash_req *rctx = ahash_request_ctx_dma(req);
  528. DECLARE_CRYPTO_WAIT(result);
  529. int ring = ctx->base.ring;
  530. int err;
  531. memset(req, 0, EIP197_AHASH_REQ_SIZE);
  532. /* create invalidation request */
  533. init_completion(&result.completion);
  534. ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
  535. crypto_req_done, &result);
  536. ahash_request_set_tfm(req, __crypto_ahash_cast(tfm));
  537. ctx = crypto_tfm_ctx(req->base.tfm);
  538. ctx->base.exit_inv = true;
  539. rctx->needs_inv = true;
  540. spin_lock_bh(&priv->ring[ring].queue_lock);
  541. crypto_enqueue_request(&priv->ring[ring].queue, &req->base);
  542. spin_unlock_bh(&priv->ring[ring].queue_lock);
  543. queue_work(priv->ring[ring].workqueue,
  544. &priv->ring[ring].work_data.work);
  545. err = crypto_wait_req(-EINPROGRESS, &result);
  546. if (err) {
  547. dev_warn(priv->dev, "hash: completion error (%d)\n", err);
  548. return err;
  549. }
  550. return 0;
  551. }
  552. /* safexcel_ahash_cache: cache data until at least one request can be sent to
  553. * the engine, aka. when there is at least 1 block size in the pipe.
  554. */
  555. static int safexcel_ahash_cache(struct ahash_request *areq)
  556. {
  557. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  558. u64 cache_len;
  559. /* cache_len: everything accepted by the driver but not sent yet,
  560. * tot sz handled by update() - last req sz - tot sz handled by send()
  561. */
  562. cache_len = safexcel_queued_len(req);
  563. /*
  564. * In case there isn't enough bytes to proceed (less than a
  565. * block size), cache the data until we have enough.
  566. */
  567. if (cache_len + areq->nbytes <= HASH_CACHE_SIZE) {
  568. sg_pcopy_to_buffer(areq->src, sg_nents(areq->src),
  569. req->cache + cache_len,
  570. areq->nbytes, 0);
  571. return 0;
  572. }
  573. /* We couldn't cache all the data */
  574. return -E2BIG;
  575. }
  576. static int safexcel_ahash_enqueue(struct ahash_request *areq)
  577. {
  578. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  579. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  580. struct safexcel_crypto_priv *priv = ctx->base.priv;
  581. int ret, ring;
  582. req->needs_inv = false;
  583. if (ctx->base.ctxr) {
  584. if (priv->flags & EIP197_TRC_CACHE && !ctx->base.needs_inv &&
  585. /* invalidate for *any* non-XCBC continuation */
  586. ((req->not_first && !req->xcbcmac) ||
  587. /* invalidate if (i)digest changed */
  588. memcmp(ctx->base.ctxr->data, req->state, req->state_sz) ||
  589. /* invalidate for HMAC finish with odigest changed */
  590. (req->finish && req->hmac &&
  591. memcmp(ctx->base.ctxr->data + (req->state_sz>>2),
  592. &ctx->base.opad, req->state_sz))))
  593. /*
  594. * We're still setting needs_inv here, even though it is
  595. * cleared right away, because the needs_inv flag can be
  596. * set in other functions and we want to keep the same
  597. * logic.
  598. */
  599. ctx->base.needs_inv = true;
  600. if (ctx->base.needs_inv) {
  601. ctx->base.needs_inv = false;
  602. req->needs_inv = true;
  603. }
  604. } else {
  605. ctx->base.ring = safexcel_select_ring(priv);
  606. ctx->base.ctxr = dma_pool_zalloc(priv->context_pool,
  607. EIP197_GFP_FLAGS(areq->base),
  608. &ctx->base.ctxr_dma);
  609. if (!ctx->base.ctxr)
  610. return -ENOMEM;
  611. }
  612. req->not_first = true;
  613. ring = ctx->base.ring;
  614. spin_lock_bh(&priv->ring[ring].queue_lock);
  615. ret = crypto_enqueue_request(&priv->ring[ring].queue, &areq->base);
  616. spin_unlock_bh(&priv->ring[ring].queue_lock);
  617. queue_work(priv->ring[ring].workqueue,
  618. &priv->ring[ring].work_data.work);
  619. return ret;
  620. }
  621. static int safexcel_ahash_update(struct ahash_request *areq)
  622. {
  623. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  624. int ret;
  625. /* If the request is 0 length, do nothing */
  626. if (!areq->nbytes)
  627. return 0;
  628. /* Add request to the cache if it fits */
  629. ret = safexcel_ahash_cache(areq);
  630. /* Update total request length */
  631. req->len += areq->nbytes;
  632. /* If not all data could fit into the cache, go process the excess.
  633. * Also go process immediately for an HMAC IV precompute, which
  634. * will never be finished at all, but needs to be processed anyway.
  635. */
  636. if ((ret && !req->finish) || req->last_req)
  637. return safexcel_ahash_enqueue(areq);
  638. return 0;
  639. }
  640. static int safexcel_ahash_final(struct ahash_request *areq)
  641. {
  642. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  643. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  644. req->finish = true;
  645. if (unlikely(!req->len && !areq->nbytes)) {
  646. /*
  647. * If we have an overall 0 length *hash* request:
  648. * The HW cannot do 0 length hash, so we provide the correct
  649. * result directly here.
  650. */
  651. if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_MD5)
  652. memcpy(areq->result, md5_zero_message_hash,
  653. MD5_DIGEST_SIZE);
  654. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA1)
  655. memcpy(areq->result, sha1_zero_message_hash,
  656. SHA1_DIGEST_SIZE);
  657. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA224)
  658. memcpy(areq->result, sha224_zero_message_hash,
  659. SHA224_DIGEST_SIZE);
  660. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA256)
  661. memcpy(areq->result, sha256_zero_message_hash,
  662. SHA256_DIGEST_SIZE);
  663. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA384)
  664. memcpy(areq->result, sha384_zero_message_hash,
  665. SHA384_DIGEST_SIZE);
  666. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SHA512)
  667. memcpy(areq->result, sha512_zero_message_hash,
  668. SHA512_DIGEST_SIZE);
  669. else if (ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_SM3) {
  670. memcpy(areq->result,
  671. EIP197_SM3_ZEROM_HASH, SM3_DIGEST_SIZE);
  672. }
  673. return 0;
  674. } else if (unlikely(req->digest == CONTEXT_CONTROL_DIGEST_XCM &&
  675. ctx->alg == CONTEXT_CONTROL_CRYPTO_ALG_MD5 &&
  676. req->len == sizeof(u32) && !areq->nbytes)) {
  677. /* Zero length CRC32 */
  678. memcpy(areq->result, &ctx->base.ipad, sizeof(u32));
  679. return 0;
  680. } else if (unlikely(ctx->cbcmac && req->len == AES_BLOCK_SIZE &&
  681. !areq->nbytes)) {
  682. /* Zero length CBC MAC */
  683. memset(areq->result, 0, AES_BLOCK_SIZE);
  684. return 0;
  685. } else if (unlikely(req->xcbcmac && req->len == AES_BLOCK_SIZE &&
  686. !areq->nbytes)) {
  687. /* Zero length (X)CBC/CMAC */
  688. int i;
  689. for (i = 0; i < AES_BLOCK_SIZE / sizeof(u32); i++) {
  690. u32 *result = (void *)areq->result;
  691. /* K3 */
  692. result[i] = swab32(ctx->base.ipad.word[i + 4]);
  693. }
  694. areq->result[0] ^= 0x80; // 10- padding
  695. aes_encrypt(ctx->aes, areq->result, areq->result);
  696. return 0;
  697. } else if (unlikely(req->hmac &&
  698. (req->len == req->block_sz) &&
  699. !areq->nbytes)) {
  700. /*
  701. * If we have an overall 0 length *HMAC* request:
  702. * For HMAC, we need to finalize the inner digest
  703. * and then perform the outer hash.
  704. */
  705. /* generate pad block in the cache */
  706. /* start with a hash block of all zeroes */
  707. memset(req->cache, 0, req->block_sz);
  708. /* set the first byte to 0x80 to 'append a 1 bit' */
  709. req->cache[0] = 0x80;
  710. /* add the length in bits in the last 2 bytes */
  711. if (req->len_is_le) {
  712. /* Little endian length word (e.g. MD5) */
  713. req->cache[req->block_sz-8] = (req->block_sz << 3) &
  714. 255;
  715. req->cache[req->block_sz-7] = (req->block_sz >> 5);
  716. } else {
  717. /* Big endian length word (e.g. any SHA) */
  718. req->cache[req->block_sz-2] = (req->block_sz >> 5);
  719. req->cache[req->block_sz-1] = (req->block_sz << 3) &
  720. 255;
  721. }
  722. req->len += req->block_sz; /* plus 1 hash block */
  723. /* Set special zero-length HMAC flag */
  724. req->hmac_zlen = true;
  725. /* Finalize HMAC */
  726. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  727. } else if (req->hmac) {
  728. /* Finalize HMAC */
  729. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  730. }
  731. return safexcel_ahash_enqueue(areq);
  732. }
  733. static int safexcel_ahash_finup(struct ahash_request *areq)
  734. {
  735. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  736. req->finish = true;
  737. safexcel_ahash_update(areq);
  738. return safexcel_ahash_final(areq);
  739. }
  740. static int safexcel_ahash_export(struct ahash_request *areq, void *out)
  741. {
  742. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  743. struct safexcel_ahash_export_state *export = out;
  744. export->len = req->len;
  745. export->processed = req->processed;
  746. export->digest = req->digest;
  747. memcpy(export->state, req->state, req->state_sz);
  748. memcpy(export->cache, req->cache, HASH_CACHE_SIZE);
  749. return 0;
  750. }
  751. static int safexcel_ahash_import(struct ahash_request *areq, const void *in)
  752. {
  753. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  754. const struct safexcel_ahash_export_state *export = in;
  755. int ret;
  756. ret = crypto_ahash_init(areq);
  757. if (ret)
  758. return ret;
  759. req->len = export->len;
  760. req->processed = export->processed;
  761. req->digest = export->digest;
  762. memcpy(req->cache, export->cache, HASH_CACHE_SIZE);
  763. memcpy(req->state, export->state, req->state_sz);
  764. return 0;
  765. }
  766. static int safexcel_ahash_cra_init(struct crypto_tfm *tfm)
  767. {
  768. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  769. struct safexcel_alg_template *tmpl =
  770. container_of(__crypto_ahash_alg(tfm->__crt_alg),
  771. struct safexcel_alg_template, alg.ahash);
  772. ctx->base.priv = tmpl->priv;
  773. ctx->base.send = safexcel_ahash_send;
  774. ctx->base.handle_result = safexcel_handle_result;
  775. ctx->fb_do_setkey = false;
  776. crypto_ahash_set_reqsize_dma(__crypto_ahash_cast(tfm),
  777. sizeof(struct safexcel_ahash_req));
  778. return 0;
  779. }
  780. static int safexcel_sha1_init(struct ahash_request *areq)
  781. {
  782. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  783. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  784. memset(req, 0, sizeof(*req));
  785. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA1;
  786. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  787. req->state_sz = SHA1_DIGEST_SIZE;
  788. req->digest_sz = SHA1_DIGEST_SIZE;
  789. req->block_sz = SHA1_BLOCK_SIZE;
  790. return 0;
  791. }
  792. static int safexcel_sha1_digest(struct ahash_request *areq)
  793. {
  794. int ret = safexcel_sha1_init(areq);
  795. if (ret)
  796. return ret;
  797. return safexcel_ahash_finup(areq);
  798. }
  799. static void safexcel_ahash_cra_exit(struct crypto_tfm *tfm)
  800. {
  801. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  802. struct safexcel_crypto_priv *priv = ctx->base.priv;
  803. int ret;
  804. /* context not allocated, skip invalidation */
  805. if (!ctx->base.ctxr)
  806. return;
  807. if (priv->flags & EIP197_TRC_CACHE) {
  808. ret = safexcel_ahash_exit_inv(tfm);
  809. if (ret)
  810. dev_warn(priv->dev, "hash: invalidation error %d\n", ret);
  811. } else {
  812. dma_pool_free(priv->context_pool, ctx->base.ctxr,
  813. ctx->base.ctxr_dma);
  814. }
  815. }
  816. struct safexcel_alg_template safexcel_alg_sha1 = {
  817. .type = SAFEXCEL_ALG_TYPE_AHASH,
  818. .algo_mask = SAFEXCEL_ALG_SHA1,
  819. .alg.ahash = {
  820. .init = safexcel_sha1_init,
  821. .update = safexcel_ahash_update,
  822. .final = safexcel_ahash_final,
  823. .finup = safexcel_ahash_finup,
  824. .digest = safexcel_sha1_digest,
  825. .export = safexcel_ahash_export,
  826. .import = safexcel_ahash_import,
  827. .halg = {
  828. .digestsize = SHA1_DIGEST_SIZE,
  829. .statesize = sizeof(struct safexcel_ahash_export_state),
  830. .base = {
  831. .cra_name = "sha1",
  832. .cra_driver_name = "safexcel-sha1",
  833. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  834. .cra_flags = CRYPTO_ALG_ASYNC |
  835. CRYPTO_ALG_ALLOCATES_MEMORY |
  836. CRYPTO_ALG_KERN_DRIVER_ONLY,
  837. .cra_blocksize = SHA1_BLOCK_SIZE,
  838. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  839. .cra_init = safexcel_ahash_cra_init,
  840. .cra_exit = safexcel_ahash_cra_exit,
  841. .cra_module = THIS_MODULE,
  842. },
  843. },
  844. },
  845. };
  846. static int safexcel_hmac_sha1_init(struct ahash_request *areq)
  847. {
  848. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  849. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  850. memset(req, 0, sizeof(*req));
  851. /* Start from ipad precompute */
  852. memcpy(req->state, &ctx->base.ipad, SHA1_DIGEST_SIZE);
  853. /* Already processed the key^ipad part now! */
  854. req->len = SHA1_BLOCK_SIZE;
  855. req->processed = SHA1_BLOCK_SIZE;
  856. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA1;
  857. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  858. req->state_sz = SHA1_DIGEST_SIZE;
  859. req->digest_sz = SHA1_DIGEST_SIZE;
  860. req->block_sz = SHA1_BLOCK_SIZE;
  861. req->hmac = true;
  862. return 0;
  863. }
  864. static int safexcel_hmac_sha1_digest(struct ahash_request *areq)
  865. {
  866. int ret = safexcel_hmac_sha1_init(areq);
  867. if (ret)
  868. return ret;
  869. return safexcel_ahash_finup(areq);
  870. }
  871. static int safexcel_hmac_init_pad(struct ahash_request *areq,
  872. unsigned int blocksize, const u8 *key,
  873. unsigned int keylen, u8 *ipad, u8 *opad)
  874. {
  875. DECLARE_CRYPTO_WAIT(result);
  876. struct scatterlist sg;
  877. int ret, i;
  878. u8 *keydup;
  879. if (keylen <= blocksize) {
  880. memcpy(ipad, key, keylen);
  881. } else {
  882. keydup = kmemdup(key, keylen, GFP_KERNEL);
  883. if (!keydup)
  884. return -ENOMEM;
  885. ahash_request_set_callback(areq, CRYPTO_TFM_REQ_MAY_BACKLOG,
  886. crypto_req_done, &result);
  887. sg_init_one(&sg, keydup, keylen);
  888. ahash_request_set_crypt(areq, &sg, ipad, keylen);
  889. ret = crypto_ahash_digest(areq);
  890. ret = crypto_wait_req(ret, &result);
  891. /* Avoid leaking */
  892. kfree_sensitive(keydup);
  893. if (ret)
  894. return ret;
  895. keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(areq));
  896. }
  897. memset(ipad + keylen, 0, blocksize - keylen);
  898. memcpy(opad, ipad, blocksize);
  899. for (i = 0; i < blocksize; i++) {
  900. ipad[i] ^= HMAC_IPAD_VALUE;
  901. opad[i] ^= HMAC_OPAD_VALUE;
  902. }
  903. return 0;
  904. }
  905. static int safexcel_hmac_init_iv(struct ahash_request *areq,
  906. unsigned int blocksize, u8 *pad, void *state)
  907. {
  908. struct safexcel_ahash_req *req;
  909. DECLARE_CRYPTO_WAIT(result);
  910. struct scatterlist sg;
  911. int ret;
  912. ahash_request_set_callback(areq, CRYPTO_TFM_REQ_MAY_BACKLOG,
  913. crypto_req_done, &result);
  914. sg_init_one(&sg, pad, blocksize);
  915. ahash_request_set_crypt(areq, &sg, pad, blocksize);
  916. ret = crypto_ahash_init(areq);
  917. if (ret)
  918. return ret;
  919. req = ahash_request_ctx_dma(areq);
  920. req->hmac = true;
  921. req->last_req = true;
  922. ret = crypto_ahash_update(areq);
  923. ret = crypto_wait_req(ret, &result);
  924. return ret ?: crypto_ahash_export(areq, state);
  925. }
  926. static int __safexcel_hmac_setkey(const char *alg, const u8 *key,
  927. unsigned int keylen,
  928. void *istate, void *ostate)
  929. {
  930. struct ahash_request *areq;
  931. struct crypto_ahash *tfm;
  932. unsigned int blocksize;
  933. u8 *ipad, *opad;
  934. int ret;
  935. tfm = crypto_alloc_ahash(alg, 0, 0);
  936. if (IS_ERR(tfm))
  937. return PTR_ERR(tfm);
  938. areq = ahash_request_alloc(tfm, GFP_KERNEL);
  939. if (!areq) {
  940. ret = -ENOMEM;
  941. goto free_ahash;
  942. }
  943. crypto_ahash_clear_flags(tfm, ~0);
  944. blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
  945. ipad = kcalloc(2, blocksize, GFP_KERNEL);
  946. if (!ipad) {
  947. ret = -ENOMEM;
  948. goto free_request;
  949. }
  950. opad = ipad + blocksize;
  951. ret = safexcel_hmac_init_pad(areq, blocksize, key, keylen, ipad, opad);
  952. if (ret)
  953. goto free_ipad;
  954. ret = safexcel_hmac_init_iv(areq, blocksize, ipad, istate);
  955. if (ret)
  956. goto free_ipad;
  957. ret = safexcel_hmac_init_iv(areq, blocksize, opad, ostate);
  958. free_ipad:
  959. kfree(ipad);
  960. free_request:
  961. ahash_request_free(areq);
  962. free_ahash:
  963. crypto_free_ahash(tfm);
  964. return ret;
  965. }
  966. int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key,
  967. unsigned int keylen, const char *alg,
  968. unsigned int state_sz)
  969. {
  970. struct safexcel_crypto_priv *priv = base->priv;
  971. struct safexcel_ahash_export_state istate, ostate;
  972. int ret;
  973. ret = __safexcel_hmac_setkey(alg, key, keylen, &istate, &ostate);
  974. if (ret)
  975. return ret;
  976. if (priv->flags & EIP197_TRC_CACHE && base->ctxr &&
  977. (memcmp(&base->ipad, istate.state, state_sz) ||
  978. memcmp(&base->opad, ostate.state, state_sz)))
  979. base->needs_inv = true;
  980. memcpy(&base->ipad, &istate.state, state_sz);
  981. memcpy(&base->opad, &ostate.state, state_sz);
  982. return 0;
  983. }
  984. static int safexcel_hmac_alg_setkey(struct crypto_ahash *tfm, const u8 *key,
  985. unsigned int keylen, const char *alg,
  986. unsigned int state_sz)
  987. {
  988. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  989. return safexcel_hmac_setkey(&ctx->base, key, keylen, alg, state_sz);
  990. }
  991. static int safexcel_hmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
  992. unsigned int keylen)
  993. {
  994. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sha1",
  995. SHA1_DIGEST_SIZE);
  996. }
  997. struct safexcel_alg_template safexcel_alg_hmac_sha1 = {
  998. .type = SAFEXCEL_ALG_TYPE_AHASH,
  999. .algo_mask = SAFEXCEL_ALG_SHA1,
  1000. .alg.ahash = {
  1001. .init = safexcel_hmac_sha1_init,
  1002. .update = safexcel_ahash_update,
  1003. .final = safexcel_ahash_final,
  1004. .finup = safexcel_ahash_finup,
  1005. .digest = safexcel_hmac_sha1_digest,
  1006. .setkey = safexcel_hmac_sha1_setkey,
  1007. .export = safexcel_ahash_export,
  1008. .import = safexcel_ahash_import,
  1009. .halg = {
  1010. .digestsize = SHA1_DIGEST_SIZE,
  1011. .statesize = sizeof(struct safexcel_ahash_export_state),
  1012. .base = {
  1013. .cra_name = "hmac(sha1)",
  1014. .cra_driver_name = "safexcel-hmac-sha1",
  1015. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1016. .cra_flags = CRYPTO_ALG_ASYNC |
  1017. CRYPTO_ALG_ALLOCATES_MEMORY |
  1018. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1019. .cra_blocksize = SHA1_BLOCK_SIZE,
  1020. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1021. .cra_init = safexcel_ahash_cra_init,
  1022. .cra_exit = safexcel_ahash_cra_exit,
  1023. .cra_module = THIS_MODULE,
  1024. },
  1025. },
  1026. },
  1027. };
  1028. static int safexcel_sha256_init(struct ahash_request *areq)
  1029. {
  1030. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1031. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1032. memset(req, 0, sizeof(*req));
  1033. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA256;
  1034. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1035. req->state_sz = SHA256_DIGEST_SIZE;
  1036. req->digest_sz = SHA256_DIGEST_SIZE;
  1037. req->block_sz = SHA256_BLOCK_SIZE;
  1038. return 0;
  1039. }
  1040. static int safexcel_sha256_digest(struct ahash_request *areq)
  1041. {
  1042. int ret = safexcel_sha256_init(areq);
  1043. if (ret)
  1044. return ret;
  1045. return safexcel_ahash_finup(areq);
  1046. }
  1047. struct safexcel_alg_template safexcel_alg_sha256 = {
  1048. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1049. .algo_mask = SAFEXCEL_ALG_SHA2_256,
  1050. .alg.ahash = {
  1051. .init = safexcel_sha256_init,
  1052. .update = safexcel_ahash_update,
  1053. .final = safexcel_ahash_final,
  1054. .finup = safexcel_ahash_finup,
  1055. .digest = safexcel_sha256_digest,
  1056. .export = safexcel_ahash_export,
  1057. .import = safexcel_ahash_import,
  1058. .halg = {
  1059. .digestsize = SHA256_DIGEST_SIZE,
  1060. .statesize = sizeof(struct safexcel_ahash_export_state),
  1061. .base = {
  1062. .cra_name = "sha256",
  1063. .cra_driver_name = "safexcel-sha256",
  1064. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1065. .cra_flags = CRYPTO_ALG_ASYNC |
  1066. CRYPTO_ALG_ALLOCATES_MEMORY |
  1067. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1068. .cra_blocksize = SHA256_BLOCK_SIZE,
  1069. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1070. .cra_init = safexcel_ahash_cra_init,
  1071. .cra_exit = safexcel_ahash_cra_exit,
  1072. .cra_module = THIS_MODULE,
  1073. },
  1074. },
  1075. },
  1076. };
  1077. static int safexcel_sha224_init(struct ahash_request *areq)
  1078. {
  1079. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1080. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1081. memset(req, 0, sizeof(*req));
  1082. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA224;
  1083. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1084. req->state_sz = SHA256_DIGEST_SIZE;
  1085. req->digest_sz = SHA256_DIGEST_SIZE;
  1086. req->block_sz = SHA256_BLOCK_SIZE;
  1087. return 0;
  1088. }
  1089. static int safexcel_sha224_digest(struct ahash_request *areq)
  1090. {
  1091. int ret = safexcel_sha224_init(areq);
  1092. if (ret)
  1093. return ret;
  1094. return safexcel_ahash_finup(areq);
  1095. }
  1096. struct safexcel_alg_template safexcel_alg_sha224 = {
  1097. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1098. .algo_mask = SAFEXCEL_ALG_SHA2_256,
  1099. .alg.ahash = {
  1100. .init = safexcel_sha224_init,
  1101. .update = safexcel_ahash_update,
  1102. .final = safexcel_ahash_final,
  1103. .finup = safexcel_ahash_finup,
  1104. .digest = safexcel_sha224_digest,
  1105. .export = safexcel_ahash_export,
  1106. .import = safexcel_ahash_import,
  1107. .halg = {
  1108. .digestsize = SHA224_DIGEST_SIZE,
  1109. .statesize = sizeof(struct safexcel_ahash_export_state),
  1110. .base = {
  1111. .cra_name = "sha224",
  1112. .cra_driver_name = "safexcel-sha224",
  1113. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1114. .cra_flags = CRYPTO_ALG_ASYNC |
  1115. CRYPTO_ALG_ALLOCATES_MEMORY |
  1116. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1117. .cra_blocksize = SHA224_BLOCK_SIZE,
  1118. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1119. .cra_init = safexcel_ahash_cra_init,
  1120. .cra_exit = safexcel_ahash_cra_exit,
  1121. .cra_module = THIS_MODULE,
  1122. },
  1123. },
  1124. },
  1125. };
  1126. static int safexcel_hmac_sha224_setkey(struct crypto_ahash *tfm, const u8 *key,
  1127. unsigned int keylen)
  1128. {
  1129. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sha224",
  1130. SHA256_DIGEST_SIZE);
  1131. }
  1132. static int safexcel_hmac_sha224_init(struct ahash_request *areq)
  1133. {
  1134. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1135. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1136. memset(req, 0, sizeof(*req));
  1137. /* Start from ipad precompute */
  1138. memcpy(req->state, &ctx->base.ipad, SHA256_DIGEST_SIZE);
  1139. /* Already processed the key^ipad part now! */
  1140. req->len = SHA256_BLOCK_SIZE;
  1141. req->processed = SHA256_BLOCK_SIZE;
  1142. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA224;
  1143. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1144. req->state_sz = SHA256_DIGEST_SIZE;
  1145. req->digest_sz = SHA256_DIGEST_SIZE;
  1146. req->block_sz = SHA256_BLOCK_SIZE;
  1147. req->hmac = true;
  1148. return 0;
  1149. }
  1150. static int safexcel_hmac_sha224_digest(struct ahash_request *areq)
  1151. {
  1152. int ret = safexcel_hmac_sha224_init(areq);
  1153. if (ret)
  1154. return ret;
  1155. return safexcel_ahash_finup(areq);
  1156. }
  1157. struct safexcel_alg_template safexcel_alg_hmac_sha224 = {
  1158. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1159. .algo_mask = SAFEXCEL_ALG_SHA2_256,
  1160. .alg.ahash = {
  1161. .init = safexcel_hmac_sha224_init,
  1162. .update = safexcel_ahash_update,
  1163. .final = safexcel_ahash_final,
  1164. .finup = safexcel_ahash_finup,
  1165. .digest = safexcel_hmac_sha224_digest,
  1166. .setkey = safexcel_hmac_sha224_setkey,
  1167. .export = safexcel_ahash_export,
  1168. .import = safexcel_ahash_import,
  1169. .halg = {
  1170. .digestsize = SHA224_DIGEST_SIZE,
  1171. .statesize = sizeof(struct safexcel_ahash_export_state),
  1172. .base = {
  1173. .cra_name = "hmac(sha224)",
  1174. .cra_driver_name = "safexcel-hmac-sha224",
  1175. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1176. .cra_flags = CRYPTO_ALG_ASYNC |
  1177. CRYPTO_ALG_ALLOCATES_MEMORY |
  1178. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1179. .cra_blocksize = SHA224_BLOCK_SIZE,
  1180. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1181. .cra_init = safexcel_ahash_cra_init,
  1182. .cra_exit = safexcel_ahash_cra_exit,
  1183. .cra_module = THIS_MODULE,
  1184. },
  1185. },
  1186. },
  1187. };
  1188. static int safexcel_hmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
  1189. unsigned int keylen)
  1190. {
  1191. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sha256",
  1192. SHA256_DIGEST_SIZE);
  1193. }
  1194. static int safexcel_hmac_sha256_init(struct ahash_request *areq)
  1195. {
  1196. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1197. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1198. memset(req, 0, sizeof(*req));
  1199. /* Start from ipad precompute */
  1200. memcpy(req->state, &ctx->base.ipad, SHA256_DIGEST_SIZE);
  1201. /* Already processed the key^ipad part now! */
  1202. req->len = SHA256_BLOCK_SIZE;
  1203. req->processed = SHA256_BLOCK_SIZE;
  1204. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA256;
  1205. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1206. req->state_sz = SHA256_DIGEST_SIZE;
  1207. req->digest_sz = SHA256_DIGEST_SIZE;
  1208. req->block_sz = SHA256_BLOCK_SIZE;
  1209. req->hmac = true;
  1210. return 0;
  1211. }
  1212. static int safexcel_hmac_sha256_digest(struct ahash_request *areq)
  1213. {
  1214. int ret = safexcel_hmac_sha256_init(areq);
  1215. if (ret)
  1216. return ret;
  1217. return safexcel_ahash_finup(areq);
  1218. }
  1219. struct safexcel_alg_template safexcel_alg_hmac_sha256 = {
  1220. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1221. .algo_mask = SAFEXCEL_ALG_SHA2_256,
  1222. .alg.ahash = {
  1223. .init = safexcel_hmac_sha256_init,
  1224. .update = safexcel_ahash_update,
  1225. .final = safexcel_ahash_final,
  1226. .finup = safexcel_ahash_finup,
  1227. .digest = safexcel_hmac_sha256_digest,
  1228. .setkey = safexcel_hmac_sha256_setkey,
  1229. .export = safexcel_ahash_export,
  1230. .import = safexcel_ahash_import,
  1231. .halg = {
  1232. .digestsize = SHA256_DIGEST_SIZE,
  1233. .statesize = sizeof(struct safexcel_ahash_export_state),
  1234. .base = {
  1235. .cra_name = "hmac(sha256)",
  1236. .cra_driver_name = "safexcel-hmac-sha256",
  1237. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1238. .cra_flags = CRYPTO_ALG_ASYNC |
  1239. CRYPTO_ALG_ALLOCATES_MEMORY |
  1240. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1241. .cra_blocksize = SHA256_BLOCK_SIZE,
  1242. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1243. .cra_init = safexcel_ahash_cra_init,
  1244. .cra_exit = safexcel_ahash_cra_exit,
  1245. .cra_module = THIS_MODULE,
  1246. },
  1247. },
  1248. },
  1249. };
  1250. static int safexcel_sha512_init(struct ahash_request *areq)
  1251. {
  1252. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1253. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1254. memset(req, 0, sizeof(*req));
  1255. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA512;
  1256. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1257. req->state_sz = SHA512_DIGEST_SIZE;
  1258. req->digest_sz = SHA512_DIGEST_SIZE;
  1259. req->block_sz = SHA512_BLOCK_SIZE;
  1260. return 0;
  1261. }
  1262. static int safexcel_sha512_digest(struct ahash_request *areq)
  1263. {
  1264. int ret = safexcel_sha512_init(areq);
  1265. if (ret)
  1266. return ret;
  1267. return safexcel_ahash_finup(areq);
  1268. }
  1269. struct safexcel_alg_template safexcel_alg_sha512 = {
  1270. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1271. .algo_mask = SAFEXCEL_ALG_SHA2_512,
  1272. .alg.ahash = {
  1273. .init = safexcel_sha512_init,
  1274. .update = safexcel_ahash_update,
  1275. .final = safexcel_ahash_final,
  1276. .finup = safexcel_ahash_finup,
  1277. .digest = safexcel_sha512_digest,
  1278. .export = safexcel_ahash_export,
  1279. .import = safexcel_ahash_import,
  1280. .halg = {
  1281. .digestsize = SHA512_DIGEST_SIZE,
  1282. .statesize = sizeof(struct safexcel_ahash_export_state),
  1283. .base = {
  1284. .cra_name = "sha512",
  1285. .cra_driver_name = "safexcel-sha512",
  1286. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1287. .cra_flags = CRYPTO_ALG_ASYNC |
  1288. CRYPTO_ALG_ALLOCATES_MEMORY |
  1289. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1290. .cra_blocksize = SHA512_BLOCK_SIZE,
  1291. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1292. .cra_init = safexcel_ahash_cra_init,
  1293. .cra_exit = safexcel_ahash_cra_exit,
  1294. .cra_module = THIS_MODULE,
  1295. },
  1296. },
  1297. },
  1298. };
  1299. static int safexcel_sha384_init(struct ahash_request *areq)
  1300. {
  1301. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1302. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1303. memset(req, 0, sizeof(*req));
  1304. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA384;
  1305. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1306. req->state_sz = SHA512_DIGEST_SIZE;
  1307. req->digest_sz = SHA512_DIGEST_SIZE;
  1308. req->block_sz = SHA512_BLOCK_SIZE;
  1309. return 0;
  1310. }
  1311. static int safexcel_sha384_digest(struct ahash_request *areq)
  1312. {
  1313. int ret = safexcel_sha384_init(areq);
  1314. if (ret)
  1315. return ret;
  1316. return safexcel_ahash_finup(areq);
  1317. }
  1318. struct safexcel_alg_template safexcel_alg_sha384 = {
  1319. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1320. .algo_mask = SAFEXCEL_ALG_SHA2_512,
  1321. .alg.ahash = {
  1322. .init = safexcel_sha384_init,
  1323. .update = safexcel_ahash_update,
  1324. .final = safexcel_ahash_final,
  1325. .finup = safexcel_ahash_finup,
  1326. .digest = safexcel_sha384_digest,
  1327. .export = safexcel_ahash_export,
  1328. .import = safexcel_ahash_import,
  1329. .halg = {
  1330. .digestsize = SHA384_DIGEST_SIZE,
  1331. .statesize = sizeof(struct safexcel_ahash_export_state),
  1332. .base = {
  1333. .cra_name = "sha384",
  1334. .cra_driver_name = "safexcel-sha384",
  1335. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1336. .cra_flags = CRYPTO_ALG_ASYNC |
  1337. CRYPTO_ALG_ALLOCATES_MEMORY |
  1338. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1339. .cra_blocksize = SHA384_BLOCK_SIZE,
  1340. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1341. .cra_init = safexcel_ahash_cra_init,
  1342. .cra_exit = safexcel_ahash_cra_exit,
  1343. .cra_module = THIS_MODULE,
  1344. },
  1345. },
  1346. },
  1347. };
  1348. static int safexcel_hmac_sha512_setkey(struct crypto_ahash *tfm, const u8 *key,
  1349. unsigned int keylen)
  1350. {
  1351. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sha512",
  1352. SHA512_DIGEST_SIZE);
  1353. }
  1354. static int safexcel_hmac_sha512_init(struct ahash_request *areq)
  1355. {
  1356. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1357. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1358. memset(req, 0, sizeof(*req));
  1359. /* Start from ipad precompute */
  1360. memcpy(req->state, &ctx->base.ipad, SHA512_DIGEST_SIZE);
  1361. /* Already processed the key^ipad part now! */
  1362. req->len = SHA512_BLOCK_SIZE;
  1363. req->processed = SHA512_BLOCK_SIZE;
  1364. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA512;
  1365. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1366. req->state_sz = SHA512_DIGEST_SIZE;
  1367. req->digest_sz = SHA512_DIGEST_SIZE;
  1368. req->block_sz = SHA512_BLOCK_SIZE;
  1369. req->hmac = true;
  1370. return 0;
  1371. }
  1372. static int safexcel_hmac_sha512_digest(struct ahash_request *areq)
  1373. {
  1374. int ret = safexcel_hmac_sha512_init(areq);
  1375. if (ret)
  1376. return ret;
  1377. return safexcel_ahash_finup(areq);
  1378. }
  1379. struct safexcel_alg_template safexcel_alg_hmac_sha512 = {
  1380. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1381. .algo_mask = SAFEXCEL_ALG_SHA2_512,
  1382. .alg.ahash = {
  1383. .init = safexcel_hmac_sha512_init,
  1384. .update = safexcel_ahash_update,
  1385. .final = safexcel_ahash_final,
  1386. .finup = safexcel_ahash_finup,
  1387. .digest = safexcel_hmac_sha512_digest,
  1388. .setkey = safexcel_hmac_sha512_setkey,
  1389. .export = safexcel_ahash_export,
  1390. .import = safexcel_ahash_import,
  1391. .halg = {
  1392. .digestsize = SHA512_DIGEST_SIZE,
  1393. .statesize = sizeof(struct safexcel_ahash_export_state),
  1394. .base = {
  1395. .cra_name = "hmac(sha512)",
  1396. .cra_driver_name = "safexcel-hmac-sha512",
  1397. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1398. .cra_flags = CRYPTO_ALG_ASYNC |
  1399. CRYPTO_ALG_ALLOCATES_MEMORY |
  1400. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1401. .cra_blocksize = SHA512_BLOCK_SIZE,
  1402. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1403. .cra_init = safexcel_ahash_cra_init,
  1404. .cra_exit = safexcel_ahash_cra_exit,
  1405. .cra_module = THIS_MODULE,
  1406. },
  1407. },
  1408. },
  1409. };
  1410. static int safexcel_hmac_sha384_setkey(struct crypto_ahash *tfm, const u8 *key,
  1411. unsigned int keylen)
  1412. {
  1413. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sha384",
  1414. SHA512_DIGEST_SIZE);
  1415. }
  1416. static int safexcel_hmac_sha384_init(struct ahash_request *areq)
  1417. {
  1418. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1419. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1420. memset(req, 0, sizeof(*req));
  1421. /* Start from ipad precompute */
  1422. memcpy(req->state, &ctx->base.ipad, SHA512_DIGEST_SIZE);
  1423. /* Already processed the key^ipad part now! */
  1424. req->len = SHA512_BLOCK_SIZE;
  1425. req->processed = SHA512_BLOCK_SIZE;
  1426. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA384;
  1427. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1428. req->state_sz = SHA512_DIGEST_SIZE;
  1429. req->digest_sz = SHA512_DIGEST_SIZE;
  1430. req->block_sz = SHA512_BLOCK_SIZE;
  1431. req->hmac = true;
  1432. return 0;
  1433. }
  1434. static int safexcel_hmac_sha384_digest(struct ahash_request *areq)
  1435. {
  1436. int ret = safexcel_hmac_sha384_init(areq);
  1437. if (ret)
  1438. return ret;
  1439. return safexcel_ahash_finup(areq);
  1440. }
  1441. struct safexcel_alg_template safexcel_alg_hmac_sha384 = {
  1442. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1443. .algo_mask = SAFEXCEL_ALG_SHA2_512,
  1444. .alg.ahash = {
  1445. .init = safexcel_hmac_sha384_init,
  1446. .update = safexcel_ahash_update,
  1447. .final = safexcel_ahash_final,
  1448. .finup = safexcel_ahash_finup,
  1449. .digest = safexcel_hmac_sha384_digest,
  1450. .setkey = safexcel_hmac_sha384_setkey,
  1451. .export = safexcel_ahash_export,
  1452. .import = safexcel_ahash_import,
  1453. .halg = {
  1454. .digestsize = SHA384_DIGEST_SIZE,
  1455. .statesize = sizeof(struct safexcel_ahash_export_state),
  1456. .base = {
  1457. .cra_name = "hmac(sha384)",
  1458. .cra_driver_name = "safexcel-hmac-sha384",
  1459. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1460. .cra_flags = CRYPTO_ALG_ASYNC |
  1461. CRYPTO_ALG_ALLOCATES_MEMORY |
  1462. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1463. .cra_blocksize = SHA384_BLOCK_SIZE,
  1464. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1465. .cra_init = safexcel_ahash_cra_init,
  1466. .cra_exit = safexcel_ahash_cra_exit,
  1467. .cra_module = THIS_MODULE,
  1468. },
  1469. },
  1470. },
  1471. };
  1472. static int safexcel_md5_init(struct ahash_request *areq)
  1473. {
  1474. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1475. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1476. memset(req, 0, sizeof(*req));
  1477. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_MD5;
  1478. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1479. req->state_sz = MD5_DIGEST_SIZE;
  1480. req->digest_sz = MD5_DIGEST_SIZE;
  1481. req->block_sz = MD5_HMAC_BLOCK_SIZE;
  1482. return 0;
  1483. }
  1484. static int safexcel_md5_digest(struct ahash_request *areq)
  1485. {
  1486. int ret = safexcel_md5_init(areq);
  1487. if (ret)
  1488. return ret;
  1489. return safexcel_ahash_finup(areq);
  1490. }
  1491. struct safexcel_alg_template safexcel_alg_md5 = {
  1492. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1493. .algo_mask = SAFEXCEL_ALG_MD5,
  1494. .alg.ahash = {
  1495. .init = safexcel_md5_init,
  1496. .update = safexcel_ahash_update,
  1497. .final = safexcel_ahash_final,
  1498. .finup = safexcel_ahash_finup,
  1499. .digest = safexcel_md5_digest,
  1500. .export = safexcel_ahash_export,
  1501. .import = safexcel_ahash_import,
  1502. .halg = {
  1503. .digestsize = MD5_DIGEST_SIZE,
  1504. .statesize = sizeof(struct safexcel_ahash_export_state),
  1505. .base = {
  1506. .cra_name = "md5",
  1507. .cra_driver_name = "safexcel-md5",
  1508. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1509. .cra_flags = CRYPTO_ALG_ASYNC |
  1510. CRYPTO_ALG_ALLOCATES_MEMORY |
  1511. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1512. .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  1513. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1514. .cra_init = safexcel_ahash_cra_init,
  1515. .cra_exit = safexcel_ahash_cra_exit,
  1516. .cra_module = THIS_MODULE,
  1517. },
  1518. },
  1519. },
  1520. };
  1521. static int safexcel_hmac_md5_init(struct ahash_request *areq)
  1522. {
  1523. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1524. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1525. memset(req, 0, sizeof(*req));
  1526. /* Start from ipad precompute */
  1527. memcpy(req->state, &ctx->base.ipad, MD5_DIGEST_SIZE);
  1528. /* Already processed the key^ipad part now! */
  1529. req->len = MD5_HMAC_BLOCK_SIZE;
  1530. req->processed = MD5_HMAC_BLOCK_SIZE;
  1531. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_MD5;
  1532. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1533. req->state_sz = MD5_DIGEST_SIZE;
  1534. req->digest_sz = MD5_DIGEST_SIZE;
  1535. req->block_sz = MD5_HMAC_BLOCK_SIZE;
  1536. req->len_is_le = true; /* MD5 is little endian! ... */
  1537. req->hmac = true;
  1538. return 0;
  1539. }
  1540. static int safexcel_hmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
  1541. unsigned int keylen)
  1542. {
  1543. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-md5",
  1544. MD5_DIGEST_SIZE);
  1545. }
  1546. static int safexcel_hmac_md5_digest(struct ahash_request *areq)
  1547. {
  1548. int ret = safexcel_hmac_md5_init(areq);
  1549. if (ret)
  1550. return ret;
  1551. return safexcel_ahash_finup(areq);
  1552. }
  1553. struct safexcel_alg_template safexcel_alg_hmac_md5 = {
  1554. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1555. .algo_mask = SAFEXCEL_ALG_MD5,
  1556. .alg.ahash = {
  1557. .init = safexcel_hmac_md5_init,
  1558. .update = safexcel_ahash_update,
  1559. .final = safexcel_ahash_final,
  1560. .finup = safexcel_ahash_finup,
  1561. .digest = safexcel_hmac_md5_digest,
  1562. .setkey = safexcel_hmac_md5_setkey,
  1563. .export = safexcel_ahash_export,
  1564. .import = safexcel_ahash_import,
  1565. .halg = {
  1566. .digestsize = MD5_DIGEST_SIZE,
  1567. .statesize = sizeof(struct safexcel_ahash_export_state),
  1568. .base = {
  1569. .cra_name = "hmac(md5)",
  1570. .cra_driver_name = "safexcel-hmac-md5",
  1571. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1572. .cra_flags = CRYPTO_ALG_ASYNC |
  1573. CRYPTO_ALG_ALLOCATES_MEMORY |
  1574. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1575. .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
  1576. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1577. .cra_init = safexcel_ahash_cra_init,
  1578. .cra_exit = safexcel_ahash_cra_exit,
  1579. .cra_module = THIS_MODULE,
  1580. },
  1581. },
  1582. },
  1583. };
  1584. static int safexcel_crc32_cra_init(struct crypto_tfm *tfm)
  1585. {
  1586. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  1587. int ret = safexcel_ahash_cra_init(tfm);
  1588. /* Default 'key' is all zeroes */
  1589. memset(&ctx->base.ipad, 0, sizeof(u32));
  1590. return ret;
  1591. }
  1592. static int safexcel_crc32_init(struct ahash_request *areq)
  1593. {
  1594. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1595. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1596. memset(req, 0, sizeof(*req));
  1597. /* Start from loaded key */
  1598. req->state[0] = cpu_to_le32(~ctx->base.ipad.word[0]);
  1599. /* Set processed to non-zero to enable invalidation detection */
  1600. req->len = sizeof(u32);
  1601. req->processed = sizeof(u32);
  1602. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_CRC32;
  1603. req->digest = CONTEXT_CONTROL_DIGEST_XCM;
  1604. req->state_sz = sizeof(u32);
  1605. req->digest_sz = sizeof(u32);
  1606. req->block_sz = sizeof(u32);
  1607. return 0;
  1608. }
  1609. static int safexcel_crc32_setkey(struct crypto_ahash *tfm, const u8 *key,
  1610. unsigned int keylen)
  1611. {
  1612. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
  1613. if (keylen != sizeof(u32))
  1614. return -EINVAL;
  1615. memcpy(&ctx->base.ipad, key, sizeof(u32));
  1616. return 0;
  1617. }
  1618. static int safexcel_crc32_digest(struct ahash_request *areq)
  1619. {
  1620. return safexcel_crc32_init(areq) ?: safexcel_ahash_finup(areq);
  1621. }
  1622. struct safexcel_alg_template safexcel_alg_crc32 = {
  1623. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1624. .algo_mask = 0,
  1625. .alg.ahash = {
  1626. .init = safexcel_crc32_init,
  1627. .update = safexcel_ahash_update,
  1628. .final = safexcel_ahash_final,
  1629. .finup = safexcel_ahash_finup,
  1630. .digest = safexcel_crc32_digest,
  1631. .setkey = safexcel_crc32_setkey,
  1632. .export = safexcel_ahash_export,
  1633. .import = safexcel_ahash_import,
  1634. .halg = {
  1635. .digestsize = sizeof(u32),
  1636. .statesize = sizeof(struct safexcel_ahash_export_state),
  1637. .base = {
  1638. .cra_name = "crc32",
  1639. .cra_driver_name = "safexcel-crc32",
  1640. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1641. .cra_flags = CRYPTO_ALG_OPTIONAL_KEY |
  1642. CRYPTO_ALG_ASYNC |
  1643. CRYPTO_ALG_ALLOCATES_MEMORY |
  1644. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1645. .cra_blocksize = 1,
  1646. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1647. .cra_init = safexcel_crc32_cra_init,
  1648. .cra_exit = safexcel_ahash_cra_exit,
  1649. .cra_module = THIS_MODULE,
  1650. },
  1651. },
  1652. },
  1653. };
  1654. static int safexcel_cbcmac_init(struct ahash_request *areq)
  1655. {
  1656. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1657. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1658. memset(req, 0, sizeof(*req));
  1659. /* Start from loaded keys */
  1660. memcpy(req->state, &ctx->base.ipad, ctx->key_sz);
  1661. /* Set processed to non-zero to enable invalidation detection */
  1662. req->len = AES_BLOCK_SIZE;
  1663. req->processed = AES_BLOCK_SIZE;
  1664. req->digest = CONTEXT_CONTROL_DIGEST_XCM;
  1665. req->state_sz = ctx->key_sz;
  1666. req->digest_sz = AES_BLOCK_SIZE;
  1667. req->block_sz = AES_BLOCK_SIZE;
  1668. req->xcbcmac = true;
  1669. return 0;
  1670. }
  1671. static int safexcel_cbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  1672. unsigned int len)
  1673. {
  1674. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
  1675. struct crypto_aes_ctx aes;
  1676. int ret, i;
  1677. ret = aes_expandkey(&aes, key, len);
  1678. if (ret)
  1679. return ret;
  1680. memset(&ctx->base.ipad, 0, 2 * AES_BLOCK_SIZE);
  1681. for (i = 0; i < len / sizeof(u32); i++)
  1682. ctx->base.ipad.be[i + 8] = cpu_to_be32(aes.key_enc[i]);
  1683. if (len == AES_KEYSIZE_192) {
  1684. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC192;
  1685. ctx->key_sz = AES_MAX_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1686. } else if (len == AES_KEYSIZE_256) {
  1687. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC256;
  1688. ctx->key_sz = AES_MAX_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1689. } else {
  1690. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC128;
  1691. ctx->key_sz = AES_MIN_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1692. }
  1693. ctx->cbcmac = true;
  1694. memzero_explicit(&aes, sizeof(aes));
  1695. return 0;
  1696. }
  1697. static int safexcel_cbcmac_digest(struct ahash_request *areq)
  1698. {
  1699. return safexcel_cbcmac_init(areq) ?: safexcel_ahash_finup(areq);
  1700. }
  1701. struct safexcel_alg_template safexcel_alg_cbcmac = {
  1702. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1703. .algo_mask = 0,
  1704. .alg.ahash = {
  1705. .init = safexcel_cbcmac_init,
  1706. .update = safexcel_ahash_update,
  1707. .final = safexcel_ahash_final,
  1708. .finup = safexcel_ahash_finup,
  1709. .digest = safexcel_cbcmac_digest,
  1710. .setkey = safexcel_cbcmac_setkey,
  1711. .export = safexcel_ahash_export,
  1712. .import = safexcel_ahash_import,
  1713. .halg = {
  1714. .digestsize = AES_BLOCK_SIZE,
  1715. .statesize = sizeof(struct safexcel_ahash_export_state),
  1716. .base = {
  1717. .cra_name = "cbcmac(aes)",
  1718. .cra_driver_name = "safexcel-cbcmac-aes",
  1719. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1720. .cra_flags = CRYPTO_ALG_ASYNC |
  1721. CRYPTO_ALG_ALLOCATES_MEMORY |
  1722. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1723. .cra_blocksize = 1,
  1724. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1725. .cra_init = safexcel_ahash_cra_init,
  1726. .cra_exit = safexcel_ahash_cra_exit,
  1727. .cra_module = THIS_MODULE,
  1728. },
  1729. },
  1730. },
  1731. };
  1732. static int safexcel_xcbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  1733. unsigned int len)
  1734. {
  1735. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
  1736. u32 key_tmp[3 * AES_BLOCK_SIZE / sizeof(u32)];
  1737. int ret, i;
  1738. ret = aes_expandkey(ctx->aes, key, len);
  1739. if (ret)
  1740. return ret;
  1741. /* precompute the XCBC key material */
  1742. aes_encrypt(ctx->aes, (u8 *)key_tmp + 2 * AES_BLOCK_SIZE,
  1743. "\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1\x1");
  1744. aes_encrypt(ctx->aes, (u8 *)key_tmp,
  1745. "\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2\x2");
  1746. aes_encrypt(ctx->aes, (u8 *)key_tmp + AES_BLOCK_SIZE,
  1747. "\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3\x3");
  1748. for (i = 0; i < 3 * AES_BLOCK_SIZE / sizeof(u32); i++)
  1749. ctx->base.ipad.word[i] = swab32(key_tmp[i]);
  1750. ret = aes_expandkey(ctx->aes,
  1751. (u8 *)key_tmp + 2 * AES_BLOCK_SIZE,
  1752. AES_MIN_KEY_SIZE);
  1753. if (ret)
  1754. return ret;
  1755. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC128;
  1756. ctx->key_sz = AES_MIN_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1757. ctx->cbcmac = false;
  1758. return 0;
  1759. }
  1760. static int safexcel_xcbcmac_cra_init(struct crypto_tfm *tfm)
  1761. {
  1762. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  1763. safexcel_ahash_cra_init(tfm);
  1764. ctx->aes = kmalloc(sizeof(*ctx->aes), GFP_KERNEL);
  1765. return ctx->aes == NULL ? -ENOMEM : 0;
  1766. }
  1767. static void safexcel_xcbcmac_cra_exit(struct crypto_tfm *tfm)
  1768. {
  1769. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  1770. kfree(ctx->aes);
  1771. safexcel_ahash_cra_exit(tfm);
  1772. }
  1773. struct safexcel_alg_template safexcel_alg_xcbcmac = {
  1774. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1775. .algo_mask = 0,
  1776. .alg.ahash = {
  1777. .init = safexcel_cbcmac_init,
  1778. .update = safexcel_ahash_update,
  1779. .final = safexcel_ahash_final,
  1780. .finup = safexcel_ahash_finup,
  1781. .digest = safexcel_cbcmac_digest,
  1782. .setkey = safexcel_xcbcmac_setkey,
  1783. .export = safexcel_ahash_export,
  1784. .import = safexcel_ahash_import,
  1785. .halg = {
  1786. .digestsize = AES_BLOCK_SIZE,
  1787. .statesize = sizeof(struct safexcel_ahash_export_state),
  1788. .base = {
  1789. .cra_name = "xcbc(aes)",
  1790. .cra_driver_name = "safexcel-xcbc-aes",
  1791. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1792. .cra_flags = CRYPTO_ALG_ASYNC |
  1793. CRYPTO_ALG_ALLOCATES_MEMORY |
  1794. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1795. .cra_blocksize = AES_BLOCK_SIZE,
  1796. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1797. .cra_init = safexcel_xcbcmac_cra_init,
  1798. .cra_exit = safexcel_xcbcmac_cra_exit,
  1799. .cra_module = THIS_MODULE,
  1800. },
  1801. },
  1802. },
  1803. };
  1804. static int safexcel_cmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  1805. unsigned int len)
  1806. {
  1807. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
  1808. __be64 consts[4];
  1809. u64 _const[2];
  1810. u8 msb_mask, gfmask;
  1811. int ret, i;
  1812. /* precompute the CMAC key material */
  1813. ret = aes_expandkey(ctx->aes, key, len);
  1814. if (ret)
  1815. return ret;
  1816. for (i = 0; i < len / sizeof(u32); i++)
  1817. ctx->base.ipad.word[i + 8] = swab32(ctx->aes->key_enc[i]);
  1818. /* code below borrowed from crypto/cmac.c */
  1819. /* encrypt the zero block */
  1820. memset(consts, 0, AES_BLOCK_SIZE);
  1821. aes_encrypt(ctx->aes, (u8 *)consts, (u8 *)consts);
  1822. gfmask = 0x87;
  1823. _const[0] = be64_to_cpu(consts[1]);
  1824. _const[1] = be64_to_cpu(consts[0]);
  1825. /* gf(2^128) multiply zero-ciphertext with u and u^2 */
  1826. for (i = 0; i < 4; i += 2) {
  1827. msb_mask = ((s64)_const[1] >> 63) & gfmask;
  1828. _const[1] = (_const[1] << 1) | (_const[0] >> 63);
  1829. _const[0] = (_const[0] << 1) ^ msb_mask;
  1830. consts[i + 0] = cpu_to_be64(_const[1]);
  1831. consts[i + 1] = cpu_to_be64(_const[0]);
  1832. }
  1833. /* end of code borrowed from crypto/cmac.c */
  1834. for (i = 0; i < 2 * AES_BLOCK_SIZE / sizeof(u32); i++)
  1835. ctx->base.ipad.be[i] = cpu_to_be32(((u32 *)consts)[i]);
  1836. if (len == AES_KEYSIZE_192) {
  1837. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC192;
  1838. ctx->key_sz = AES_MAX_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1839. } else if (len == AES_KEYSIZE_256) {
  1840. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC256;
  1841. ctx->key_sz = AES_MAX_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1842. } else {
  1843. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC128;
  1844. ctx->key_sz = AES_MIN_KEY_SIZE + 2 * AES_BLOCK_SIZE;
  1845. }
  1846. ctx->cbcmac = false;
  1847. return 0;
  1848. }
  1849. struct safexcel_alg_template safexcel_alg_cmac = {
  1850. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1851. .algo_mask = 0,
  1852. .alg.ahash = {
  1853. .init = safexcel_cbcmac_init,
  1854. .update = safexcel_ahash_update,
  1855. .final = safexcel_ahash_final,
  1856. .finup = safexcel_ahash_finup,
  1857. .digest = safexcel_cbcmac_digest,
  1858. .setkey = safexcel_cmac_setkey,
  1859. .export = safexcel_ahash_export,
  1860. .import = safexcel_ahash_import,
  1861. .halg = {
  1862. .digestsize = AES_BLOCK_SIZE,
  1863. .statesize = sizeof(struct safexcel_ahash_export_state),
  1864. .base = {
  1865. .cra_name = "cmac(aes)",
  1866. .cra_driver_name = "safexcel-cmac-aes",
  1867. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1868. .cra_flags = CRYPTO_ALG_ASYNC |
  1869. CRYPTO_ALG_ALLOCATES_MEMORY |
  1870. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1871. .cra_blocksize = AES_BLOCK_SIZE,
  1872. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1873. .cra_init = safexcel_xcbcmac_cra_init,
  1874. .cra_exit = safexcel_xcbcmac_cra_exit,
  1875. .cra_module = THIS_MODULE,
  1876. },
  1877. },
  1878. },
  1879. };
  1880. static int safexcel_sm3_init(struct ahash_request *areq)
  1881. {
  1882. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1883. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1884. memset(req, 0, sizeof(*req));
  1885. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SM3;
  1886. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1887. req->state_sz = SM3_DIGEST_SIZE;
  1888. req->digest_sz = SM3_DIGEST_SIZE;
  1889. req->block_sz = SM3_BLOCK_SIZE;
  1890. return 0;
  1891. }
  1892. static int safexcel_sm3_digest(struct ahash_request *areq)
  1893. {
  1894. int ret = safexcel_sm3_init(areq);
  1895. if (ret)
  1896. return ret;
  1897. return safexcel_ahash_finup(areq);
  1898. }
  1899. struct safexcel_alg_template safexcel_alg_sm3 = {
  1900. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1901. .algo_mask = SAFEXCEL_ALG_SM3,
  1902. .alg.ahash = {
  1903. .init = safexcel_sm3_init,
  1904. .update = safexcel_ahash_update,
  1905. .final = safexcel_ahash_final,
  1906. .finup = safexcel_ahash_finup,
  1907. .digest = safexcel_sm3_digest,
  1908. .export = safexcel_ahash_export,
  1909. .import = safexcel_ahash_import,
  1910. .halg = {
  1911. .digestsize = SM3_DIGEST_SIZE,
  1912. .statesize = sizeof(struct safexcel_ahash_export_state),
  1913. .base = {
  1914. .cra_name = "sm3",
  1915. .cra_driver_name = "safexcel-sm3",
  1916. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1917. .cra_flags = CRYPTO_ALG_ASYNC |
  1918. CRYPTO_ALG_ALLOCATES_MEMORY |
  1919. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1920. .cra_blocksize = SM3_BLOCK_SIZE,
  1921. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1922. .cra_init = safexcel_ahash_cra_init,
  1923. .cra_exit = safexcel_ahash_cra_exit,
  1924. .cra_module = THIS_MODULE,
  1925. },
  1926. },
  1927. },
  1928. };
  1929. static int safexcel_hmac_sm3_setkey(struct crypto_ahash *tfm, const u8 *key,
  1930. unsigned int keylen)
  1931. {
  1932. return safexcel_hmac_alg_setkey(tfm, key, keylen, "safexcel-sm3",
  1933. SM3_DIGEST_SIZE);
  1934. }
  1935. static int safexcel_hmac_sm3_init(struct ahash_request *areq)
  1936. {
  1937. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(areq));
  1938. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1939. memset(req, 0, sizeof(*req));
  1940. /* Start from ipad precompute */
  1941. memcpy(req->state, &ctx->base.ipad, SM3_DIGEST_SIZE);
  1942. /* Already processed the key^ipad part now! */
  1943. req->len = SM3_BLOCK_SIZE;
  1944. req->processed = SM3_BLOCK_SIZE;
  1945. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SM3;
  1946. req->digest = CONTEXT_CONTROL_DIGEST_PRECOMPUTED;
  1947. req->state_sz = SM3_DIGEST_SIZE;
  1948. req->digest_sz = SM3_DIGEST_SIZE;
  1949. req->block_sz = SM3_BLOCK_SIZE;
  1950. req->hmac = true;
  1951. return 0;
  1952. }
  1953. static int safexcel_hmac_sm3_digest(struct ahash_request *areq)
  1954. {
  1955. int ret = safexcel_hmac_sm3_init(areq);
  1956. if (ret)
  1957. return ret;
  1958. return safexcel_ahash_finup(areq);
  1959. }
  1960. struct safexcel_alg_template safexcel_alg_hmac_sm3 = {
  1961. .type = SAFEXCEL_ALG_TYPE_AHASH,
  1962. .algo_mask = SAFEXCEL_ALG_SM3,
  1963. .alg.ahash = {
  1964. .init = safexcel_hmac_sm3_init,
  1965. .update = safexcel_ahash_update,
  1966. .final = safexcel_ahash_final,
  1967. .finup = safexcel_ahash_finup,
  1968. .digest = safexcel_hmac_sm3_digest,
  1969. .setkey = safexcel_hmac_sm3_setkey,
  1970. .export = safexcel_ahash_export,
  1971. .import = safexcel_ahash_import,
  1972. .halg = {
  1973. .digestsize = SM3_DIGEST_SIZE,
  1974. .statesize = sizeof(struct safexcel_ahash_export_state),
  1975. .base = {
  1976. .cra_name = "hmac(sm3)",
  1977. .cra_driver_name = "safexcel-hmac-sm3",
  1978. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  1979. .cra_flags = CRYPTO_ALG_ASYNC |
  1980. CRYPTO_ALG_ALLOCATES_MEMORY |
  1981. CRYPTO_ALG_KERN_DRIVER_ONLY,
  1982. .cra_blocksize = SM3_BLOCK_SIZE,
  1983. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  1984. .cra_init = safexcel_ahash_cra_init,
  1985. .cra_exit = safexcel_ahash_cra_exit,
  1986. .cra_module = THIS_MODULE,
  1987. },
  1988. },
  1989. },
  1990. };
  1991. static int safexcel_sha3_224_init(struct ahash_request *areq)
  1992. {
  1993. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  1994. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  1995. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  1996. memset(req, 0, sizeof(*req));
  1997. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224;
  1998. req->digest = CONTEXT_CONTROL_DIGEST_INITIAL;
  1999. req->state_sz = SHA3_224_DIGEST_SIZE;
  2000. req->digest_sz = SHA3_224_DIGEST_SIZE;
  2001. req->block_sz = SHA3_224_BLOCK_SIZE;
  2002. ctx->do_fallback = false;
  2003. ctx->fb_init_done = false;
  2004. return 0;
  2005. }
  2006. static int safexcel_sha3_fbcheck(struct ahash_request *req)
  2007. {
  2008. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2009. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2010. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2011. int ret = 0;
  2012. if (ctx->do_fallback) {
  2013. ahash_request_set_tfm(subreq, ctx->fback);
  2014. ahash_request_set_callback(subreq, req->base.flags,
  2015. req->base.complete, req->base.data);
  2016. ahash_request_set_crypt(subreq, req->src, req->result,
  2017. req->nbytes);
  2018. if (!ctx->fb_init_done) {
  2019. if (ctx->fb_do_setkey) {
  2020. /* Set fallback cipher HMAC key */
  2021. u8 key[SHA3_224_BLOCK_SIZE];
  2022. memcpy(key, &ctx->base.ipad,
  2023. crypto_ahash_blocksize(ctx->fback) / 2);
  2024. memcpy(key +
  2025. crypto_ahash_blocksize(ctx->fback) / 2,
  2026. &ctx->base.opad,
  2027. crypto_ahash_blocksize(ctx->fback) / 2);
  2028. ret = crypto_ahash_setkey(ctx->fback, key,
  2029. crypto_ahash_blocksize(ctx->fback));
  2030. memzero_explicit(key,
  2031. crypto_ahash_blocksize(ctx->fback));
  2032. ctx->fb_do_setkey = false;
  2033. }
  2034. ret = ret ?: crypto_ahash_init(subreq);
  2035. ctx->fb_init_done = true;
  2036. }
  2037. }
  2038. return ret;
  2039. }
  2040. static int safexcel_sha3_update(struct ahash_request *req)
  2041. {
  2042. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2043. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2044. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2045. ctx->do_fallback = true;
  2046. return safexcel_sha3_fbcheck(req) ?: crypto_ahash_update(subreq);
  2047. }
  2048. static int safexcel_sha3_final(struct ahash_request *req)
  2049. {
  2050. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2051. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2052. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2053. ctx->do_fallback = true;
  2054. return safexcel_sha3_fbcheck(req) ?: crypto_ahash_final(subreq);
  2055. }
  2056. static int safexcel_sha3_finup(struct ahash_request *req)
  2057. {
  2058. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2059. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2060. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2061. ctx->do_fallback |= !req->nbytes;
  2062. if (ctx->do_fallback)
  2063. /* Update or ex/import happened or len 0, cannot use the HW */
  2064. return safexcel_sha3_fbcheck(req) ?:
  2065. crypto_ahash_finup(subreq);
  2066. else
  2067. return safexcel_ahash_finup(req);
  2068. }
  2069. static int safexcel_sha3_digest_fallback(struct ahash_request *req)
  2070. {
  2071. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2072. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2073. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2074. ctx->do_fallback = true;
  2075. ctx->fb_init_done = false;
  2076. return safexcel_sha3_fbcheck(req) ?: crypto_ahash_finup(subreq);
  2077. }
  2078. static int safexcel_sha3_224_digest(struct ahash_request *req)
  2079. {
  2080. if (req->nbytes)
  2081. return safexcel_sha3_224_init(req) ?: safexcel_ahash_finup(req);
  2082. /* HW cannot do zero length hash, use fallback instead */
  2083. return safexcel_sha3_digest_fallback(req);
  2084. }
  2085. static int safexcel_sha3_export(struct ahash_request *req, void *out)
  2086. {
  2087. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2088. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2089. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2090. ctx->do_fallback = true;
  2091. return safexcel_sha3_fbcheck(req) ?: crypto_ahash_export(subreq, out);
  2092. }
  2093. static int safexcel_sha3_import(struct ahash_request *req, const void *in)
  2094. {
  2095. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  2096. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2097. struct ahash_request *subreq = ahash_request_ctx_dma(req);
  2098. ctx->do_fallback = true;
  2099. return safexcel_sha3_fbcheck(req) ?: crypto_ahash_import(subreq, in);
  2100. // return safexcel_ahash_import(req, in);
  2101. }
  2102. static int safexcel_sha3_cra_init(struct crypto_tfm *tfm)
  2103. {
  2104. struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
  2105. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  2106. safexcel_ahash_cra_init(tfm);
  2107. /* Allocate fallback implementation */
  2108. ctx->fback = crypto_alloc_ahash(crypto_tfm_alg_name(tfm), 0,
  2109. CRYPTO_ALG_ASYNC |
  2110. CRYPTO_ALG_NEED_FALLBACK);
  2111. if (IS_ERR(ctx->fback))
  2112. return PTR_ERR(ctx->fback);
  2113. /* Update statesize from fallback algorithm! */
  2114. crypto_hash_alg_common(ahash)->statesize =
  2115. crypto_ahash_statesize(ctx->fback);
  2116. crypto_ahash_set_reqsize_dma(
  2117. ahash, max(sizeof(struct safexcel_ahash_req),
  2118. sizeof(struct ahash_request) +
  2119. crypto_ahash_reqsize(ctx->fback)));
  2120. return 0;
  2121. }
  2122. static void safexcel_sha3_cra_exit(struct crypto_tfm *tfm)
  2123. {
  2124. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  2125. crypto_free_ahash(ctx->fback);
  2126. safexcel_ahash_cra_exit(tfm);
  2127. }
  2128. struct safexcel_alg_template safexcel_alg_sha3_224 = {
  2129. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2130. .algo_mask = SAFEXCEL_ALG_SHA3,
  2131. .alg.ahash = {
  2132. .init = safexcel_sha3_224_init,
  2133. .update = safexcel_sha3_update,
  2134. .final = safexcel_sha3_final,
  2135. .finup = safexcel_sha3_finup,
  2136. .digest = safexcel_sha3_224_digest,
  2137. .export = safexcel_sha3_export,
  2138. .import = safexcel_sha3_import,
  2139. .halg = {
  2140. .digestsize = SHA3_224_DIGEST_SIZE,
  2141. .statesize = sizeof(struct safexcel_ahash_export_state),
  2142. .base = {
  2143. .cra_name = "sha3-224",
  2144. .cra_driver_name = "safexcel-sha3-224",
  2145. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2146. .cra_flags = CRYPTO_ALG_ASYNC |
  2147. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2148. CRYPTO_ALG_NEED_FALLBACK,
  2149. .cra_blocksize = SHA3_224_BLOCK_SIZE,
  2150. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2151. .cra_init = safexcel_sha3_cra_init,
  2152. .cra_exit = safexcel_sha3_cra_exit,
  2153. .cra_module = THIS_MODULE,
  2154. },
  2155. },
  2156. },
  2157. };
  2158. static int safexcel_sha3_256_init(struct ahash_request *areq)
  2159. {
  2160. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2161. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2162. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2163. memset(req, 0, sizeof(*req));
  2164. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256;
  2165. req->digest = CONTEXT_CONTROL_DIGEST_INITIAL;
  2166. req->state_sz = SHA3_256_DIGEST_SIZE;
  2167. req->digest_sz = SHA3_256_DIGEST_SIZE;
  2168. req->block_sz = SHA3_256_BLOCK_SIZE;
  2169. ctx->do_fallback = false;
  2170. ctx->fb_init_done = false;
  2171. return 0;
  2172. }
  2173. static int safexcel_sha3_256_digest(struct ahash_request *req)
  2174. {
  2175. if (req->nbytes)
  2176. return safexcel_sha3_256_init(req) ?: safexcel_ahash_finup(req);
  2177. /* HW cannot do zero length hash, use fallback instead */
  2178. return safexcel_sha3_digest_fallback(req);
  2179. }
  2180. struct safexcel_alg_template safexcel_alg_sha3_256 = {
  2181. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2182. .algo_mask = SAFEXCEL_ALG_SHA3,
  2183. .alg.ahash = {
  2184. .init = safexcel_sha3_256_init,
  2185. .update = safexcel_sha3_update,
  2186. .final = safexcel_sha3_final,
  2187. .finup = safexcel_sha3_finup,
  2188. .digest = safexcel_sha3_256_digest,
  2189. .export = safexcel_sha3_export,
  2190. .import = safexcel_sha3_import,
  2191. .halg = {
  2192. .digestsize = SHA3_256_DIGEST_SIZE,
  2193. .statesize = sizeof(struct safexcel_ahash_export_state),
  2194. .base = {
  2195. .cra_name = "sha3-256",
  2196. .cra_driver_name = "safexcel-sha3-256",
  2197. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2198. .cra_flags = CRYPTO_ALG_ASYNC |
  2199. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2200. CRYPTO_ALG_NEED_FALLBACK,
  2201. .cra_blocksize = SHA3_256_BLOCK_SIZE,
  2202. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2203. .cra_init = safexcel_sha3_cra_init,
  2204. .cra_exit = safexcel_sha3_cra_exit,
  2205. .cra_module = THIS_MODULE,
  2206. },
  2207. },
  2208. },
  2209. };
  2210. static int safexcel_sha3_384_init(struct ahash_request *areq)
  2211. {
  2212. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2213. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2214. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2215. memset(req, 0, sizeof(*req));
  2216. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384;
  2217. req->digest = CONTEXT_CONTROL_DIGEST_INITIAL;
  2218. req->state_sz = SHA3_384_DIGEST_SIZE;
  2219. req->digest_sz = SHA3_384_DIGEST_SIZE;
  2220. req->block_sz = SHA3_384_BLOCK_SIZE;
  2221. ctx->do_fallback = false;
  2222. ctx->fb_init_done = false;
  2223. return 0;
  2224. }
  2225. static int safexcel_sha3_384_digest(struct ahash_request *req)
  2226. {
  2227. if (req->nbytes)
  2228. return safexcel_sha3_384_init(req) ?: safexcel_ahash_finup(req);
  2229. /* HW cannot do zero length hash, use fallback instead */
  2230. return safexcel_sha3_digest_fallback(req);
  2231. }
  2232. struct safexcel_alg_template safexcel_alg_sha3_384 = {
  2233. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2234. .algo_mask = SAFEXCEL_ALG_SHA3,
  2235. .alg.ahash = {
  2236. .init = safexcel_sha3_384_init,
  2237. .update = safexcel_sha3_update,
  2238. .final = safexcel_sha3_final,
  2239. .finup = safexcel_sha3_finup,
  2240. .digest = safexcel_sha3_384_digest,
  2241. .export = safexcel_sha3_export,
  2242. .import = safexcel_sha3_import,
  2243. .halg = {
  2244. .digestsize = SHA3_384_DIGEST_SIZE,
  2245. .statesize = sizeof(struct safexcel_ahash_export_state),
  2246. .base = {
  2247. .cra_name = "sha3-384",
  2248. .cra_driver_name = "safexcel-sha3-384",
  2249. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2250. .cra_flags = CRYPTO_ALG_ASYNC |
  2251. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2252. CRYPTO_ALG_NEED_FALLBACK,
  2253. .cra_blocksize = SHA3_384_BLOCK_SIZE,
  2254. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2255. .cra_init = safexcel_sha3_cra_init,
  2256. .cra_exit = safexcel_sha3_cra_exit,
  2257. .cra_module = THIS_MODULE,
  2258. },
  2259. },
  2260. },
  2261. };
  2262. static int safexcel_sha3_512_init(struct ahash_request *areq)
  2263. {
  2264. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2265. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2266. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2267. memset(req, 0, sizeof(*req));
  2268. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512;
  2269. req->digest = CONTEXT_CONTROL_DIGEST_INITIAL;
  2270. req->state_sz = SHA3_512_DIGEST_SIZE;
  2271. req->digest_sz = SHA3_512_DIGEST_SIZE;
  2272. req->block_sz = SHA3_512_BLOCK_SIZE;
  2273. ctx->do_fallback = false;
  2274. ctx->fb_init_done = false;
  2275. return 0;
  2276. }
  2277. static int safexcel_sha3_512_digest(struct ahash_request *req)
  2278. {
  2279. if (req->nbytes)
  2280. return safexcel_sha3_512_init(req) ?: safexcel_ahash_finup(req);
  2281. /* HW cannot do zero length hash, use fallback instead */
  2282. return safexcel_sha3_digest_fallback(req);
  2283. }
  2284. struct safexcel_alg_template safexcel_alg_sha3_512 = {
  2285. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2286. .algo_mask = SAFEXCEL_ALG_SHA3,
  2287. .alg.ahash = {
  2288. .init = safexcel_sha3_512_init,
  2289. .update = safexcel_sha3_update,
  2290. .final = safexcel_sha3_final,
  2291. .finup = safexcel_sha3_finup,
  2292. .digest = safexcel_sha3_512_digest,
  2293. .export = safexcel_sha3_export,
  2294. .import = safexcel_sha3_import,
  2295. .halg = {
  2296. .digestsize = SHA3_512_DIGEST_SIZE,
  2297. .statesize = sizeof(struct safexcel_ahash_export_state),
  2298. .base = {
  2299. .cra_name = "sha3-512",
  2300. .cra_driver_name = "safexcel-sha3-512",
  2301. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2302. .cra_flags = CRYPTO_ALG_ASYNC |
  2303. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2304. CRYPTO_ALG_NEED_FALLBACK,
  2305. .cra_blocksize = SHA3_512_BLOCK_SIZE,
  2306. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2307. .cra_init = safexcel_sha3_cra_init,
  2308. .cra_exit = safexcel_sha3_cra_exit,
  2309. .cra_module = THIS_MODULE,
  2310. },
  2311. },
  2312. },
  2313. };
  2314. static int safexcel_hmac_sha3_cra_init(struct crypto_tfm *tfm, const char *alg)
  2315. {
  2316. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  2317. int ret;
  2318. ret = safexcel_sha3_cra_init(tfm);
  2319. if (ret)
  2320. return ret;
  2321. /* Allocate precalc basic digest implementation */
  2322. ctx->shpre = crypto_alloc_shash(alg, 0, CRYPTO_ALG_NEED_FALLBACK);
  2323. if (IS_ERR(ctx->shpre))
  2324. return PTR_ERR(ctx->shpre);
  2325. ctx->shdesc = kmalloc(sizeof(*ctx->shdesc) +
  2326. crypto_shash_descsize(ctx->shpre), GFP_KERNEL);
  2327. if (!ctx->shdesc) {
  2328. crypto_free_shash(ctx->shpre);
  2329. return -ENOMEM;
  2330. }
  2331. ctx->shdesc->tfm = ctx->shpre;
  2332. return 0;
  2333. }
  2334. static void safexcel_hmac_sha3_cra_exit(struct crypto_tfm *tfm)
  2335. {
  2336. struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(tfm);
  2337. crypto_free_ahash(ctx->fback);
  2338. crypto_free_shash(ctx->shpre);
  2339. kfree(ctx->shdesc);
  2340. safexcel_ahash_cra_exit(tfm);
  2341. }
  2342. static int safexcel_hmac_sha3_setkey(struct crypto_ahash *tfm, const u8 *key,
  2343. unsigned int keylen)
  2344. {
  2345. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2346. int ret = 0;
  2347. if (keylen > crypto_ahash_blocksize(tfm)) {
  2348. /*
  2349. * If the key is larger than the blocksize, then hash it
  2350. * first using our fallback cipher
  2351. */
  2352. ret = crypto_shash_digest(ctx->shdesc, key, keylen,
  2353. ctx->base.ipad.byte);
  2354. keylen = crypto_shash_digestsize(ctx->shpre);
  2355. /*
  2356. * If the digest is larger than half the blocksize, we need to
  2357. * move the rest to opad due to the way our HMAC infra works.
  2358. */
  2359. if (keylen > crypto_ahash_blocksize(tfm) / 2)
  2360. /* Buffers overlap, need to use memmove iso memcpy! */
  2361. memmove(&ctx->base.opad,
  2362. ctx->base.ipad.byte +
  2363. crypto_ahash_blocksize(tfm) / 2,
  2364. keylen - crypto_ahash_blocksize(tfm) / 2);
  2365. } else {
  2366. /*
  2367. * Copy the key to our ipad & opad buffers
  2368. * Note that ipad and opad each contain one half of the key,
  2369. * to match the existing HMAC driver infrastructure.
  2370. */
  2371. if (keylen <= crypto_ahash_blocksize(tfm) / 2) {
  2372. memcpy(&ctx->base.ipad, key, keylen);
  2373. } else {
  2374. memcpy(&ctx->base.ipad, key,
  2375. crypto_ahash_blocksize(tfm) / 2);
  2376. memcpy(&ctx->base.opad,
  2377. key + crypto_ahash_blocksize(tfm) / 2,
  2378. keylen - crypto_ahash_blocksize(tfm) / 2);
  2379. }
  2380. }
  2381. /* Pad key with zeroes */
  2382. if (keylen <= crypto_ahash_blocksize(tfm) / 2) {
  2383. memset(ctx->base.ipad.byte + keylen, 0,
  2384. crypto_ahash_blocksize(tfm) / 2 - keylen);
  2385. memset(&ctx->base.opad, 0, crypto_ahash_blocksize(tfm) / 2);
  2386. } else {
  2387. memset(ctx->base.opad.byte + keylen -
  2388. crypto_ahash_blocksize(tfm) / 2, 0,
  2389. crypto_ahash_blocksize(tfm) - keylen);
  2390. }
  2391. /* If doing fallback, still need to set the new key! */
  2392. ctx->fb_do_setkey = true;
  2393. return ret;
  2394. }
  2395. static int safexcel_hmac_sha3_224_init(struct ahash_request *areq)
  2396. {
  2397. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2398. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2399. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2400. memset(req, 0, sizeof(*req));
  2401. /* Copy (half of) the key */
  2402. memcpy(req->state, &ctx->base.ipad, SHA3_224_BLOCK_SIZE / 2);
  2403. /* Start of HMAC should have len == processed == blocksize */
  2404. req->len = SHA3_224_BLOCK_SIZE;
  2405. req->processed = SHA3_224_BLOCK_SIZE;
  2406. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224;
  2407. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  2408. req->state_sz = SHA3_224_BLOCK_SIZE / 2;
  2409. req->digest_sz = SHA3_224_DIGEST_SIZE;
  2410. req->block_sz = SHA3_224_BLOCK_SIZE;
  2411. req->hmac = true;
  2412. ctx->do_fallback = false;
  2413. ctx->fb_init_done = false;
  2414. return 0;
  2415. }
  2416. static int safexcel_hmac_sha3_224_digest(struct ahash_request *req)
  2417. {
  2418. if (req->nbytes)
  2419. return safexcel_hmac_sha3_224_init(req) ?:
  2420. safexcel_ahash_finup(req);
  2421. /* HW cannot do zero length HMAC, use fallback instead */
  2422. return safexcel_sha3_digest_fallback(req);
  2423. }
  2424. static int safexcel_hmac_sha3_224_cra_init(struct crypto_tfm *tfm)
  2425. {
  2426. return safexcel_hmac_sha3_cra_init(tfm, "sha3-224");
  2427. }
  2428. struct safexcel_alg_template safexcel_alg_hmac_sha3_224 = {
  2429. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2430. .algo_mask = SAFEXCEL_ALG_SHA3,
  2431. .alg.ahash = {
  2432. .init = safexcel_hmac_sha3_224_init,
  2433. .update = safexcel_sha3_update,
  2434. .final = safexcel_sha3_final,
  2435. .finup = safexcel_sha3_finup,
  2436. .digest = safexcel_hmac_sha3_224_digest,
  2437. .setkey = safexcel_hmac_sha3_setkey,
  2438. .export = safexcel_sha3_export,
  2439. .import = safexcel_sha3_import,
  2440. .halg = {
  2441. .digestsize = SHA3_224_DIGEST_SIZE,
  2442. .statesize = sizeof(struct safexcel_ahash_export_state),
  2443. .base = {
  2444. .cra_name = "hmac(sha3-224)",
  2445. .cra_driver_name = "safexcel-hmac-sha3-224",
  2446. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2447. .cra_flags = CRYPTO_ALG_ASYNC |
  2448. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2449. CRYPTO_ALG_NEED_FALLBACK,
  2450. .cra_blocksize = SHA3_224_BLOCK_SIZE,
  2451. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2452. .cra_init = safexcel_hmac_sha3_224_cra_init,
  2453. .cra_exit = safexcel_hmac_sha3_cra_exit,
  2454. .cra_module = THIS_MODULE,
  2455. },
  2456. },
  2457. },
  2458. };
  2459. static int safexcel_hmac_sha3_256_init(struct ahash_request *areq)
  2460. {
  2461. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2462. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2463. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2464. memset(req, 0, sizeof(*req));
  2465. /* Copy (half of) the key */
  2466. memcpy(req->state, &ctx->base.ipad, SHA3_256_BLOCK_SIZE / 2);
  2467. /* Start of HMAC should have len == processed == blocksize */
  2468. req->len = SHA3_256_BLOCK_SIZE;
  2469. req->processed = SHA3_256_BLOCK_SIZE;
  2470. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256;
  2471. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  2472. req->state_sz = SHA3_256_BLOCK_SIZE / 2;
  2473. req->digest_sz = SHA3_256_DIGEST_SIZE;
  2474. req->block_sz = SHA3_256_BLOCK_SIZE;
  2475. req->hmac = true;
  2476. ctx->do_fallback = false;
  2477. ctx->fb_init_done = false;
  2478. return 0;
  2479. }
  2480. static int safexcel_hmac_sha3_256_digest(struct ahash_request *req)
  2481. {
  2482. if (req->nbytes)
  2483. return safexcel_hmac_sha3_256_init(req) ?:
  2484. safexcel_ahash_finup(req);
  2485. /* HW cannot do zero length HMAC, use fallback instead */
  2486. return safexcel_sha3_digest_fallback(req);
  2487. }
  2488. static int safexcel_hmac_sha3_256_cra_init(struct crypto_tfm *tfm)
  2489. {
  2490. return safexcel_hmac_sha3_cra_init(tfm, "sha3-256");
  2491. }
  2492. struct safexcel_alg_template safexcel_alg_hmac_sha3_256 = {
  2493. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2494. .algo_mask = SAFEXCEL_ALG_SHA3,
  2495. .alg.ahash = {
  2496. .init = safexcel_hmac_sha3_256_init,
  2497. .update = safexcel_sha3_update,
  2498. .final = safexcel_sha3_final,
  2499. .finup = safexcel_sha3_finup,
  2500. .digest = safexcel_hmac_sha3_256_digest,
  2501. .setkey = safexcel_hmac_sha3_setkey,
  2502. .export = safexcel_sha3_export,
  2503. .import = safexcel_sha3_import,
  2504. .halg = {
  2505. .digestsize = SHA3_256_DIGEST_SIZE,
  2506. .statesize = sizeof(struct safexcel_ahash_export_state),
  2507. .base = {
  2508. .cra_name = "hmac(sha3-256)",
  2509. .cra_driver_name = "safexcel-hmac-sha3-256",
  2510. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2511. .cra_flags = CRYPTO_ALG_ASYNC |
  2512. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2513. CRYPTO_ALG_NEED_FALLBACK,
  2514. .cra_blocksize = SHA3_256_BLOCK_SIZE,
  2515. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2516. .cra_init = safexcel_hmac_sha3_256_cra_init,
  2517. .cra_exit = safexcel_hmac_sha3_cra_exit,
  2518. .cra_module = THIS_MODULE,
  2519. },
  2520. },
  2521. },
  2522. };
  2523. static int safexcel_hmac_sha3_384_init(struct ahash_request *areq)
  2524. {
  2525. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2526. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2527. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2528. memset(req, 0, sizeof(*req));
  2529. /* Copy (half of) the key */
  2530. memcpy(req->state, &ctx->base.ipad, SHA3_384_BLOCK_SIZE / 2);
  2531. /* Start of HMAC should have len == processed == blocksize */
  2532. req->len = SHA3_384_BLOCK_SIZE;
  2533. req->processed = SHA3_384_BLOCK_SIZE;
  2534. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384;
  2535. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  2536. req->state_sz = SHA3_384_BLOCK_SIZE / 2;
  2537. req->digest_sz = SHA3_384_DIGEST_SIZE;
  2538. req->block_sz = SHA3_384_BLOCK_SIZE;
  2539. req->hmac = true;
  2540. ctx->do_fallback = false;
  2541. ctx->fb_init_done = false;
  2542. return 0;
  2543. }
  2544. static int safexcel_hmac_sha3_384_digest(struct ahash_request *req)
  2545. {
  2546. if (req->nbytes)
  2547. return safexcel_hmac_sha3_384_init(req) ?:
  2548. safexcel_ahash_finup(req);
  2549. /* HW cannot do zero length HMAC, use fallback instead */
  2550. return safexcel_sha3_digest_fallback(req);
  2551. }
  2552. static int safexcel_hmac_sha3_384_cra_init(struct crypto_tfm *tfm)
  2553. {
  2554. return safexcel_hmac_sha3_cra_init(tfm, "sha3-384");
  2555. }
  2556. struct safexcel_alg_template safexcel_alg_hmac_sha3_384 = {
  2557. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2558. .algo_mask = SAFEXCEL_ALG_SHA3,
  2559. .alg.ahash = {
  2560. .init = safexcel_hmac_sha3_384_init,
  2561. .update = safexcel_sha3_update,
  2562. .final = safexcel_sha3_final,
  2563. .finup = safexcel_sha3_finup,
  2564. .digest = safexcel_hmac_sha3_384_digest,
  2565. .setkey = safexcel_hmac_sha3_setkey,
  2566. .export = safexcel_sha3_export,
  2567. .import = safexcel_sha3_import,
  2568. .halg = {
  2569. .digestsize = SHA3_384_DIGEST_SIZE,
  2570. .statesize = sizeof(struct safexcel_ahash_export_state),
  2571. .base = {
  2572. .cra_name = "hmac(sha3-384)",
  2573. .cra_driver_name = "safexcel-hmac-sha3-384",
  2574. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2575. .cra_flags = CRYPTO_ALG_ASYNC |
  2576. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2577. CRYPTO_ALG_NEED_FALLBACK,
  2578. .cra_blocksize = SHA3_384_BLOCK_SIZE,
  2579. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2580. .cra_init = safexcel_hmac_sha3_384_cra_init,
  2581. .cra_exit = safexcel_hmac_sha3_cra_exit,
  2582. .cra_module = THIS_MODULE,
  2583. },
  2584. },
  2585. },
  2586. };
  2587. static int safexcel_hmac_sha3_512_init(struct ahash_request *areq)
  2588. {
  2589. struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
  2590. struct safexcel_ahash_ctx *ctx = crypto_ahash_ctx(tfm);
  2591. struct safexcel_ahash_req *req = ahash_request_ctx_dma(areq);
  2592. memset(req, 0, sizeof(*req));
  2593. /* Copy (half of) the key */
  2594. memcpy(req->state, &ctx->base.ipad, SHA3_512_BLOCK_SIZE / 2);
  2595. /* Start of HMAC should have len == processed == blocksize */
  2596. req->len = SHA3_512_BLOCK_SIZE;
  2597. req->processed = SHA3_512_BLOCK_SIZE;
  2598. ctx->alg = CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512;
  2599. req->digest = CONTEXT_CONTROL_DIGEST_HMAC;
  2600. req->state_sz = SHA3_512_BLOCK_SIZE / 2;
  2601. req->digest_sz = SHA3_512_DIGEST_SIZE;
  2602. req->block_sz = SHA3_512_BLOCK_SIZE;
  2603. req->hmac = true;
  2604. ctx->do_fallback = false;
  2605. ctx->fb_init_done = false;
  2606. return 0;
  2607. }
  2608. static int safexcel_hmac_sha3_512_digest(struct ahash_request *req)
  2609. {
  2610. if (req->nbytes)
  2611. return safexcel_hmac_sha3_512_init(req) ?:
  2612. safexcel_ahash_finup(req);
  2613. /* HW cannot do zero length HMAC, use fallback instead */
  2614. return safexcel_sha3_digest_fallback(req);
  2615. }
  2616. static int safexcel_hmac_sha3_512_cra_init(struct crypto_tfm *tfm)
  2617. {
  2618. return safexcel_hmac_sha3_cra_init(tfm, "sha3-512");
  2619. }
  2620. struct safexcel_alg_template safexcel_alg_hmac_sha3_512 = {
  2621. .type = SAFEXCEL_ALG_TYPE_AHASH,
  2622. .algo_mask = SAFEXCEL_ALG_SHA3,
  2623. .alg.ahash = {
  2624. .init = safexcel_hmac_sha3_512_init,
  2625. .update = safexcel_sha3_update,
  2626. .final = safexcel_sha3_final,
  2627. .finup = safexcel_sha3_finup,
  2628. .digest = safexcel_hmac_sha3_512_digest,
  2629. .setkey = safexcel_hmac_sha3_setkey,
  2630. .export = safexcel_sha3_export,
  2631. .import = safexcel_sha3_import,
  2632. .halg = {
  2633. .digestsize = SHA3_512_DIGEST_SIZE,
  2634. .statesize = sizeof(struct safexcel_ahash_export_state),
  2635. .base = {
  2636. .cra_name = "hmac(sha3-512)",
  2637. .cra_driver_name = "safexcel-hmac-sha3-512",
  2638. .cra_priority = SAFEXCEL_CRA_PRIORITY,
  2639. .cra_flags = CRYPTO_ALG_ASYNC |
  2640. CRYPTO_ALG_KERN_DRIVER_ONLY |
  2641. CRYPTO_ALG_NEED_FALLBACK,
  2642. .cra_blocksize = SHA3_512_BLOCK_SIZE,
  2643. .cra_ctxsize = sizeof(struct safexcel_ahash_ctx),
  2644. .cra_init = safexcel_hmac_sha3_512_cra_init,
  2645. .cra_exit = safexcel_hmac_sha3_cra_exit,
  2646. .cra_module = THIS_MODULE,
  2647. },
  2648. },
  2649. },
  2650. };