qcom-rng.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2017-18 Linaro Limited
  3. //
  4. // Based on msm-rng.c and downstream driver
  5. #include <crypto/internal/rng.h>
  6. #include <linux/acpi.h>
  7. #include <linux/clk.h>
  8. #include <linux/crypto.h>
  9. #include <linux/hw_random.h>
  10. #include <linux/io.h>
  11. #include <linux/iopoll.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. /* Device specific register offsets */
  17. #define PRNG_DATA_OUT 0x0000
  18. #define PRNG_STATUS 0x0004
  19. #define PRNG_LFSR_CFG 0x0100
  20. #define PRNG_CONFIG 0x0104
  21. /* Device specific register masks and config values */
  22. #define PRNG_LFSR_CFG_MASK 0x0000ffff
  23. #define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
  24. #define PRNG_CONFIG_HW_ENABLE BIT(1)
  25. #define PRNG_STATUS_DATA_AVAIL BIT(0)
  26. #define WORD_SZ 4
  27. #define QCOM_TRNG_QUALITY 1024
  28. struct qcom_rng {
  29. struct mutex lock;
  30. void __iomem *base;
  31. struct clk *clk;
  32. struct hwrng hwrng;
  33. struct qcom_rng_match_data *match_data;
  34. };
  35. struct qcom_rng_ctx {
  36. struct qcom_rng *rng;
  37. };
  38. struct qcom_rng_match_data {
  39. bool skip_init;
  40. bool hwrng_support;
  41. };
  42. static struct qcom_rng *qcom_rng_dev;
  43. static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
  44. {
  45. unsigned int currsize = 0;
  46. u32 val;
  47. int ret;
  48. /* read random data from hardware */
  49. do {
  50. ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
  51. val & PRNG_STATUS_DATA_AVAIL,
  52. 200, 10000);
  53. if (ret)
  54. return ret;
  55. val = readl_relaxed(rng->base + PRNG_DATA_OUT);
  56. if (!val)
  57. return -EINVAL;
  58. if ((max - currsize) >= WORD_SZ) {
  59. memcpy(data, &val, WORD_SZ);
  60. data += WORD_SZ;
  61. currsize += WORD_SZ;
  62. } else {
  63. /* copy only remaining bytes */
  64. memcpy(data, &val, max - currsize);
  65. currsize = max;
  66. }
  67. } while (currsize < max);
  68. return currsize;
  69. }
  70. static int qcom_rng_generate(struct crypto_rng *tfm,
  71. const u8 *src, unsigned int slen,
  72. u8 *dstn, unsigned int dlen)
  73. {
  74. struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
  75. struct qcom_rng *rng = ctx->rng;
  76. int ret;
  77. ret = clk_prepare_enable(rng->clk);
  78. if (ret)
  79. return ret;
  80. mutex_lock(&rng->lock);
  81. ret = qcom_rng_read(rng, dstn, dlen);
  82. mutex_unlock(&rng->lock);
  83. clk_disable_unprepare(rng->clk);
  84. if (ret >= 0)
  85. ret = 0;
  86. return ret;
  87. }
  88. static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
  89. unsigned int slen)
  90. {
  91. return 0;
  92. }
  93. static int qcom_hwrng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
  94. {
  95. struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);
  96. return qcom_rng_read(qrng, data, max);
  97. }
  98. static int qcom_rng_enable(struct qcom_rng *rng)
  99. {
  100. u32 val;
  101. int ret;
  102. ret = clk_prepare_enable(rng->clk);
  103. if (ret)
  104. return ret;
  105. /* Enable PRNG only if it is not already enabled */
  106. val = readl_relaxed(rng->base + PRNG_CONFIG);
  107. if (val & PRNG_CONFIG_HW_ENABLE)
  108. goto already_enabled;
  109. val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
  110. val &= ~PRNG_LFSR_CFG_MASK;
  111. val |= PRNG_LFSR_CFG_CLOCKS;
  112. writel(val, rng->base + PRNG_LFSR_CFG);
  113. val = readl_relaxed(rng->base + PRNG_CONFIG);
  114. val |= PRNG_CONFIG_HW_ENABLE;
  115. writel(val, rng->base + PRNG_CONFIG);
  116. already_enabled:
  117. clk_disable_unprepare(rng->clk);
  118. return 0;
  119. }
  120. static int qcom_rng_init(struct crypto_tfm *tfm)
  121. {
  122. struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
  123. ctx->rng = qcom_rng_dev;
  124. if (!ctx->rng->match_data->skip_init)
  125. return qcom_rng_enable(ctx->rng);
  126. return 0;
  127. }
  128. static struct rng_alg qcom_rng_alg = {
  129. .generate = qcom_rng_generate,
  130. .seed = qcom_rng_seed,
  131. .seedsize = 0,
  132. .base = {
  133. .cra_name = "stdrng",
  134. .cra_driver_name = "qcom-rng",
  135. .cra_flags = CRYPTO_ALG_TYPE_RNG,
  136. .cra_priority = 300,
  137. .cra_ctxsize = sizeof(struct qcom_rng_ctx),
  138. .cra_module = THIS_MODULE,
  139. .cra_init = qcom_rng_init,
  140. }
  141. };
  142. static int qcom_rng_probe(struct platform_device *pdev)
  143. {
  144. struct qcom_rng *rng;
  145. int ret;
  146. rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
  147. if (!rng)
  148. return -ENOMEM;
  149. platform_set_drvdata(pdev, rng);
  150. mutex_init(&rng->lock);
  151. rng->base = devm_platform_ioremap_resource(pdev, 0);
  152. if (IS_ERR(rng->base))
  153. return PTR_ERR(rng->base);
  154. rng->clk = devm_clk_get_optional(&pdev->dev, "core");
  155. if (IS_ERR(rng->clk))
  156. return PTR_ERR(rng->clk);
  157. rng->match_data = (struct qcom_rng_match_data *)device_get_match_data(&pdev->dev);
  158. qcom_rng_dev = rng;
  159. ret = crypto_register_rng(&qcom_rng_alg);
  160. if (ret) {
  161. dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
  162. qcom_rng_dev = NULL;
  163. return ret;
  164. }
  165. if (rng->match_data->hwrng_support) {
  166. rng->hwrng.name = "qcom_hwrng";
  167. rng->hwrng.read = qcom_hwrng_read;
  168. rng->hwrng.quality = QCOM_TRNG_QUALITY;
  169. ret = devm_hwrng_register(&pdev->dev, &rng->hwrng);
  170. if (ret) {
  171. dev_err(&pdev->dev, "Register hwrng failed: %d\n", ret);
  172. qcom_rng_dev = NULL;
  173. goto fail;
  174. }
  175. }
  176. return ret;
  177. fail:
  178. crypto_unregister_rng(&qcom_rng_alg);
  179. return ret;
  180. }
  181. static void qcom_rng_remove(struct platform_device *pdev)
  182. {
  183. crypto_unregister_rng(&qcom_rng_alg);
  184. qcom_rng_dev = NULL;
  185. }
  186. static struct qcom_rng_match_data qcom_prng_match_data = {
  187. .skip_init = false,
  188. .hwrng_support = false,
  189. };
  190. static struct qcom_rng_match_data qcom_prng_ee_match_data = {
  191. .skip_init = true,
  192. .hwrng_support = false,
  193. };
  194. static struct qcom_rng_match_data qcom_trng_match_data = {
  195. .skip_init = true,
  196. .hwrng_support = true,
  197. };
  198. static const struct acpi_device_id __maybe_unused qcom_rng_acpi_match[] = {
  199. { .id = "QCOM8160", .driver_data = (kernel_ulong_t)&qcom_prng_ee_match_data },
  200. {}
  201. };
  202. MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
  203. static const struct of_device_id __maybe_unused qcom_rng_of_match[] = {
  204. { .compatible = "qcom,prng", .data = &qcom_prng_match_data },
  205. { .compatible = "qcom,prng-ee", .data = &qcom_prng_ee_match_data },
  206. { .compatible = "qcom,trng", .data = &qcom_trng_match_data },
  207. {}
  208. };
  209. MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
  210. static struct platform_driver qcom_rng_driver = {
  211. .probe = qcom_rng_probe,
  212. .remove_new = qcom_rng_remove,
  213. .driver = {
  214. .name = KBUILD_MODNAME,
  215. .of_match_table = of_match_ptr(qcom_rng_of_match),
  216. .acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
  217. }
  218. };
  219. module_platform_driver(qcom_rng_driver);
  220. MODULE_ALIAS("platform:" KBUILD_MODNAME);
  221. MODULE_DESCRIPTION("Qualcomm random number generator driver");
  222. MODULE_LICENSE("GPL v2");