ghes_edac.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * GHES/EDAC Linux driver
  4. *
  5. * Copyright (c) 2013 by Mauro Carvalho Chehab
  6. *
  7. * Red Hat Inc. https://www.redhat.com
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <acpi/ghes.h>
  11. #include <linux/edac.h>
  12. #include <linux/dmi.h>
  13. #include "edac_module.h"
  14. #include <ras/ras_event.h>
  15. #include <linux/notifier.h>
  16. #define OTHER_DETAIL_LEN 400
  17. struct ghes_pvt {
  18. struct mem_ctl_info *mci;
  19. /* Buffers for the error handling routine */
  20. char other_detail[OTHER_DETAIL_LEN];
  21. char msg[80];
  22. };
  23. static refcount_t ghes_refcount = REFCOUNT_INIT(0);
  24. /*
  25. * Access to ghes_pvt must be protected by ghes_lock. The spinlock
  26. * also provides the necessary (implicit) memory barrier for the SMP
  27. * case to make the pointer visible on another CPU.
  28. */
  29. static struct ghes_pvt *ghes_pvt;
  30. /*
  31. * This driver's representation of the system hardware, as collected
  32. * from DMI.
  33. */
  34. static struct ghes_hw_desc {
  35. int num_dimms;
  36. struct dimm_info *dimms;
  37. } ghes_hw;
  38. /* GHES registration mutex */
  39. static DEFINE_MUTEX(ghes_reg_mutex);
  40. /*
  41. * Sync with other, potentially concurrent callers of
  42. * ghes_edac_report_mem_error(). We don't know what the
  43. * "inventive" firmware would do.
  44. */
  45. static DEFINE_SPINLOCK(ghes_lock);
  46. static bool system_scanned;
  47. static struct list_head *ghes_devs;
  48. /* Memory Device - Type 17 of SMBIOS spec */
  49. struct memdev_dmi_entry {
  50. u8 type;
  51. u8 length;
  52. u16 handle;
  53. u16 phys_mem_array_handle;
  54. u16 mem_err_info_handle;
  55. u16 total_width;
  56. u16 data_width;
  57. u16 size;
  58. u8 form_factor;
  59. u8 device_set;
  60. u8 device_locator;
  61. u8 bank_locator;
  62. u8 memory_type;
  63. u16 type_detail;
  64. u16 speed;
  65. u8 manufacturer;
  66. u8 serial_number;
  67. u8 asset_tag;
  68. u8 part_number;
  69. u8 attributes;
  70. u32 extended_size;
  71. u16 conf_mem_clk_speed;
  72. } __attribute__((__packed__));
  73. static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
  74. {
  75. struct dimm_info *dimm;
  76. mci_for_each_dimm(mci, dimm) {
  77. if (dimm->smbios_handle == handle)
  78. return dimm;
  79. }
  80. return NULL;
  81. }
  82. static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
  83. {
  84. const char *bank = NULL, *device = NULL;
  85. dmi_memdev_name(handle, &bank, &device);
  86. /*
  87. * Set to a NULL string when both bank and device are zero. In this case,
  88. * the label assigned by default will be preserved.
  89. */
  90. snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
  91. (bank && *bank) ? bank : "",
  92. (bank && *bank && device && *device) ? " " : "",
  93. (device && *device) ? device : "");
  94. }
  95. static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
  96. {
  97. u16 rdr_mask = BIT(7) | BIT(13);
  98. if (entry->size == 0xffff) {
  99. pr_info("Can't get DIMM%i size\n", dimm->idx);
  100. dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
  101. } else if (entry->size == 0x7fff) {
  102. dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
  103. } else {
  104. if (entry->size & BIT(15))
  105. dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
  106. else
  107. dimm->nr_pages = MiB_TO_PAGES(entry->size);
  108. }
  109. switch (entry->memory_type) {
  110. case 0x12:
  111. if (entry->type_detail & BIT(13))
  112. dimm->mtype = MEM_RDDR;
  113. else
  114. dimm->mtype = MEM_DDR;
  115. break;
  116. case 0x13:
  117. if (entry->type_detail & BIT(13))
  118. dimm->mtype = MEM_RDDR2;
  119. else
  120. dimm->mtype = MEM_DDR2;
  121. break;
  122. case 0x14:
  123. dimm->mtype = MEM_FB_DDR2;
  124. break;
  125. case 0x18:
  126. if (entry->type_detail & BIT(12))
  127. dimm->mtype = MEM_NVDIMM;
  128. else if (entry->type_detail & BIT(13))
  129. dimm->mtype = MEM_RDDR3;
  130. else
  131. dimm->mtype = MEM_DDR3;
  132. break;
  133. case 0x1a:
  134. if (entry->type_detail & BIT(12))
  135. dimm->mtype = MEM_NVDIMM;
  136. else if (entry->type_detail & BIT(13))
  137. dimm->mtype = MEM_RDDR4;
  138. else
  139. dimm->mtype = MEM_DDR4;
  140. break;
  141. default:
  142. if (entry->type_detail & BIT(6))
  143. dimm->mtype = MEM_RMBS;
  144. else if ((entry->type_detail & rdr_mask) == rdr_mask)
  145. dimm->mtype = MEM_RDR;
  146. else if (entry->type_detail & BIT(7))
  147. dimm->mtype = MEM_SDR;
  148. else if (entry->type_detail & BIT(9))
  149. dimm->mtype = MEM_EDO;
  150. else
  151. dimm->mtype = MEM_UNKNOWN;
  152. }
  153. /*
  154. * Actually, we can only detect if the memory has bits for
  155. * checksum or not
  156. */
  157. if (entry->total_width == entry->data_width)
  158. dimm->edac_mode = EDAC_NONE;
  159. else
  160. dimm->edac_mode = EDAC_SECDED;
  161. dimm->dtype = DEV_UNKNOWN;
  162. dimm->grain = 128; /* Likely, worse case */
  163. dimm_setup_label(dimm, entry->handle);
  164. if (dimm->nr_pages) {
  165. edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
  166. dimm->idx, edac_mem_types[dimm->mtype],
  167. PAGES_TO_MiB(dimm->nr_pages),
  168. (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
  169. edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
  170. entry->memory_type, entry->type_detail,
  171. entry->total_width, entry->data_width);
  172. }
  173. dimm->smbios_handle = entry->handle;
  174. }
  175. static void enumerate_dimms(const struct dmi_header *dh, void *arg)
  176. {
  177. struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
  178. struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
  179. struct dimm_info *d;
  180. if (dh->type != DMI_ENTRY_MEM_DEVICE)
  181. return;
  182. /* Enlarge the array with additional 16 */
  183. if (!hw->num_dimms || !(hw->num_dimms % 16)) {
  184. struct dimm_info *new;
  185. new = krealloc_array(hw->dimms, hw->num_dimms + 16,
  186. sizeof(struct dimm_info), GFP_KERNEL);
  187. if (!new) {
  188. WARN_ON_ONCE(1);
  189. return;
  190. }
  191. hw->dimms = new;
  192. }
  193. d = &hw->dimms[hw->num_dimms];
  194. d->idx = hw->num_dimms;
  195. assign_dmi_dimm_info(d, entry);
  196. hw->num_dimms++;
  197. }
  198. static void ghes_scan_system(void)
  199. {
  200. if (system_scanned)
  201. return;
  202. dmi_walk(enumerate_dimms, &ghes_hw);
  203. system_scanned = true;
  204. }
  205. static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
  206. const char *location, unsigned int len)
  207. {
  208. u32 n;
  209. if (!msg)
  210. return 0;
  211. n = 0;
  212. len -= 1;
  213. n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
  214. if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
  215. goto out;
  216. n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
  217. n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
  218. out:
  219. msg[n] = '\0';
  220. return n;
  221. }
  222. static int ghes_edac_report_mem_error(struct notifier_block *nb,
  223. unsigned long val, void *data)
  224. {
  225. struct cper_sec_mem_err *mem_err = (struct cper_sec_mem_err *)data;
  226. struct cper_mem_err_compact cmem;
  227. struct edac_raw_error_desc *e;
  228. struct mem_ctl_info *mci;
  229. unsigned long sev = val;
  230. struct ghes_pvt *pvt;
  231. unsigned long flags;
  232. char *p;
  233. /*
  234. * We can do the locking below because GHES defers error processing
  235. * from NMI to IRQ context. Whenever that changes, we'd at least
  236. * know.
  237. */
  238. if (WARN_ON_ONCE(in_nmi()))
  239. return NOTIFY_OK;
  240. spin_lock_irqsave(&ghes_lock, flags);
  241. pvt = ghes_pvt;
  242. if (!pvt)
  243. goto unlock;
  244. mci = pvt->mci;
  245. e = &mci->error_desc;
  246. /* Cleans the error report buffer */
  247. memset(e, 0, sizeof (*e));
  248. e->error_count = 1;
  249. e->grain = 1;
  250. e->msg = pvt->msg;
  251. e->other_detail = pvt->other_detail;
  252. e->top_layer = -1;
  253. e->mid_layer = -1;
  254. e->low_layer = -1;
  255. *pvt->other_detail = '\0';
  256. *pvt->msg = '\0';
  257. switch (sev) {
  258. case GHES_SEV_CORRECTED:
  259. e->type = HW_EVENT_ERR_CORRECTED;
  260. break;
  261. case GHES_SEV_RECOVERABLE:
  262. e->type = HW_EVENT_ERR_UNCORRECTED;
  263. break;
  264. case GHES_SEV_PANIC:
  265. e->type = HW_EVENT_ERR_FATAL;
  266. break;
  267. default:
  268. case GHES_SEV_NO:
  269. e->type = HW_EVENT_ERR_INFO;
  270. }
  271. edac_dbg(1, "error validation_bits: 0x%08llx\n",
  272. (long long)mem_err->validation_bits);
  273. /* Error type, mapped on e->msg */
  274. if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
  275. u8 etype = mem_err->error_type;
  276. p = pvt->msg;
  277. p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
  278. } else {
  279. strcpy(pvt->msg, "unknown error");
  280. }
  281. /* Error address */
  282. if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
  283. e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
  284. e->offset_in_page = offset_in_page(mem_err->physical_addr);
  285. }
  286. /* Error grain */
  287. if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
  288. e->grain = ~mem_err->physical_addr_mask + 1;
  289. /* Memory error location, mapped on e->location */
  290. p = e->location;
  291. cper_mem_err_pack(mem_err, &cmem);
  292. p += cper_mem_err_location(&cmem, p);
  293. if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
  294. struct dimm_info *dimm;
  295. p += cper_dimm_err_location(&cmem, p);
  296. dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
  297. if (dimm) {
  298. e->top_layer = dimm->idx;
  299. strcpy(e->label, dimm->label);
  300. }
  301. }
  302. if (p > e->location)
  303. *(p - 1) = '\0';
  304. if (!*e->label)
  305. strcpy(e->label, "unknown memory");
  306. /* All other fields are mapped on e->other_detail */
  307. p = pvt->other_detail;
  308. p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
  309. if (p > pvt->other_detail)
  310. *(p - 1) = '\0';
  311. edac_raw_mc_handle_error(e);
  312. unlock:
  313. spin_unlock_irqrestore(&ghes_lock, flags);
  314. return NOTIFY_OK;
  315. }
  316. static struct notifier_block ghes_edac_mem_err_nb = {
  317. .notifier_call = ghes_edac_report_mem_error,
  318. .priority = 0,
  319. };
  320. static int ghes_edac_register(struct device *dev)
  321. {
  322. bool fake = false;
  323. struct mem_ctl_info *mci;
  324. struct ghes_pvt *pvt;
  325. struct edac_mc_layer layers[1];
  326. unsigned long flags;
  327. int rc = 0;
  328. /* finish another registration/unregistration instance first */
  329. mutex_lock(&ghes_reg_mutex);
  330. /*
  331. * We have only one logical memory controller to which all DIMMs belong.
  332. */
  333. if (refcount_inc_not_zero(&ghes_refcount))
  334. goto unlock;
  335. ghes_scan_system();
  336. /* Check if we've got a bogus BIOS */
  337. if (!ghes_hw.num_dimms) {
  338. fake = true;
  339. ghes_hw.num_dimms = 1;
  340. }
  341. layers[0].type = EDAC_MC_LAYER_ALL_MEM;
  342. layers[0].size = ghes_hw.num_dimms;
  343. layers[0].is_virt_csrow = true;
  344. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
  345. if (!mci) {
  346. pr_info("Can't allocate memory for EDAC data\n");
  347. rc = -ENOMEM;
  348. goto unlock;
  349. }
  350. pvt = mci->pvt_info;
  351. pvt->mci = mci;
  352. mci->pdev = dev;
  353. mci->mtype_cap = MEM_FLAG_EMPTY;
  354. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  355. mci->edac_cap = EDAC_FLAG_NONE;
  356. mci->mod_name = "ghes_edac.c";
  357. mci->ctl_name = "ghes_edac";
  358. mci->dev_name = "ghes";
  359. if (fake) {
  360. pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
  361. pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
  362. pr_info("work on such system. Use this driver with caution\n");
  363. }
  364. pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
  365. if (!fake) {
  366. struct dimm_info *src, *dst;
  367. int i = 0;
  368. mci_for_each_dimm(mci, dst) {
  369. src = &ghes_hw.dimms[i];
  370. dst->idx = src->idx;
  371. dst->smbios_handle = src->smbios_handle;
  372. dst->nr_pages = src->nr_pages;
  373. dst->mtype = src->mtype;
  374. dst->edac_mode = src->edac_mode;
  375. dst->dtype = src->dtype;
  376. dst->grain = src->grain;
  377. /*
  378. * If no src->label, preserve default label assigned
  379. * from EDAC core.
  380. */
  381. if (strlen(src->label))
  382. memcpy(dst->label, src->label, sizeof(src->label));
  383. i++;
  384. }
  385. } else {
  386. struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
  387. dimm->nr_pages = 1;
  388. dimm->grain = 128;
  389. dimm->mtype = MEM_UNKNOWN;
  390. dimm->dtype = DEV_UNKNOWN;
  391. dimm->edac_mode = EDAC_SECDED;
  392. }
  393. rc = edac_mc_add_mc(mci);
  394. if (rc < 0) {
  395. pr_info("Can't register with the EDAC core\n");
  396. edac_mc_free(mci);
  397. rc = -ENODEV;
  398. goto unlock;
  399. }
  400. spin_lock_irqsave(&ghes_lock, flags);
  401. ghes_pvt = pvt;
  402. spin_unlock_irqrestore(&ghes_lock, flags);
  403. ghes_register_report_chain(&ghes_edac_mem_err_nb);
  404. /* only set on success */
  405. refcount_set(&ghes_refcount, 1);
  406. unlock:
  407. /* Not needed anymore */
  408. kfree(ghes_hw.dimms);
  409. ghes_hw.dimms = NULL;
  410. mutex_unlock(&ghes_reg_mutex);
  411. return rc;
  412. }
  413. static void ghes_edac_unregister(struct ghes *ghes)
  414. {
  415. struct mem_ctl_info *mci;
  416. unsigned long flags;
  417. mutex_lock(&ghes_reg_mutex);
  418. system_scanned = false;
  419. memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
  420. if (!refcount_dec_and_test(&ghes_refcount))
  421. goto unlock;
  422. /*
  423. * Wait for the irq handler being finished.
  424. */
  425. spin_lock_irqsave(&ghes_lock, flags);
  426. mci = ghes_pvt ? ghes_pvt->mci : NULL;
  427. ghes_pvt = NULL;
  428. spin_unlock_irqrestore(&ghes_lock, flags);
  429. if (!mci)
  430. goto unlock;
  431. mci = edac_mc_del_mc(mci->pdev);
  432. if (mci)
  433. edac_mc_free(mci);
  434. ghes_unregister_report_chain(&ghes_edac_mem_err_nb);
  435. unlock:
  436. mutex_unlock(&ghes_reg_mutex);
  437. }
  438. static int __init ghes_edac_init(void)
  439. {
  440. struct ghes *g, *g_tmp;
  441. ghes_devs = ghes_get_devices();
  442. if (!ghes_devs)
  443. return -ENODEV;
  444. if (list_empty(ghes_devs)) {
  445. pr_info("GHES probing device list is empty\n");
  446. return -ENODEV;
  447. }
  448. list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
  449. ghes_edac_register(g->dev);
  450. }
  451. return 0;
  452. }
  453. module_init(ghes_edac_init);
  454. static void __exit ghes_edac_exit(void)
  455. {
  456. struct ghes *g, *g_tmp;
  457. list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
  458. ghes_edac_unregister(g);
  459. }
  460. }
  461. module_exit(ghes_edac_exit);
  462. MODULE_LICENSE("GPL");
  463. MODULE_DESCRIPTION("Output ACPI APEI/GHES BIOS detected errors via EDAC");