kxcjk-1013.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * KXCJK-1013 3-axis accelerometer driver
  4. * Copyright (c) 2014, Intel Corporation.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/i2c.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/delay.h>
  10. #include <linux/bitops.h>
  11. #include <linux/slab.h>
  12. #include <linux/string.h>
  13. #include <linux/acpi.h>
  14. #include <linux/pm.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #include <linux/iio/buffer.h>
  20. #include <linux/iio/trigger.h>
  21. #include <linux/iio/events.h>
  22. #include <linux/iio/trigger_consumer.h>
  23. #include <linux/iio/triggered_buffer.h>
  24. #include <linux/iio/accel/kxcjk_1013.h>
  25. #define KXCJK1013_DRV_NAME "kxcjk1013"
  26. #define KXCJK1013_IRQ_NAME "kxcjk1013_event"
  27. #define KXTF9_REG_HP_XOUT_L 0x00
  28. #define KXTF9_REG_HP_XOUT_H 0x01
  29. #define KXTF9_REG_HP_YOUT_L 0x02
  30. #define KXTF9_REG_HP_YOUT_H 0x03
  31. #define KXTF9_REG_HP_ZOUT_L 0x04
  32. #define KXTF9_REG_HP_ZOUT_H 0x05
  33. #define KXCJK1013_REG_XOUT_L 0x06
  34. /*
  35. * From low byte X axis register, all the other addresses of Y and Z can be
  36. * obtained by just applying axis offset. The following axis defines are just
  37. * provide clarity, but not used.
  38. */
  39. #define KXCJK1013_REG_XOUT_H 0x07
  40. #define KXCJK1013_REG_YOUT_L 0x08
  41. #define KXCJK1013_REG_YOUT_H 0x09
  42. #define KXCJK1013_REG_ZOUT_L 0x0A
  43. #define KXCJK1013_REG_ZOUT_H 0x0B
  44. #define KXCJK1013_REG_DCST_RESP 0x0C
  45. #define KXCJK1013_REG_WHO_AM_I 0x0F
  46. #define KXTF9_REG_TILT_POS_CUR 0x10
  47. #define KXTF9_REG_TILT_POS_PREV 0x11
  48. #define KXTF9_REG_INT_SRC1 0x15
  49. #define KXTF9_REG_INT_SRC2 0x16
  50. #define KXCJK1013_REG_INT_SRC1 0x16
  51. #define KXCJK1013_REG_INT_SRC2 0x17
  52. #define KXCJK1013_REG_STATUS_REG 0x18
  53. #define KXCJK1013_REG_INT_REL 0x1A
  54. #define KXCJK1013_REG_CTRL1 0x1B
  55. #define KXTF9_REG_CTRL2 0x1C
  56. #define KXTF9_REG_CTRL3 0x1D
  57. #define KXCJK1013_REG_CTRL2 0x1D
  58. #define KXCJK1013_REG_INT_CTRL1 0x1E
  59. #define KXCJK1013_REG_INT_CTRL2 0x1F
  60. #define KXTF9_REG_INT_CTRL3 0x20
  61. #define KXCJK1013_REG_DATA_CTRL 0x21
  62. #define KXTF9_REG_TILT_TIMER 0x28
  63. #define KXCJK1013_REG_WAKE_TIMER 0x29
  64. #define KXTF9_REG_TDT_TIMER 0x2B
  65. #define KXTF9_REG_TDT_THRESH_H 0x2C
  66. #define KXTF9_REG_TDT_THRESH_L 0x2D
  67. #define KXTF9_REG_TDT_TAP_TIMER 0x2E
  68. #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
  69. #define KXTF9_REG_TDT_LATENCY_TIMER 0x30
  70. #define KXTF9_REG_TDT_WINDOW_TIMER 0x31
  71. #define KXCJK1013_REG_SELF_TEST 0x3A
  72. #define KXTF9_REG_WAKE_THRESH 0x5A
  73. #define KXTF9_REG_TILT_ANGLE 0x5C
  74. #define KXTF9_REG_HYST_SET 0x5F
  75. #define KXCJK1013_REG_WAKE_THRES 0x6A
  76. /* Everything up to 0x11 is equal to KXCJK1013/KXTF9 above */
  77. #define KX023_REG_INS1 0x12
  78. #define KX023_REG_INS2 0x13
  79. #define KX023_REG_INS3 0x14
  80. #define KX023_REG_STAT 0x15
  81. #define KX023_REG_INT_REL 0x17
  82. #define KX023_REG_CNTL1 0x18
  83. #define KX023_REG_CNTL2 0x19
  84. #define KX023_REG_CNTL3 0x1A
  85. #define KX023_REG_ODCNTL 0x1B
  86. #define KX023_REG_INC1 0x1C
  87. #define KX023_REG_INC2 0x1D
  88. #define KX023_REG_INC3 0x1E
  89. #define KX023_REG_INC4 0x1F
  90. #define KX023_REG_INC5 0x20
  91. #define KX023_REG_INC6 0x21
  92. #define KX023_REG_TILT_TIMER 0x22
  93. #define KX023_REG_WUFC 0x23
  94. #define KX023_REG_TDTRC 0x24
  95. #define KX023_REG_TDTC 0x25
  96. #define KX023_REG_TTH 0x26
  97. #define KX023_REG_TTL 0x27
  98. #define KX023_REG_FTD 0x28
  99. #define KX023_REG_STD 0x29
  100. #define KX023_REG_TLT 0x2A
  101. #define KX023_REG_TWS 0x2B
  102. #define KX023_REG_ATH 0x30
  103. #define KX023_REG_TILT_ANGLE_LL 0x32
  104. #define KX023_REG_TILT_ANGLE_HL 0x33
  105. #define KX023_REG_HYST_SET 0x34
  106. #define KX023_REG_LP_CNTL 0x35
  107. #define KX023_REG_BUF_CNTL1 0x3A
  108. #define KX023_REG_BUF_CNTL2 0x3B
  109. #define KX023_REG_BUF_STATUS_1 0x3C
  110. #define KX023_REG_BUF_STATUS_2 0x3D
  111. #define KX023_REG_BUF_CLEAR 0x3E
  112. #define KX023_REG_BUF_READ 0x3F
  113. #define KX023_REG_SELF_TEST 0x60
  114. #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
  115. #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
  116. #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
  117. #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
  118. #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
  119. #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
  120. #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
  121. #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
  122. #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
  123. #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
  124. #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
  125. #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
  126. #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
  127. #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
  128. #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
  129. #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
  130. #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
  131. #define KXCJK1013_MAX_STARTUP_TIME_US 100000
  132. #define KXCJK1013_SLEEP_DELAY_MS 2000
  133. #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
  134. #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
  135. #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
  136. #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
  137. #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
  138. #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
  139. #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
  140. /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
  141. #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
  142. #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
  143. #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
  144. #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
  145. #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
  146. #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
  147. /* KX023 interrupt routing to INT1. INT2 can be configured with INC6 */
  148. #define KX023_REG_INC4_BFI1 BIT(6)
  149. #define KX023_REG_INC4_WMI1 BIT(5)
  150. #define KX023_REG_INC4_DRDY1 BIT(4)
  151. #define KX023_REG_INC4_TDTI1 BIT(2)
  152. #define KX023_REG_INC4_WUFI1 BIT(1)
  153. #define KX023_REG_INC4_TPI1 BIT(0)
  154. #define KXCJK1013_DEFAULT_WAKE_THRES 1
  155. enum kx_chipset {
  156. KXCJK1013,
  157. KXCJ91008,
  158. KXTJ21009,
  159. KXTF9,
  160. KX0221020,
  161. KX0231025,
  162. KX_MAX_CHIPS /* this must be last */
  163. };
  164. enum kx_acpi_type {
  165. ACPI_GENERIC,
  166. ACPI_SMO8500,
  167. ACPI_KIOX010A,
  168. };
  169. struct kx_chipset_regs {
  170. u8 int_src1;
  171. u8 int_src2;
  172. u8 int_rel;
  173. u8 ctrl1;
  174. u8 wuf_ctrl;
  175. u8 int_ctrl1;
  176. u8 data_ctrl;
  177. u8 wake_timer;
  178. u8 wake_thres;
  179. };
  180. static const struct kx_chipset_regs kxcjk1013_regs = {
  181. .int_src1 = KXCJK1013_REG_INT_SRC1,
  182. .int_src2 = KXCJK1013_REG_INT_SRC2,
  183. .int_rel = KXCJK1013_REG_INT_REL,
  184. .ctrl1 = KXCJK1013_REG_CTRL1,
  185. .wuf_ctrl = KXCJK1013_REG_CTRL2,
  186. .int_ctrl1 = KXCJK1013_REG_INT_CTRL1,
  187. .data_ctrl = KXCJK1013_REG_DATA_CTRL,
  188. .wake_timer = KXCJK1013_REG_WAKE_TIMER,
  189. .wake_thres = KXCJK1013_REG_WAKE_THRES,
  190. };
  191. static const struct kx_chipset_regs kxtf9_regs = {
  192. /* .int_src1 was moved to INT_SRC2 on KXTF9 */
  193. .int_src1 = KXTF9_REG_INT_SRC2,
  194. /* .int_src2 is not available */
  195. .int_rel = KXCJK1013_REG_INT_REL,
  196. .ctrl1 = KXCJK1013_REG_CTRL1,
  197. .wuf_ctrl = KXTF9_REG_CTRL3,
  198. .int_ctrl1 = KXCJK1013_REG_INT_CTRL1,
  199. .data_ctrl = KXCJK1013_REG_DATA_CTRL,
  200. .wake_timer = KXCJK1013_REG_WAKE_TIMER,
  201. .wake_thres = KXTF9_REG_WAKE_THRESH,
  202. };
  203. /* The registers have totally different names but the bits are compatible */
  204. static const struct kx_chipset_regs kx0231025_regs = {
  205. .int_src1 = KX023_REG_INS2,
  206. .int_src2 = KX023_REG_INS3,
  207. .int_rel = KX023_REG_INT_REL,
  208. .ctrl1 = KX023_REG_CNTL1,
  209. .wuf_ctrl = KX023_REG_CNTL3,
  210. .int_ctrl1 = KX023_REG_INC1,
  211. .data_ctrl = KX023_REG_ODCNTL,
  212. .wake_timer = KX023_REG_WUFC,
  213. .wake_thres = KX023_REG_ATH,
  214. };
  215. enum kxcjk1013_axis {
  216. AXIS_X,
  217. AXIS_Y,
  218. AXIS_Z,
  219. AXIS_MAX
  220. };
  221. struct kxcjk1013_data {
  222. struct i2c_client *client;
  223. struct iio_trigger *dready_trig;
  224. struct iio_trigger *motion_trig;
  225. struct iio_mount_matrix orientation;
  226. struct mutex mutex;
  227. /* Ensure timestamp naturally aligned */
  228. struct {
  229. s16 chans[AXIS_MAX];
  230. s64 timestamp __aligned(8);
  231. } scan;
  232. u8 odr_bits;
  233. u8 range;
  234. int wake_thres;
  235. int wake_dur;
  236. bool active_high_intr;
  237. bool dready_trigger_on;
  238. int ev_enable_state;
  239. bool motion_trigger_on;
  240. int64_t timestamp;
  241. enum kx_chipset chipset;
  242. enum kx_acpi_type acpi_type;
  243. const struct kx_chipset_regs *regs;
  244. };
  245. enum kxcjk1013_mode {
  246. STANDBY,
  247. OPERATION,
  248. };
  249. enum kxcjk1013_range {
  250. KXCJK1013_RANGE_2G,
  251. KXCJK1013_RANGE_4G,
  252. KXCJK1013_RANGE_8G,
  253. };
  254. struct kx_odr_map {
  255. int val;
  256. int val2;
  257. int odr_bits;
  258. int wuf_bits;
  259. };
  260. static const struct kx_odr_map samp_freq_table[] = {
  261. { 0, 781000, 0x08, 0x00 },
  262. { 1, 563000, 0x09, 0x01 },
  263. { 3, 125000, 0x0A, 0x02 },
  264. { 6, 250000, 0x0B, 0x03 },
  265. { 12, 500000, 0x00, 0x04 },
  266. { 25, 0, 0x01, 0x05 },
  267. { 50, 0, 0x02, 0x06 },
  268. { 100, 0, 0x03, 0x06 },
  269. { 200, 0, 0x04, 0x06 },
  270. { 400, 0, 0x05, 0x06 },
  271. { 800, 0, 0x06, 0x06 },
  272. { 1600, 0, 0x07, 0x06 },
  273. };
  274. static const char *const kxcjk1013_samp_freq_avail =
  275. "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
  276. static const struct kx_odr_map kxtf9_samp_freq_table[] = {
  277. { 25, 0, 0x01, 0x00 },
  278. { 50, 0, 0x02, 0x01 },
  279. { 100, 0, 0x03, 0x01 },
  280. { 200, 0, 0x04, 0x01 },
  281. { 400, 0, 0x05, 0x01 },
  282. { 800, 0, 0x06, 0x01 },
  283. };
  284. static const char *const kxtf9_samp_freq_avail =
  285. "25 50 100 200 400 800";
  286. /* Refer to section 4 of the specification */
  287. static __maybe_unused const struct {
  288. int odr_bits;
  289. int usec;
  290. } odr_start_up_times[KX_MAX_CHIPS][12] = {
  291. /* KXCJK-1013 */
  292. {
  293. {0x08, 100000},
  294. {0x09, 100000},
  295. {0x0A, 100000},
  296. {0x0B, 100000},
  297. {0, 80000},
  298. {0x01, 41000},
  299. {0x02, 21000},
  300. {0x03, 11000},
  301. {0x04, 6400},
  302. {0x05, 3900},
  303. {0x06, 2700},
  304. {0x07, 2100},
  305. },
  306. /* KXCJ9-1008 */
  307. {
  308. {0x08, 100000},
  309. {0x09, 100000},
  310. {0x0A, 100000},
  311. {0x0B, 100000},
  312. {0, 80000},
  313. {0x01, 41000},
  314. {0x02, 21000},
  315. {0x03, 11000},
  316. {0x04, 6400},
  317. {0x05, 3900},
  318. {0x06, 2700},
  319. {0x07, 2100},
  320. },
  321. /* KXCTJ2-1009 */
  322. {
  323. {0x08, 1240000},
  324. {0x09, 621000},
  325. {0x0A, 309000},
  326. {0x0B, 151000},
  327. {0, 80000},
  328. {0x01, 41000},
  329. {0x02, 21000},
  330. {0x03, 11000},
  331. {0x04, 6000},
  332. {0x05, 4000},
  333. {0x06, 3000},
  334. {0x07, 2000},
  335. },
  336. /* KXTF9 */
  337. {
  338. {0x01, 81000},
  339. {0x02, 41000},
  340. {0x03, 21000},
  341. {0x04, 11000},
  342. {0x05, 5100},
  343. {0x06, 2700},
  344. },
  345. /* KX023-1025 */
  346. {
  347. /* First 4 are not in datasheet, taken from KXCTJ2-1009 */
  348. {0x08, 1240000},
  349. {0x09, 621000},
  350. {0x0A, 309000},
  351. {0x0B, 151000},
  352. {0, 81000},
  353. {0x01, 40000},
  354. {0x02, 22000},
  355. {0x03, 12000},
  356. {0x04, 7000},
  357. {0x05, 4400},
  358. {0x06, 3000},
  359. {0x07, 3000},
  360. },
  361. };
  362. static const struct {
  363. u16 scale;
  364. u8 gsel_0;
  365. u8 gsel_1;
  366. } KXCJK1013_scale_table[] = { {9582, 0, 0},
  367. {19163, 1, 0},
  368. {38326, 0, 1} };
  369. #ifdef CONFIG_ACPI
  370. enum kiox010a_fn_index {
  371. KIOX010A_SET_LAPTOP_MODE = 1,
  372. KIOX010A_SET_TABLET_MODE = 2,
  373. };
  374. static int kiox010a_dsm(struct device *dev, int fn_index)
  375. {
  376. acpi_handle handle = ACPI_HANDLE(dev);
  377. guid_t kiox010a_dsm_guid;
  378. union acpi_object *obj;
  379. if (!handle)
  380. return -ENODEV;
  381. guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid);
  382. obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL);
  383. if (!obj)
  384. return -EIO;
  385. ACPI_FREE(obj);
  386. return 0;
  387. }
  388. static const struct acpi_device_id kx_acpi_match[] = {
  389. {"KXCJ1013", KXCJK1013},
  390. {"KXCJ1008", KXCJ91008},
  391. {"KXCJ9000", KXCJ91008},
  392. {"KIOX0008", KXCJ91008},
  393. {"KIOX0009", KXTJ21009},
  394. {"KIOX000A", KXCJ91008},
  395. {"KIOX010A", KXCJ91008}, /* KXCJ91008 in the display of a yoga 2-in-1 */
  396. {"KIOX020A", KXCJ91008}, /* KXCJ91008 in the base of a yoga 2-in-1 */
  397. {"KXTJ1009", KXTJ21009},
  398. {"KXJ2109", KXTJ21009},
  399. {"SMO8500", KXCJ91008},
  400. { }
  401. };
  402. MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
  403. #endif
  404. static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
  405. enum kxcjk1013_mode mode)
  406. {
  407. int ret;
  408. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  409. if (ret < 0) {
  410. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  411. return ret;
  412. }
  413. if (mode == STANDBY)
  414. ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
  415. else
  416. ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
  417. ret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);
  418. if (ret < 0) {
  419. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  420. return ret;
  421. }
  422. return 0;
  423. }
  424. static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
  425. enum kxcjk1013_mode *mode)
  426. {
  427. int ret;
  428. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  429. if (ret < 0) {
  430. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  431. return ret;
  432. }
  433. if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
  434. *mode = OPERATION;
  435. else
  436. *mode = STANDBY;
  437. return 0;
  438. }
  439. static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
  440. {
  441. int ret;
  442. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  443. if (ret < 0) {
  444. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  445. return ret;
  446. }
  447. ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
  448. KXCJK1013_REG_CTRL1_BIT_GSEL1);
  449. ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
  450. ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
  451. ret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);
  452. if (ret < 0) {
  453. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  454. return ret;
  455. }
  456. data->range = range_index;
  457. return 0;
  458. }
  459. static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
  460. {
  461. int ret;
  462. #ifdef CONFIG_ACPI
  463. if (data->acpi_type == ACPI_KIOX010A) {
  464. /* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */
  465. kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);
  466. }
  467. #endif
  468. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
  469. if (ret < 0) {
  470. dev_err(&data->client->dev, "Error reading who_am_i\n");
  471. return ret;
  472. }
  473. dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
  474. ret = kxcjk1013_set_mode(data, STANDBY);
  475. if (ret < 0)
  476. return ret;
  477. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  478. if (ret < 0) {
  479. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  480. return ret;
  481. }
  482. /* Set 12 bit mode */
  483. ret |= KXCJK1013_REG_CTRL1_BIT_RES;
  484. ret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);
  485. if (ret < 0) {
  486. dev_err(&data->client->dev, "Error reading reg_ctrl\n");
  487. return ret;
  488. }
  489. /* Setting range to 4G */
  490. ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
  491. if (ret < 0)
  492. return ret;
  493. ret = i2c_smbus_read_byte_data(data->client, data->regs->data_ctrl);
  494. if (ret < 0) {
  495. dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
  496. return ret;
  497. }
  498. data->odr_bits = ret;
  499. /* Set up INT polarity */
  500. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_ctrl1);
  501. if (ret < 0) {
  502. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  503. return ret;
  504. }
  505. if (data->active_high_intr)
  506. ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;
  507. else
  508. ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;
  509. ret = i2c_smbus_write_byte_data(data->client, data->regs->int_ctrl1, ret);
  510. if (ret < 0) {
  511. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  512. return ret;
  513. }
  514. /* On KX023 and KX022, route all used interrupts to INT1 for now */
  515. if ((data->chipset == KX0231025 || data->chipset == KX0221020) && data->client->irq > 0) {
  516. ret = i2c_smbus_write_byte_data(data->client, KX023_REG_INC4,
  517. KX023_REG_INC4_DRDY1 |
  518. KX023_REG_INC4_WUFI1);
  519. if (ret < 0) {
  520. dev_err(&data->client->dev, "Error writing reg_inc4\n");
  521. return ret;
  522. }
  523. }
  524. ret = kxcjk1013_set_mode(data, OPERATION);
  525. if (ret < 0)
  526. return ret;
  527. data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
  528. return 0;
  529. }
  530. #ifdef CONFIG_PM
  531. static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
  532. {
  533. int i;
  534. int idx = data->chipset;
  535. for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
  536. if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
  537. return odr_start_up_times[idx][i].usec;
  538. }
  539. return KXCJK1013_MAX_STARTUP_TIME_US;
  540. }
  541. #endif
  542. static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
  543. {
  544. #ifdef CONFIG_PM
  545. int ret;
  546. if (on)
  547. ret = pm_runtime_resume_and_get(&data->client->dev);
  548. else {
  549. pm_runtime_mark_last_busy(&data->client->dev);
  550. ret = pm_runtime_put_autosuspend(&data->client->dev);
  551. }
  552. if (ret < 0) {
  553. dev_err(&data->client->dev,
  554. "Failed: %s for %d\n", __func__, on);
  555. return ret;
  556. }
  557. #endif
  558. return 0;
  559. }
  560. static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
  561. {
  562. int ret;
  563. ret = i2c_smbus_write_byte_data(data->client, data->regs->wake_timer,
  564. data->wake_dur);
  565. if (ret < 0) {
  566. dev_err(&data->client->dev,
  567. "Error writing reg_wake_timer\n");
  568. return ret;
  569. }
  570. ret = i2c_smbus_write_byte_data(data->client, data->regs->wake_thres,
  571. data->wake_thres);
  572. if (ret < 0) {
  573. dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
  574. return ret;
  575. }
  576. return 0;
  577. }
  578. static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
  579. bool status)
  580. {
  581. int ret;
  582. enum kxcjk1013_mode store_mode;
  583. ret = kxcjk1013_get_mode(data, &store_mode);
  584. if (ret < 0)
  585. return ret;
  586. /* This is requirement by spec to change state to STANDBY */
  587. ret = kxcjk1013_set_mode(data, STANDBY);
  588. if (ret < 0)
  589. return ret;
  590. ret = kxcjk1013_chip_update_thresholds(data);
  591. if (ret < 0)
  592. return ret;
  593. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_ctrl1);
  594. if (ret < 0) {
  595. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  596. return ret;
  597. }
  598. if (status)
  599. ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  600. else
  601. ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  602. ret = i2c_smbus_write_byte_data(data->client, data->regs->int_ctrl1, ret);
  603. if (ret < 0) {
  604. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  605. return ret;
  606. }
  607. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  608. if (ret < 0) {
  609. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  610. return ret;
  611. }
  612. if (status)
  613. ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
  614. else
  615. ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
  616. ret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);
  617. if (ret < 0) {
  618. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  619. return ret;
  620. }
  621. if (store_mode == OPERATION) {
  622. ret = kxcjk1013_set_mode(data, OPERATION);
  623. if (ret < 0)
  624. return ret;
  625. }
  626. return 0;
  627. }
  628. static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
  629. bool status)
  630. {
  631. int ret;
  632. enum kxcjk1013_mode store_mode;
  633. ret = kxcjk1013_get_mode(data, &store_mode);
  634. if (ret < 0)
  635. return ret;
  636. /* This is requirement by spec to change state to STANDBY */
  637. ret = kxcjk1013_set_mode(data, STANDBY);
  638. if (ret < 0)
  639. return ret;
  640. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_ctrl1);
  641. if (ret < 0) {
  642. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  643. return ret;
  644. }
  645. if (status)
  646. ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  647. else
  648. ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  649. ret = i2c_smbus_write_byte_data(data->client, data->regs->int_ctrl1, ret);
  650. if (ret < 0) {
  651. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  652. return ret;
  653. }
  654. ret = i2c_smbus_read_byte_data(data->client, data->regs->ctrl1);
  655. if (ret < 0) {
  656. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  657. return ret;
  658. }
  659. if (status)
  660. ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
  661. else
  662. ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
  663. ret = i2c_smbus_write_byte_data(data->client, data->regs->ctrl1, ret);
  664. if (ret < 0) {
  665. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  666. return ret;
  667. }
  668. if (store_mode == OPERATION) {
  669. ret = kxcjk1013_set_mode(data, OPERATION);
  670. if (ret < 0)
  671. return ret;
  672. }
  673. return 0;
  674. }
  675. static const struct kx_odr_map *kxcjk1013_find_odr_value(
  676. const struct kx_odr_map *map, size_t map_size, int val, int val2)
  677. {
  678. int i;
  679. for (i = 0; i < map_size; ++i) {
  680. if (map[i].val == val && map[i].val2 == val2)
  681. return &map[i];
  682. }
  683. return ERR_PTR(-EINVAL);
  684. }
  685. static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map,
  686. size_t map_size, int odr_bits,
  687. int *val, int *val2)
  688. {
  689. int i;
  690. for (i = 0; i < map_size; ++i) {
  691. if (map[i].odr_bits == odr_bits) {
  692. *val = map[i].val;
  693. *val2 = map[i].val2;
  694. return IIO_VAL_INT_PLUS_MICRO;
  695. }
  696. }
  697. return -EINVAL;
  698. }
  699. static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
  700. {
  701. int ret;
  702. enum kxcjk1013_mode store_mode;
  703. const struct kx_odr_map *odr_setting;
  704. ret = kxcjk1013_get_mode(data, &store_mode);
  705. if (ret < 0)
  706. return ret;
  707. if (data->chipset == KXTF9)
  708. odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
  709. ARRAY_SIZE(kxtf9_samp_freq_table),
  710. val, val2);
  711. else
  712. odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
  713. ARRAY_SIZE(samp_freq_table),
  714. val, val2);
  715. if (IS_ERR(odr_setting))
  716. return PTR_ERR(odr_setting);
  717. /* To change ODR, the chip must be set to STANDBY as per spec */
  718. ret = kxcjk1013_set_mode(data, STANDBY);
  719. if (ret < 0)
  720. return ret;
  721. ret = i2c_smbus_write_byte_data(data->client, data->regs->data_ctrl,
  722. odr_setting->odr_bits);
  723. if (ret < 0) {
  724. dev_err(&data->client->dev, "Error writing data_ctrl\n");
  725. return ret;
  726. }
  727. data->odr_bits = odr_setting->odr_bits;
  728. ret = i2c_smbus_write_byte_data(data->client, data->regs->wuf_ctrl,
  729. odr_setting->wuf_bits);
  730. if (ret < 0) {
  731. dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
  732. return ret;
  733. }
  734. if (store_mode == OPERATION) {
  735. ret = kxcjk1013_set_mode(data, OPERATION);
  736. if (ret < 0)
  737. return ret;
  738. }
  739. return 0;
  740. }
  741. static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
  742. {
  743. if (data->chipset == KXTF9)
  744. return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
  745. ARRAY_SIZE(kxtf9_samp_freq_table),
  746. data->odr_bits, val, val2);
  747. else
  748. return kxcjk1013_convert_odr_value(samp_freq_table,
  749. ARRAY_SIZE(samp_freq_table),
  750. data->odr_bits, val, val2);
  751. }
  752. static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
  753. {
  754. u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
  755. int ret;
  756. ret = i2c_smbus_read_word_data(data->client, reg);
  757. if (ret < 0) {
  758. dev_err(&data->client->dev,
  759. "failed to read accel_%c registers\n", 'x' + axis);
  760. return ret;
  761. }
  762. return ret;
  763. }
  764. static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
  765. {
  766. int ret, i;
  767. enum kxcjk1013_mode store_mode;
  768. for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
  769. if (KXCJK1013_scale_table[i].scale == val) {
  770. ret = kxcjk1013_get_mode(data, &store_mode);
  771. if (ret < 0)
  772. return ret;
  773. ret = kxcjk1013_set_mode(data, STANDBY);
  774. if (ret < 0)
  775. return ret;
  776. ret = kxcjk1013_set_range(data, i);
  777. if (ret < 0)
  778. return ret;
  779. if (store_mode == OPERATION) {
  780. ret = kxcjk1013_set_mode(data, OPERATION);
  781. if (ret)
  782. return ret;
  783. }
  784. return 0;
  785. }
  786. }
  787. return -EINVAL;
  788. }
  789. static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
  790. struct iio_chan_spec const *chan, int *val,
  791. int *val2, long mask)
  792. {
  793. struct kxcjk1013_data *data = iio_priv(indio_dev);
  794. int ret;
  795. switch (mask) {
  796. case IIO_CHAN_INFO_RAW:
  797. mutex_lock(&data->mutex);
  798. if (iio_buffer_enabled(indio_dev))
  799. ret = -EBUSY;
  800. else {
  801. ret = kxcjk1013_set_power_state(data, true);
  802. if (ret < 0) {
  803. mutex_unlock(&data->mutex);
  804. return ret;
  805. }
  806. ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
  807. if (ret < 0) {
  808. kxcjk1013_set_power_state(data, false);
  809. mutex_unlock(&data->mutex);
  810. return ret;
  811. }
  812. *val = sign_extend32(ret >> chan->scan_type.shift,
  813. chan->scan_type.realbits - 1);
  814. ret = kxcjk1013_set_power_state(data, false);
  815. }
  816. mutex_unlock(&data->mutex);
  817. if (ret < 0)
  818. return ret;
  819. return IIO_VAL_INT;
  820. case IIO_CHAN_INFO_SCALE:
  821. *val = 0;
  822. *val2 = KXCJK1013_scale_table[data->range].scale;
  823. return IIO_VAL_INT_PLUS_MICRO;
  824. case IIO_CHAN_INFO_SAMP_FREQ:
  825. mutex_lock(&data->mutex);
  826. ret = kxcjk1013_get_odr(data, val, val2);
  827. mutex_unlock(&data->mutex);
  828. return ret;
  829. default:
  830. return -EINVAL;
  831. }
  832. }
  833. static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
  834. struct iio_chan_spec const *chan, int val,
  835. int val2, long mask)
  836. {
  837. struct kxcjk1013_data *data = iio_priv(indio_dev);
  838. int ret;
  839. switch (mask) {
  840. case IIO_CHAN_INFO_SAMP_FREQ:
  841. mutex_lock(&data->mutex);
  842. ret = kxcjk1013_set_odr(data, val, val2);
  843. mutex_unlock(&data->mutex);
  844. break;
  845. case IIO_CHAN_INFO_SCALE:
  846. if (val)
  847. return -EINVAL;
  848. mutex_lock(&data->mutex);
  849. ret = kxcjk1013_set_scale(data, val2);
  850. mutex_unlock(&data->mutex);
  851. break;
  852. default:
  853. ret = -EINVAL;
  854. }
  855. return ret;
  856. }
  857. static int kxcjk1013_read_event(struct iio_dev *indio_dev,
  858. const struct iio_chan_spec *chan,
  859. enum iio_event_type type,
  860. enum iio_event_direction dir,
  861. enum iio_event_info info,
  862. int *val, int *val2)
  863. {
  864. struct kxcjk1013_data *data = iio_priv(indio_dev);
  865. *val2 = 0;
  866. switch (info) {
  867. case IIO_EV_INFO_VALUE:
  868. *val = data->wake_thres;
  869. break;
  870. case IIO_EV_INFO_PERIOD:
  871. *val = data->wake_dur;
  872. break;
  873. default:
  874. return -EINVAL;
  875. }
  876. return IIO_VAL_INT;
  877. }
  878. static int kxcjk1013_write_event(struct iio_dev *indio_dev,
  879. const struct iio_chan_spec *chan,
  880. enum iio_event_type type,
  881. enum iio_event_direction dir,
  882. enum iio_event_info info,
  883. int val, int val2)
  884. {
  885. struct kxcjk1013_data *data = iio_priv(indio_dev);
  886. if (data->ev_enable_state)
  887. return -EBUSY;
  888. switch (info) {
  889. case IIO_EV_INFO_VALUE:
  890. data->wake_thres = val;
  891. break;
  892. case IIO_EV_INFO_PERIOD:
  893. data->wake_dur = val;
  894. break;
  895. default:
  896. return -EINVAL;
  897. }
  898. return 0;
  899. }
  900. static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
  901. const struct iio_chan_spec *chan,
  902. enum iio_event_type type,
  903. enum iio_event_direction dir)
  904. {
  905. struct kxcjk1013_data *data = iio_priv(indio_dev);
  906. return data->ev_enable_state;
  907. }
  908. static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
  909. const struct iio_chan_spec *chan,
  910. enum iio_event_type type,
  911. enum iio_event_direction dir,
  912. int state)
  913. {
  914. struct kxcjk1013_data *data = iio_priv(indio_dev);
  915. int ret;
  916. if (state && data->ev_enable_state)
  917. return 0;
  918. mutex_lock(&data->mutex);
  919. if (!state && data->motion_trigger_on) {
  920. data->ev_enable_state = 0;
  921. mutex_unlock(&data->mutex);
  922. return 0;
  923. }
  924. /*
  925. * We will expect the enable and disable to do operation in
  926. * reverse order. This will happen here anyway as our
  927. * resume operation uses sync mode runtime pm calls, the
  928. * suspend operation will be delayed by autosuspend delay
  929. * So the disable operation will still happen in reverse of
  930. * enable operation. When runtime pm is disabled the mode
  931. * is always on so sequence doesn't matter
  932. */
  933. ret = kxcjk1013_set_power_state(data, state);
  934. if (ret < 0) {
  935. mutex_unlock(&data->mutex);
  936. return ret;
  937. }
  938. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  939. if (ret < 0) {
  940. kxcjk1013_set_power_state(data, false);
  941. data->ev_enable_state = 0;
  942. mutex_unlock(&data->mutex);
  943. return ret;
  944. }
  945. data->ev_enable_state = state;
  946. mutex_unlock(&data->mutex);
  947. return 0;
  948. }
  949. static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
  950. {
  951. struct kxcjk1013_data *data = iio_priv(indio_dev);
  952. return kxcjk1013_set_power_state(data, true);
  953. }
  954. static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
  955. {
  956. struct kxcjk1013_data *data = iio_priv(indio_dev);
  957. return kxcjk1013_set_power_state(data, false);
  958. }
  959. static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
  960. struct device_attribute *attr,
  961. char *buf)
  962. {
  963. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  964. struct kxcjk1013_data *data = iio_priv(indio_dev);
  965. const char *str;
  966. if (data->chipset == KXTF9)
  967. str = kxtf9_samp_freq_avail;
  968. else
  969. str = kxcjk1013_samp_freq_avail;
  970. return sprintf(buf, "%s\n", str);
  971. }
  972. static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
  973. kxcjk1013_get_samp_freq_avail, NULL, 0);
  974. static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
  975. static struct attribute *kxcjk1013_attributes[] = {
  976. &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr,
  977. &iio_const_attr_in_accel_scale_available.dev_attr.attr,
  978. NULL,
  979. };
  980. static const struct attribute_group kxcjk1013_attrs_group = {
  981. .attrs = kxcjk1013_attributes,
  982. };
  983. static const struct iio_event_spec kxcjk1013_event = {
  984. .type = IIO_EV_TYPE_THRESH,
  985. .dir = IIO_EV_DIR_EITHER,
  986. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  987. BIT(IIO_EV_INFO_ENABLE) |
  988. BIT(IIO_EV_INFO_PERIOD)
  989. };
  990. static const struct iio_mount_matrix *
  991. kxcjk1013_get_mount_matrix(const struct iio_dev *indio_dev,
  992. const struct iio_chan_spec *chan)
  993. {
  994. struct kxcjk1013_data *data = iio_priv(indio_dev);
  995. return &data->orientation;
  996. }
  997. static const struct iio_chan_spec_ext_info kxcjk1013_ext_info[] = {
  998. IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxcjk1013_get_mount_matrix),
  999. { }
  1000. };
  1001. #define KXCJK1013_CHANNEL(_axis) { \
  1002. .type = IIO_ACCEL, \
  1003. .modified = 1, \
  1004. .channel2 = IIO_MOD_##_axis, \
  1005. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  1006. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  1007. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  1008. .scan_index = AXIS_##_axis, \
  1009. .scan_type = { \
  1010. .sign = 's', \
  1011. .realbits = 12, \
  1012. .storagebits = 16, \
  1013. .shift = 4, \
  1014. .endianness = IIO_LE, \
  1015. }, \
  1016. .event_spec = &kxcjk1013_event, \
  1017. .ext_info = kxcjk1013_ext_info, \
  1018. .num_event_specs = 1 \
  1019. }
  1020. static const struct iio_chan_spec kxcjk1013_channels[] = {
  1021. KXCJK1013_CHANNEL(X),
  1022. KXCJK1013_CHANNEL(Y),
  1023. KXCJK1013_CHANNEL(Z),
  1024. IIO_CHAN_SOFT_TIMESTAMP(3),
  1025. };
  1026. static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
  1027. .preenable = kxcjk1013_buffer_preenable,
  1028. .postdisable = kxcjk1013_buffer_postdisable,
  1029. };
  1030. static const struct iio_info kxcjk1013_info = {
  1031. .attrs = &kxcjk1013_attrs_group,
  1032. .read_raw = kxcjk1013_read_raw,
  1033. .write_raw = kxcjk1013_write_raw,
  1034. .read_event_value = kxcjk1013_read_event,
  1035. .write_event_value = kxcjk1013_write_event,
  1036. .write_event_config = kxcjk1013_write_event_config,
  1037. .read_event_config = kxcjk1013_read_event_config,
  1038. };
  1039. static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0};
  1040. static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
  1041. {
  1042. struct iio_poll_func *pf = p;
  1043. struct iio_dev *indio_dev = pf->indio_dev;
  1044. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1045. int ret;
  1046. mutex_lock(&data->mutex);
  1047. ret = i2c_smbus_read_i2c_block_data_or_emulated(data->client,
  1048. KXCJK1013_REG_XOUT_L,
  1049. AXIS_MAX * 2,
  1050. (u8 *)data->scan.chans);
  1051. mutex_unlock(&data->mutex);
  1052. if (ret < 0)
  1053. goto err;
  1054. iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
  1055. data->timestamp);
  1056. err:
  1057. iio_trigger_notify_done(indio_dev->trig);
  1058. return IRQ_HANDLED;
  1059. }
  1060. static void kxcjk1013_trig_reen(struct iio_trigger *trig)
  1061. {
  1062. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  1063. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1064. int ret;
  1065. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_rel);
  1066. if (ret < 0)
  1067. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  1068. }
  1069. static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
  1070. bool state)
  1071. {
  1072. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  1073. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1074. int ret;
  1075. mutex_lock(&data->mutex);
  1076. if (!state && data->ev_enable_state && data->motion_trigger_on) {
  1077. data->motion_trigger_on = false;
  1078. mutex_unlock(&data->mutex);
  1079. return 0;
  1080. }
  1081. ret = kxcjk1013_set_power_state(data, state);
  1082. if (ret < 0) {
  1083. mutex_unlock(&data->mutex);
  1084. return ret;
  1085. }
  1086. if (data->motion_trig == trig)
  1087. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  1088. else
  1089. ret = kxcjk1013_setup_new_data_interrupt(data, state);
  1090. if (ret < 0) {
  1091. kxcjk1013_set_power_state(data, false);
  1092. mutex_unlock(&data->mutex);
  1093. return ret;
  1094. }
  1095. if (data->motion_trig == trig)
  1096. data->motion_trigger_on = state;
  1097. else
  1098. data->dready_trigger_on = state;
  1099. mutex_unlock(&data->mutex);
  1100. return 0;
  1101. }
  1102. static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
  1103. .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
  1104. .reenable = kxcjk1013_trig_reen,
  1105. };
  1106. static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev)
  1107. {
  1108. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1109. int ret = i2c_smbus_read_byte_data(data->client, data->regs->int_src2);
  1110. if (ret < 0) {
  1111. dev_err(&data->client->dev, "Error reading reg_int_src2\n");
  1112. return;
  1113. }
  1114. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
  1115. iio_push_event(indio_dev,
  1116. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1117. 0,
  1118. IIO_MOD_X,
  1119. IIO_EV_TYPE_THRESH,
  1120. IIO_EV_DIR_FALLING),
  1121. data->timestamp);
  1122. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
  1123. iio_push_event(indio_dev,
  1124. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1125. 0,
  1126. IIO_MOD_X,
  1127. IIO_EV_TYPE_THRESH,
  1128. IIO_EV_DIR_RISING),
  1129. data->timestamp);
  1130. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
  1131. iio_push_event(indio_dev,
  1132. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1133. 0,
  1134. IIO_MOD_Y,
  1135. IIO_EV_TYPE_THRESH,
  1136. IIO_EV_DIR_FALLING),
  1137. data->timestamp);
  1138. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
  1139. iio_push_event(indio_dev,
  1140. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1141. 0,
  1142. IIO_MOD_Y,
  1143. IIO_EV_TYPE_THRESH,
  1144. IIO_EV_DIR_RISING),
  1145. data->timestamp);
  1146. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
  1147. iio_push_event(indio_dev,
  1148. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1149. 0,
  1150. IIO_MOD_Z,
  1151. IIO_EV_TYPE_THRESH,
  1152. IIO_EV_DIR_FALLING),
  1153. data->timestamp);
  1154. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
  1155. iio_push_event(indio_dev,
  1156. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1157. 0,
  1158. IIO_MOD_Z,
  1159. IIO_EV_TYPE_THRESH,
  1160. IIO_EV_DIR_RISING),
  1161. data->timestamp);
  1162. }
  1163. static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
  1164. {
  1165. struct iio_dev *indio_dev = private;
  1166. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1167. int ret;
  1168. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_src1);
  1169. if (ret < 0) {
  1170. dev_err(&data->client->dev, "Error reading reg_int_src1\n");
  1171. goto ack_intr;
  1172. }
  1173. if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
  1174. if (data->chipset == KXTF9)
  1175. iio_push_event(indio_dev,
  1176. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1177. 0,
  1178. IIO_MOD_X_AND_Y_AND_Z,
  1179. IIO_EV_TYPE_THRESH,
  1180. IIO_EV_DIR_RISING),
  1181. data->timestamp);
  1182. else
  1183. kxcjk1013_report_motion_event(indio_dev);
  1184. }
  1185. ack_intr:
  1186. if (data->dready_trigger_on)
  1187. return IRQ_HANDLED;
  1188. ret = i2c_smbus_read_byte_data(data->client, data->regs->int_rel);
  1189. if (ret < 0)
  1190. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  1191. return IRQ_HANDLED;
  1192. }
  1193. static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
  1194. {
  1195. struct iio_dev *indio_dev = private;
  1196. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1197. data->timestamp = iio_get_time_ns(indio_dev);
  1198. if (data->dready_trigger_on)
  1199. iio_trigger_poll(data->dready_trig);
  1200. else if (data->motion_trigger_on)
  1201. iio_trigger_poll(data->motion_trig);
  1202. if (data->ev_enable_state)
  1203. return IRQ_WAKE_THREAD;
  1204. else
  1205. return IRQ_HANDLED;
  1206. }
  1207. static const char *kxcjk1013_match_acpi_device(struct device *dev,
  1208. enum kx_chipset *chipset,
  1209. enum kx_acpi_type *acpi_type,
  1210. const char **label)
  1211. {
  1212. const struct acpi_device_id *id;
  1213. id = acpi_match_device(dev->driver->acpi_match_table, dev);
  1214. if (!id)
  1215. return NULL;
  1216. if (strcmp(id->id, "SMO8500") == 0) {
  1217. *acpi_type = ACPI_SMO8500;
  1218. } else if (strcmp(id->id, "KIOX010A") == 0) {
  1219. *acpi_type = ACPI_KIOX010A;
  1220. *label = "accel-display";
  1221. } else if (strcmp(id->id, "KIOX020A") == 0) {
  1222. *label = "accel-base";
  1223. }
  1224. *chipset = (enum kx_chipset)id->driver_data;
  1225. return dev_name(dev);
  1226. }
  1227. static int kxcjk1013_probe(struct i2c_client *client)
  1228. {
  1229. const struct i2c_device_id *id = i2c_client_get_device_id(client);
  1230. static const char * const regulator_names[] = { "vdd", "vddio" };
  1231. struct kxcjk1013_data *data;
  1232. struct iio_dev *indio_dev;
  1233. struct kxcjk_1013_platform_data *pdata;
  1234. const char *name;
  1235. int ret;
  1236. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  1237. if (!indio_dev)
  1238. return -ENOMEM;
  1239. data = iio_priv(indio_dev);
  1240. i2c_set_clientdata(client, indio_dev);
  1241. data->client = client;
  1242. pdata = dev_get_platdata(&client->dev);
  1243. if (pdata) {
  1244. data->active_high_intr = pdata->active_high_intr;
  1245. data->orientation = pdata->orientation;
  1246. } else {
  1247. data->active_high_intr = true; /* default polarity */
  1248. if (!iio_read_acpi_mount_matrix(&client->dev, &data->orientation, "ROTM")) {
  1249. ret = iio_read_mount_matrix(&client->dev, &data->orientation);
  1250. if (ret)
  1251. return ret;
  1252. }
  1253. }
  1254. ret = devm_regulator_bulk_get_enable(&client->dev,
  1255. ARRAY_SIZE(regulator_names),
  1256. regulator_names);
  1257. if (ret)
  1258. return dev_err_probe(&client->dev, ret, "Failed to get regulators\n");
  1259. /*
  1260. * A typical delay of 10ms is required for powering up
  1261. * according to the data sheets of supported chips.
  1262. * Hence double that to play safe.
  1263. */
  1264. msleep(20);
  1265. if (id) {
  1266. data->chipset = (enum kx_chipset)(id->driver_data);
  1267. name = id->name;
  1268. } else if (ACPI_HANDLE(&client->dev)) {
  1269. name = kxcjk1013_match_acpi_device(&client->dev,
  1270. &data->chipset,
  1271. &data->acpi_type,
  1272. &indio_dev->label);
  1273. } else
  1274. return -ENODEV;
  1275. switch (data->chipset) {
  1276. case KXCJK1013:
  1277. case KXCJ91008:
  1278. case KXTJ21009:
  1279. data->regs = &kxcjk1013_regs;
  1280. break;
  1281. case KXTF9:
  1282. data->regs = &kxtf9_regs;
  1283. break;
  1284. case KX0221020:
  1285. case KX0231025:
  1286. data->regs = &kx0231025_regs;
  1287. break;
  1288. default:
  1289. return -EINVAL;
  1290. }
  1291. ret = kxcjk1013_chip_init(data);
  1292. if (ret < 0)
  1293. return ret;
  1294. mutex_init(&data->mutex);
  1295. indio_dev->channels = kxcjk1013_channels;
  1296. indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
  1297. indio_dev->available_scan_masks = kxcjk1013_scan_masks;
  1298. indio_dev->name = name;
  1299. indio_dev->modes = INDIO_DIRECT_MODE;
  1300. indio_dev->info = &kxcjk1013_info;
  1301. if (client->irq > 0 && data->acpi_type != ACPI_SMO8500) {
  1302. ret = devm_request_threaded_irq(&client->dev, client->irq,
  1303. kxcjk1013_data_rdy_trig_poll,
  1304. kxcjk1013_event_handler,
  1305. IRQF_TRIGGER_RISING,
  1306. KXCJK1013_IRQ_NAME,
  1307. indio_dev);
  1308. if (ret)
  1309. goto err_poweroff;
  1310. data->dready_trig = devm_iio_trigger_alloc(&client->dev,
  1311. "%s-dev%d",
  1312. indio_dev->name,
  1313. iio_device_id(indio_dev));
  1314. if (!data->dready_trig) {
  1315. ret = -ENOMEM;
  1316. goto err_poweroff;
  1317. }
  1318. data->motion_trig = devm_iio_trigger_alloc(&client->dev,
  1319. "%s-any-motion-dev%d",
  1320. indio_dev->name,
  1321. iio_device_id(indio_dev));
  1322. if (!data->motion_trig) {
  1323. ret = -ENOMEM;
  1324. goto err_poweroff;
  1325. }
  1326. data->dready_trig->ops = &kxcjk1013_trigger_ops;
  1327. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  1328. ret = iio_trigger_register(data->dready_trig);
  1329. if (ret)
  1330. goto err_poweroff;
  1331. indio_dev->trig = iio_trigger_get(data->dready_trig);
  1332. data->motion_trig->ops = &kxcjk1013_trigger_ops;
  1333. iio_trigger_set_drvdata(data->motion_trig, indio_dev);
  1334. ret = iio_trigger_register(data->motion_trig);
  1335. if (ret) {
  1336. data->motion_trig = NULL;
  1337. goto err_trigger_unregister;
  1338. }
  1339. }
  1340. ret = iio_triggered_buffer_setup(indio_dev,
  1341. &iio_pollfunc_store_time,
  1342. kxcjk1013_trigger_handler,
  1343. &kxcjk1013_buffer_setup_ops);
  1344. if (ret < 0) {
  1345. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  1346. goto err_trigger_unregister;
  1347. }
  1348. ret = pm_runtime_set_active(&client->dev);
  1349. if (ret)
  1350. goto err_buffer_cleanup;
  1351. pm_runtime_enable(&client->dev);
  1352. pm_runtime_set_autosuspend_delay(&client->dev,
  1353. KXCJK1013_SLEEP_DELAY_MS);
  1354. pm_runtime_use_autosuspend(&client->dev);
  1355. ret = iio_device_register(indio_dev);
  1356. if (ret < 0) {
  1357. dev_err(&client->dev, "unable to register iio device\n");
  1358. goto err_pm_cleanup;
  1359. }
  1360. return 0;
  1361. err_pm_cleanup:
  1362. pm_runtime_dont_use_autosuspend(&client->dev);
  1363. pm_runtime_disable(&client->dev);
  1364. err_buffer_cleanup:
  1365. iio_triggered_buffer_cleanup(indio_dev);
  1366. err_trigger_unregister:
  1367. if (data->dready_trig)
  1368. iio_trigger_unregister(data->dready_trig);
  1369. if (data->motion_trig)
  1370. iio_trigger_unregister(data->motion_trig);
  1371. err_poweroff:
  1372. kxcjk1013_set_mode(data, STANDBY);
  1373. return ret;
  1374. }
  1375. static void kxcjk1013_remove(struct i2c_client *client)
  1376. {
  1377. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  1378. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1379. iio_device_unregister(indio_dev);
  1380. pm_runtime_disable(&client->dev);
  1381. pm_runtime_set_suspended(&client->dev);
  1382. iio_triggered_buffer_cleanup(indio_dev);
  1383. if (data->dready_trig) {
  1384. iio_trigger_unregister(data->dready_trig);
  1385. iio_trigger_unregister(data->motion_trig);
  1386. }
  1387. mutex_lock(&data->mutex);
  1388. kxcjk1013_set_mode(data, STANDBY);
  1389. mutex_unlock(&data->mutex);
  1390. }
  1391. #ifdef CONFIG_PM_SLEEP
  1392. static int kxcjk1013_suspend(struct device *dev)
  1393. {
  1394. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1395. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1396. int ret;
  1397. mutex_lock(&data->mutex);
  1398. ret = kxcjk1013_set_mode(data, STANDBY);
  1399. mutex_unlock(&data->mutex);
  1400. return ret;
  1401. }
  1402. static int kxcjk1013_resume(struct device *dev)
  1403. {
  1404. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1405. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1406. int ret = 0;
  1407. mutex_lock(&data->mutex);
  1408. ret = kxcjk1013_set_mode(data, OPERATION);
  1409. if (ret == 0)
  1410. ret = kxcjk1013_set_range(data, data->range);
  1411. mutex_unlock(&data->mutex);
  1412. return ret;
  1413. }
  1414. #endif
  1415. #ifdef CONFIG_PM
  1416. static int kxcjk1013_runtime_suspend(struct device *dev)
  1417. {
  1418. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1419. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1420. int ret;
  1421. ret = kxcjk1013_set_mode(data, STANDBY);
  1422. if (ret < 0) {
  1423. dev_err(&data->client->dev, "powering off device failed\n");
  1424. return -EAGAIN;
  1425. }
  1426. return 0;
  1427. }
  1428. static int kxcjk1013_runtime_resume(struct device *dev)
  1429. {
  1430. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1431. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1432. int ret;
  1433. int sleep_val;
  1434. ret = kxcjk1013_set_mode(data, OPERATION);
  1435. if (ret < 0)
  1436. return ret;
  1437. sleep_val = kxcjk1013_get_startup_times(data);
  1438. if (sleep_val < 20000)
  1439. usleep_range(sleep_val, 20000);
  1440. else
  1441. msleep_interruptible(sleep_val/1000);
  1442. return 0;
  1443. }
  1444. #endif
  1445. static const struct dev_pm_ops kxcjk1013_pm_ops = {
  1446. SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
  1447. SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
  1448. kxcjk1013_runtime_resume, NULL)
  1449. };
  1450. static const struct i2c_device_id kxcjk1013_id[] = {
  1451. {"kxcjk1013", KXCJK1013},
  1452. {"kxcj91008", KXCJ91008},
  1453. {"kxtj21009", KXTJ21009},
  1454. {"kxtf9", KXTF9},
  1455. {"kx022-1020", KX0221020},
  1456. {"kx023-1025", KX0231025},
  1457. {"SMO8500", KXCJ91008},
  1458. {}
  1459. };
  1460. MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
  1461. static const struct of_device_id kxcjk1013_of_match[] = {
  1462. { .compatible = "kionix,kxcjk1013", },
  1463. { .compatible = "kionix,kxcj91008", },
  1464. { .compatible = "kionix,kxtj21009", },
  1465. { .compatible = "kionix,kxtf9", },
  1466. { .compatible = "kionix,kx022-1020", },
  1467. { .compatible = "kionix,kx023-1025", },
  1468. { }
  1469. };
  1470. MODULE_DEVICE_TABLE(of, kxcjk1013_of_match);
  1471. static struct i2c_driver kxcjk1013_driver = {
  1472. .driver = {
  1473. .name = KXCJK1013_DRV_NAME,
  1474. .acpi_match_table = ACPI_PTR(kx_acpi_match),
  1475. .of_match_table = kxcjk1013_of_match,
  1476. .pm = &kxcjk1013_pm_ops,
  1477. },
  1478. .probe = kxcjk1013_probe,
  1479. .remove = kxcjk1013_remove,
  1480. .id_table = kxcjk1013_id,
  1481. };
  1482. module_i2c_driver(kxcjk1013_driver);
  1483. MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
  1484. MODULE_LICENSE("GPL v2");
  1485. MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");