Kconfig 10 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menuconfig MAILBOX
  3. bool "Mailbox Hardware Support"
  4. help
  5. Mailbox is a framework to control hardware communication between
  6. on-chip processors through queued messages and interrupt driven
  7. signals. Say Y if your platform supports hardware mailboxes.
  8. if MAILBOX
  9. config ARM_MHU
  10. tristate "ARM MHU Mailbox"
  11. depends on ARM_AMBA
  12. help
  13. Say Y here if you want to build the ARM MHU controller driver.
  14. The controller has 3 mailbox channels, the last of which can be
  15. used in Secure mode only.
  16. config ARM_MHU_V2
  17. tristate "ARM MHUv2 Mailbox"
  18. depends on ARM_AMBA
  19. help
  20. Say Y here if you want to build the ARM MHUv2 controller driver,
  21. which provides unidirectional mailboxes between processing elements.
  22. config ARM_MHU_V3
  23. tristate "ARM MHUv3 Mailbox"
  24. depends on ARM64 || COMPILE_TEST
  25. depends on HAS_IOMEM || COMPILE_TEST
  26. depends on OF
  27. help
  28. Say Y here if you want to build the ARM MHUv3 controller driver,
  29. which provides unidirectional mailboxes between processing elements.
  30. ARM MHUv3 controllers can implement a varying number of extensions
  31. that provides different means of transports: supported extensions
  32. will be discovered and possibly managed at probe-time.
  33. config IMX_MBOX
  34. tristate "i.MX Mailbox"
  35. depends on ARCH_MXC || COMPILE_TEST
  36. help
  37. Mailbox implementation for i.MX Messaging Unit (MU).
  38. config PLATFORM_MHU
  39. tristate "Platform MHU Mailbox"
  40. depends on OF
  41. depends on HAS_IOMEM
  42. help
  43. Say Y here if you want to build a platform specific variant MHU
  44. controller driver.
  45. The controller has a maximum of 3 mailbox channels, the last of
  46. which can be used in Secure mode only.
  47. config PL320_MBOX
  48. bool "ARM PL320 Mailbox"
  49. depends on ARM_AMBA
  50. help
  51. An implementation of the ARM PL320 Interprocessor Communication
  52. Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
  53. send short messages between Highbank's A9 cores and the EnergyCore
  54. Management Engine, primarily for cpufreq. Say Y here if you want
  55. to use the PL320 IPCM support.
  56. config ARMADA_37XX_RWTM_MBOX
  57. tristate "Armada 37xx rWTM BIU Mailbox"
  58. depends on ARCH_MVEBU || COMPILE_TEST
  59. depends on OF
  60. help
  61. Mailbox implementation for communication with the the firmware
  62. running on the Cortex-M3 rWTM secure processor of the Armada 37xx
  63. SOC. Say Y here if you are building for such a device (for example
  64. the Turris Mox router).
  65. config OMAP2PLUS_MBOX
  66. tristate "OMAP2+ Mailbox framework support"
  67. depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST
  68. help
  69. Mailbox implementation for OMAP family chips with hardware for
  70. interprocessor communication involving DSP, IVA1.0 and IVA2 in
  71. OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
  72. want to use OMAP2+ Mailbox framework support.
  73. config ROCKCHIP_MBOX
  74. bool "Rockchip Soc Integrated Mailbox Support"
  75. depends on ARCH_ROCKCHIP || COMPILE_TEST
  76. help
  77. This driver provides support for inter-processor communication
  78. between CPU cores and MCU processor on Some Rockchip SOCs.
  79. Please check it that the Soc you use have Mailbox hardware.
  80. Say Y here if you want to use the Rockchip Mailbox support.
  81. config PCC
  82. bool "Platform Communication Channel Driver"
  83. depends on ACPI
  84. default n
  85. help
  86. ACPI 5.0+ spec defines a generic mode of communication
  87. between the OS and a platform such as the BMC. This medium
  88. (PCC) is typically used by CPPC (ACPI CPU Performance management),
  89. RAS (ACPI reliability protocol) and MPST (ACPI Memory power
  90. states). Select this driver if your platform implements the
  91. PCC clients mentioned above.
  92. config ALTERA_MBOX
  93. tristate "Altera Mailbox"
  94. depends on HAS_IOMEM
  95. help
  96. An implementation of the Altera Mailbox soft core. It is used
  97. to send message between processors. Say Y here if you want to use the
  98. Altera mailbox support.
  99. config BCM2835_MBOX
  100. tristate "BCM2835 Mailbox"
  101. depends on ARCH_BCM2835
  102. help
  103. An implementation of the BCM2385 Mailbox. It is used to invoke
  104. the services of the Videocore. Say Y here if you want to use the
  105. BCM2835 Mailbox.
  106. config STI_MBOX
  107. tristate "STI Mailbox framework support"
  108. depends on ARCH_STI && OF
  109. help
  110. Mailbox implementation for STMicroelectonics family chips with
  111. hardware for interprocessor communication.
  112. config TI_MESSAGE_MANAGER
  113. tristate "Texas Instruments Message Manager Driver"
  114. depends on ARCH_KEYSTONE || ARCH_K3
  115. default ARCH_K3
  116. help
  117. An implementation of Message Manager slave driver for Keystone
  118. and K3 architecture SoCs from Texas Instruments. Message Manager
  119. is a communication entity found on few of Texas Instrument's keystone
  120. and K3 architecture SoCs. These may be used for communication between
  121. multiple processors within the SoC. Select this driver if your
  122. platform has support for the hardware block.
  123. config HI3660_MBOX
  124. tristate "Hi3660 Mailbox" if EXPERT
  125. depends on (ARCH_HISI || COMPILE_TEST)
  126. depends on OF
  127. default ARCH_HISI
  128. help
  129. An implementation of the hi3660 mailbox. It is used to send message
  130. between application processors and other processors/MCU/DSP. Select
  131. Y here if you want to use Hi3660 mailbox controller.
  132. config HI6220_MBOX
  133. tristate "Hi6220 Mailbox" if EXPERT
  134. depends on (ARCH_HISI || COMPILE_TEST)
  135. depends on OF
  136. default ARCH_HISI
  137. help
  138. An implementation of the hi6220 mailbox. It is used to send message
  139. between application processors and MCU. Say Y here if you want to
  140. build Hi6220 mailbox controller driver.
  141. config MAILBOX_TEST
  142. tristate "Mailbox Test Client"
  143. depends on OF
  144. depends on HAS_IOMEM
  145. help
  146. Test client to help with testing new Controller driver
  147. implementations.
  148. config POLARFIRE_SOC_MAILBOX
  149. tristate "PolarFire SoC (MPFS) Mailbox"
  150. depends on HAS_IOMEM
  151. depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
  152. help
  153. This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
  154. To compile this driver as a module, choose M here. the
  155. module will be called mailbox-mpfs.
  156. If unsure, say N.
  157. config QCOM_APCS_IPC
  158. tristate "Qualcomm APCS IPC driver"
  159. depends on ARCH_QCOM || COMPILE_TEST
  160. help
  161. Say y here to enable support for the APCS IPC mailbox driver,
  162. providing an interface for invoking the inter-process communication
  163. signals from the application processor to other masters.
  164. config TEGRA_HSP_MBOX
  165. bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
  166. depends on ARCH_TEGRA
  167. help
  168. The Tegra HSP driver is used for the interprocessor communication
  169. between different remote processors and host processors on Tegra186
  170. and later SoCs. Say Y here if you want to have this support.
  171. If unsure say N.
  172. config XGENE_SLIMPRO_MBOX
  173. tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
  174. depends on ARCH_XGENE
  175. help
  176. An implementation of the APM X-Gene Interprocessor Communication
  177. Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
  178. It is used to send short messages between ARM64-bit cores and
  179. the SLIMpro Management Engine, primarily for PM. Say Y here if you
  180. want to use the APM X-Gene SLIMpro IPCM support.
  181. config BCM_PDC_MBOX
  182. tristate "Broadcom FlexSparx DMA Mailbox"
  183. depends on ARCH_BCM_IPROC || COMPILE_TEST
  184. help
  185. Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
  186. which provides access to various offload engines on Broadcom
  187. SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
  188. config BCM_FLEXRM_MBOX
  189. tristate "Broadcom FlexRM Mailbox"
  190. depends on ARM64
  191. depends on ARCH_BCM_IPROC || COMPILE_TEST
  192. select GENERIC_MSI_IRQ
  193. default m if ARCH_BCM_IPROC
  194. help
  195. Mailbox implementation of the Broadcom FlexRM ring manager,
  196. which provides access to various offload engines on Broadcom
  197. SoCs. Say Y here if you want to use the Broadcom FlexRM.
  198. config STM32_IPCC
  199. tristate "STM32 IPCC Mailbox"
  200. depends on MACH_STM32MP157 || COMPILE_TEST
  201. help
  202. Mailbox implementation for STMicroelectonics STM32 family chips
  203. with hardware for Inter-Processor Communication Controller (IPCC)
  204. between processors. Say Y here if you want to have this support.
  205. config MTK_ADSP_MBOX
  206. tristate "MediaTek ADSP Mailbox Controller"
  207. depends on ARCH_MEDIATEK || COMPILE_TEST
  208. help
  209. Say yes here to add support for "MediaTek ADSP Mailbox Controller.
  210. This mailbox driver is used to send notification or short message
  211. between processors with ADSP. It will place the message to share
  212. buffer and will access the ipc control.
  213. config MTK_CMDQ_MBOX
  214. tristate "MediaTek CMDQ Mailbox Support"
  215. depends on ARCH_MEDIATEK || COMPILE_TEST
  216. select MTK_INFRACFG
  217. help
  218. Say yes here to add support for the MediaTek Command Queue (CMDQ)
  219. mailbox driver. The CMDQ is used to help read/write registers with
  220. critical time limitation, such as updating display configuration
  221. during the vblank.
  222. config ZYNQMP_IPI_MBOX
  223. tristate "Xilinx ZynqMP IPI Mailbox"
  224. depends on ARCH_ZYNQMP && OF
  225. help
  226. Say yes here to add support for Xilinx IPI mailbox driver.
  227. This mailbox driver is used to send notification or short message
  228. between processors with Xilinx ZynqMP IPI. It will place the
  229. message to the IPI buffer and will access the IPI control
  230. registers to kick the other processor or enquire status.
  231. config SUN6I_MSGBOX
  232. tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
  233. depends on ARCH_SUNXI || COMPILE_TEST
  234. default ARCH_SUNXI
  235. help
  236. Mailbox implementation for the hardware message box present in
  237. various Allwinner SoCs. This mailbox is used for communication
  238. between the application CPUs and the power management coprocessor.
  239. config SPRD_MBOX
  240. tristate "Spreadtrum Mailbox"
  241. depends on ARCH_SPRD || COMPILE_TEST
  242. help
  243. Mailbox driver implementation for the Spreadtrum platform. It is used
  244. to send message between application processors and MCU. Say Y here if
  245. you want to build the Spreatrum mailbox controller driver.
  246. config QCOM_CPUCP_MBOX
  247. tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
  248. depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT
  249. help
  250. Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
  251. controller driver enables communication between AP and CPUCP. Say
  252. Y here if you want to build this driver.
  253. config QCOM_IPCC
  254. tristate "Qualcomm Technologies, Inc. IPCC driver"
  255. depends on ARCH_QCOM || COMPILE_TEST
  256. help
  257. Qualcomm Technologies, Inc. Inter-Processor Communication Controller
  258. (IPCC) driver for MSM devices. The driver provides mailbox support for
  259. sending interrupts to the clients. On the other hand, the driver also
  260. acts as an interrupt controller for receiving interrupts from clients.
  261. Say Y here if you want to build this driver.
  262. endif