platform_mhu.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2016 BayLibre SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. * Synchronised with arm_mhu.c from :
  6. * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
  7. * Copyright (C) 2015 Linaro Ltd.
  8. * Author: Jassi Brar <jaswinder.singh@linaro.org>
  9. */
  10. #include <linux/interrupt.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/mutex.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/err.h>
  16. #include <linux/io.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/mailbox_controller.h>
  21. #define INTR_SET_OFS 0x0
  22. #define INTR_STAT_OFS 0x4
  23. #define INTR_CLR_OFS 0x8
  24. #define MHU_SEC_OFFSET 0x0
  25. #define MHU_LP_OFFSET 0xc
  26. #define MHU_HP_OFFSET 0x18
  27. #define TX_REG_OFFSET 0x24
  28. #define MHU_CHANS 3
  29. struct platform_mhu_link {
  30. int irq;
  31. void __iomem *tx_reg;
  32. void __iomem *rx_reg;
  33. };
  34. struct platform_mhu {
  35. void __iomem *base;
  36. struct platform_mhu_link mlink[MHU_CHANS];
  37. struct mbox_chan chan[MHU_CHANS];
  38. struct mbox_controller mbox;
  39. };
  40. static irqreturn_t platform_mhu_rx_interrupt(int irq, void *p)
  41. {
  42. struct mbox_chan *chan = p;
  43. struct platform_mhu_link *mlink = chan->con_priv;
  44. u32 val;
  45. val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
  46. if (!val)
  47. return IRQ_NONE;
  48. mbox_chan_received_data(chan, (void *)&val);
  49. writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
  50. return IRQ_HANDLED;
  51. }
  52. static bool platform_mhu_last_tx_done(struct mbox_chan *chan)
  53. {
  54. struct platform_mhu_link *mlink = chan->con_priv;
  55. u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  56. return (val == 0);
  57. }
  58. static int platform_mhu_send_data(struct mbox_chan *chan, void *data)
  59. {
  60. struct platform_mhu_link *mlink = chan->con_priv;
  61. u32 *arg = data;
  62. writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
  63. return 0;
  64. }
  65. static int platform_mhu_startup(struct mbox_chan *chan)
  66. {
  67. struct platform_mhu_link *mlink = chan->con_priv;
  68. u32 val;
  69. int ret;
  70. val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
  71. writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
  72. ret = request_irq(mlink->irq, platform_mhu_rx_interrupt,
  73. IRQF_SHARED, "platform_mhu_link", chan);
  74. if (ret) {
  75. dev_err(chan->mbox->dev,
  76. "Unable to acquire IRQ %d\n", mlink->irq);
  77. return ret;
  78. }
  79. return 0;
  80. }
  81. static void platform_mhu_shutdown(struct mbox_chan *chan)
  82. {
  83. struct platform_mhu_link *mlink = chan->con_priv;
  84. free_irq(mlink->irq, chan);
  85. }
  86. static const struct mbox_chan_ops platform_mhu_ops = {
  87. .send_data = platform_mhu_send_data,
  88. .startup = platform_mhu_startup,
  89. .shutdown = platform_mhu_shutdown,
  90. .last_tx_done = platform_mhu_last_tx_done,
  91. };
  92. static int platform_mhu_probe(struct platform_device *pdev)
  93. {
  94. int i, err;
  95. struct platform_mhu *mhu;
  96. struct device *dev = &pdev->dev;
  97. int platform_mhu_reg[MHU_CHANS] = {
  98. MHU_SEC_OFFSET, MHU_LP_OFFSET, MHU_HP_OFFSET
  99. };
  100. /* Allocate memory for device */
  101. mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
  102. if (!mhu)
  103. return -ENOMEM;
  104. mhu->base = devm_platform_ioremap_resource(pdev, 0);
  105. if (IS_ERR(mhu->base)) {
  106. dev_err(dev, "ioremap failed\n");
  107. return PTR_ERR(mhu->base);
  108. }
  109. for (i = 0; i < MHU_CHANS; i++) {
  110. mhu->chan[i].con_priv = &mhu->mlink[i];
  111. mhu->mlink[i].irq = platform_get_irq(pdev, i);
  112. if (mhu->mlink[i].irq < 0)
  113. return mhu->mlink[i].irq;
  114. mhu->mlink[i].rx_reg = mhu->base + platform_mhu_reg[i];
  115. mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
  116. }
  117. mhu->mbox.dev = dev;
  118. mhu->mbox.chans = &mhu->chan[0];
  119. mhu->mbox.num_chans = MHU_CHANS;
  120. mhu->mbox.ops = &platform_mhu_ops;
  121. mhu->mbox.txdone_irq = false;
  122. mhu->mbox.txdone_poll = true;
  123. mhu->mbox.txpoll_period = 1;
  124. platform_set_drvdata(pdev, mhu);
  125. err = devm_mbox_controller_register(dev, &mhu->mbox);
  126. if (err) {
  127. dev_err(dev, "Failed to register mailboxes %d\n", err);
  128. return err;
  129. }
  130. dev_info(dev, "Platform MHU Mailbox registered\n");
  131. return 0;
  132. }
  133. static const struct of_device_id platform_mhu_dt_ids[] = {
  134. { .compatible = "amlogic,meson-gxbb-mhu", },
  135. { /* sentinel */ },
  136. };
  137. MODULE_DEVICE_TABLE(of, platform_mhu_dt_ids);
  138. static struct platform_driver platform_mhu_driver = {
  139. .probe = platform_mhu_probe,
  140. .driver = {
  141. .name = "platform-mhu",
  142. .of_match_table = platform_mhu_dt_ids,
  143. },
  144. };
  145. module_platform_driver(platform_mhu_driver);
  146. MODULE_LICENSE("GPL v2");
  147. MODULE_ALIAS("platform:platform-mhu");
  148. MODULE_DESCRIPTION("Platform MHU Driver");
  149. MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");