qcom-ipcc.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/irq.h>
  8. #include <linux/irqdomain.h>
  9. #include <linux/mailbox_controller.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <dt-bindings/mailbox/qcom-ipcc.h>
  13. /* IPCC Register offsets */
  14. #define IPCC_REG_SEND_ID 0x0c
  15. #define IPCC_REG_RECV_ID 0x10
  16. #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
  17. #define IPCC_REG_RECV_SIGNAL_DISABLE 0x18
  18. #define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c
  19. #define IPCC_REG_CLIENT_CLEAR 0x38
  20. #define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)
  21. #define IPCC_CLIENT_ID_MASK GENMASK(31, 16)
  22. #define IPCC_NO_PENDING_IRQ GENMASK(31, 0)
  23. /**
  24. * struct qcom_ipcc_chan_info - Per-mailbox-channel info
  25. * @client_id: The client-id to which the interrupt has to be triggered
  26. * @signal_id: The signal-id to which the interrupt has to be triggered
  27. */
  28. struct qcom_ipcc_chan_info {
  29. u16 client_id;
  30. u16 signal_id;
  31. };
  32. /**
  33. * struct qcom_ipcc - Holder for the mailbox driver
  34. * @dev: Device associated with this instance
  35. * @base: Base address of the IPCC frame associated to APSS
  36. * @irq_domain: The irq_domain associated with this instance
  37. * @chans: The mailbox channels array
  38. * @mchan: The per-mailbox channel info array
  39. * @mbox: The mailbox controller
  40. * @num_chans: Number of @chans elements
  41. * @irq: Summary irq
  42. */
  43. struct qcom_ipcc {
  44. struct device *dev;
  45. void __iomem *base;
  46. struct irq_domain *irq_domain;
  47. struct mbox_chan *chans;
  48. struct qcom_ipcc_chan_info *mchan;
  49. struct mbox_controller mbox;
  50. int num_chans;
  51. int irq;
  52. };
  53. static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
  54. {
  55. return container_of(mbox, struct qcom_ipcc, mbox);
  56. }
  57. static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
  58. {
  59. return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
  60. FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
  61. }
  62. static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
  63. {
  64. struct qcom_ipcc *ipcc = data;
  65. u32 hwirq;
  66. int virq;
  67. for (;;) {
  68. hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
  69. if (hwirq == IPCC_NO_PENDING_IRQ)
  70. break;
  71. virq = irq_find_mapping(ipcc->irq_domain, hwirq);
  72. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
  73. generic_handle_irq(virq);
  74. }
  75. return IRQ_HANDLED;
  76. }
  77. static void qcom_ipcc_mask_irq(struct irq_data *irqd)
  78. {
  79. struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
  80. irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  81. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
  82. }
  83. static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
  84. {
  85. struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
  86. irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  87. writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
  88. }
  89. static struct irq_chip qcom_ipcc_irq_chip = {
  90. .name = "ipcc",
  91. .irq_mask = qcom_ipcc_mask_irq,
  92. .irq_unmask = qcom_ipcc_unmask_irq,
  93. .flags = IRQCHIP_SKIP_SET_WAKE,
  94. };
  95. static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
  96. irq_hw_number_t hw)
  97. {
  98. struct qcom_ipcc *ipcc = d->host_data;
  99. irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
  100. irq_set_chip_data(irq, ipcc);
  101. irq_set_noprobe(irq);
  102. return 0;
  103. }
  104. static int qcom_ipcc_domain_xlate(struct irq_domain *d,
  105. struct device_node *node, const u32 *intspec,
  106. unsigned int intsize,
  107. unsigned long *out_hwirq,
  108. unsigned int *out_type)
  109. {
  110. if (intsize != 3)
  111. return -EINVAL;
  112. *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
  113. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  114. return 0;
  115. }
  116. static const struct irq_domain_ops qcom_ipcc_irq_ops = {
  117. .map = qcom_ipcc_domain_map,
  118. .xlate = qcom_ipcc_domain_xlate,
  119. };
  120. static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
  121. {
  122. struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
  123. struct qcom_ipcc_chan_info *mchan = chan->con_priv;
  124. u32 hwirq;
  125. hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
  126. writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
  127. return 0;
  128. }
  129. static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
  130. {
  131. chan->con_priv = NULL;
  132. }
  133. static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
  134. const struct of_phandle_args *ph)
  135. {
  136. struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
  137. struct qcom_ipcc_chan_info *mchan;
  138. struct mbox_chan *chan;
  139. struct device *dev;
  140. int chan_id;
  141. dev = ipcc->dev;
  142. if (ph->args_count != 2)
  143. return ERR_PTR(-EINVAL);
  144. for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) {
  145. chan = &ipcc->chans[chan_id];
  146. mchan = chan->con_priv;
  147. if (!mchan)
  148. break;
  149. else if (mchan->client_id == ph->args[0] &&
  150. mchan->signal_id == ph->args[1])
  151. return ERR_PTR(-EBUSY);
  152. }
  153. if (chan_id >= mbox->num_chans)
  154. return ERR_PTR(-EBUSY);
  155. mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL);
  156. if (!mchan)
  157. return ERR_PTR(-ENOMEM);
  158. mchan->client_id = ph->args[0];
  159. mchan->signal_id = ph->args[1];
  160. chan->con_priv = mchan;
  161. return chan;
  162. }
  163. static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
  164. .send_data = qcom_ipcc_mbox_send_data,
  165. .shutdown = qcom_ipcc_mbox_shutdown,
  166. };
  167. static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc,
  168. struct device_node *controller_dn)
  169. {
  170. struct of_phandle_args curr_ph;
  171. struct device_node *client_dn;
  172. struct mbox_controller *mbox;
  173. struct device *dev = ipcc->dev;
  174. int i, j, ret;
  175. /*
  176. * Find out the number of clients interested in this mailbox
  177. * and create channels accordingly.
  178. */
  179. ipcc->num_chans = 0;
  180. for_each_node_with_property(client_dn, "mboxes") {
  181. if (!of_device_is_available(client_dn))
  182. continue;
  183. i = of_count_phandle_with_args(client_dn,
  184. "mboxes", "#mbox-cells");
  185. for (j = 0; j < i; j++) {
  186. ret = of_parse_phandle_with_args(client_dn, "mboxes",
  187. "#mbox-cells", j, &curr_ph);
  188. of_node_put(curr_ph.np);
  189. if (!ret && curr_ph.np == controller_dn)
  190. ipcc->num_chans++;
  191. }
  192. }
  193. /* If no clients are found, skip registering as a mbox controller */
  194. if (!ipcc->num_chans)
  195. return 0;
  196. ipcc->chans = devm_kcalloc(dev, ipcc->num_chans,
  197. sizeof(struct mbox_chan), GFP_KERNEL);
  198. if (!ipcc->chans)
  199. return -ENOMEM;
  200. mbox = &ipcc->mbox;
  201. mbox->dev = dev;
  202. mbox->num_chans = ipcc->num_chans;
  203. mbox->chans = ipcc->chans;
  204. mbox->ops = &ipcc_mbox_chan_ops;
  205. mbox->of_xlate = qcom_ipcc_mbox_xlate;
  206. mbox->txdone_irq = false;
  207. mbox->txdone_poll = false;
  208. return devm_mbox_controller_register(dev, mbox);
  209. }
  210. static int qcom_ipcc_pm_resume(struct device *dev)
  211. {
  212. struct qcom_ipcc *ipcc = dev_get_drvdata(dev);
  213. u32 hwirq;
  214. int virq;
  215. hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
  216. if (hwirq == IPCC_NO_PENDING_IRQ)
  217. return 0;
  218. virq = irq_find_mapping(ipcc->irq_domain, hwirq);
  219. dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq,
  220. FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq));
  221. return 0;
  222. }
  223. static int qcom_ipcc_probe(struct platform_device *pdev)
  224. {
  225. struct qcom_ipcc *ipcc;
  226. static int id;
  227. char *name;
  228. int ret;
  229. ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
  230. if (!ipcc)
  231. return -ENOMEM;
  232. ipcc->dev = &pdev->dev;
  233. ipcc->base = devm_platform_ioremap_resource(pdev, 0);
  234. if (IS_ERR(ipcc->base))
  235. return PTR_ERR(ipcc->base);
  236. ipcc->irq = platform_get_irq(pdev, 0);
  237. if (ipcc->irq < 0)
  238. return ipcc->irq;
  239. name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ipcc_%d", id++);
  240. if (!name)
  241. return -ENOMEM;
  242. ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
  243. &qcom_ipcc_irq_ops, ipcc);
  244. if (!ipcc->irq_domain)
  245. return -ENOMEM;
  246. ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node);
  247. if (ret)
  248. goto err_mbox;
  249. ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
  250. IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND |
  251. IRQF_NO_THREAD, name, ipcc);
  252. if (ret < 0) {
  253. dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
  254. goto err_req_irq;
  255. }
  256. platform_set_drvdata(pdev, ipcc);
  257. return 0;
  258. err_req_irq:
  259. if (ipcc->num_chans)
  260. mbox_controller_unregister(&ipcc->mbox);
  261. err_mbox:
  262. irq_domain_remove(ipcc->irq_domain);
  263. return ret;
  264. }
  265. static void qcom_ipcc_remove(struct platform_device *pdev)
  266. {
  267. struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
  268. disable_irq_wake(ipcc->irq);
  269. irq_domain_remove(ipcc->irq_domain);
  270. }
  271. static const struct of_device_id qcom_ipcc_of_match[] = {
  272. { .compatible = "qcom,ipcc"},
  273. {}
  274. };
  275. MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
  276. static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {
  277. NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume)
  278. };
  279. static struct platform_driver qcom_ipcc_driver = {
  280. .probe = qcom_ipcc_probe,
  281. .remove_new = qcom_ipcc_remove,
  282. .driver = {
  283. .name = "qcom-ipcc",
  284. .of_match_table = qcom_ipcc_of_match,
  285. .suppress_bind_attrs = true,
  286. .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops),
  287. },
  288. };
  289. static int __init qcom_ipcc_init(void)
  290. {
  291. return platform_driver_register(&qcom_ipcc_driver);
  292. }
  293. arch_initcall(qcom_ipcc_init);
  294. MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
  295. MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
  296. MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
  297. MODULE_LICENSE("GPL v2");