aspeed-video.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. // Copyright 2020 IBM Corp.
  3. // Copyright (c) 2019-2020 Intel Corporation
  4. #include <linux/atomic.h>
  5. #include <linux/bitfield.h>
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/jiffies.h>
  12. #include <linux/module.h>
  13. #include <linux/mutex.h>
  14. #include <linux/of.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_reserved_mem.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/sched.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/string.h>
  21. #include <linux/v4l2-controls.h>
  22. #include <linux/videodev2.h>
  23. #include <linux/wait.h>
  24. #include <linux/workqueue.h>
  25. #include <linux/debugfs.h>
  26. #include <linux/ktime.h>
  27. #include <media/v4l2-ctrls.h>
  28. #include <media/v4l2-dev.h>
  29. #include <media/v4l2-device.h>
  30. #include <media/v4l2-dv-timings.h>
  31. #include <media/v4l2-event.h>
  32. #include <media/v4l2-ioctl.h>
  33. #include <media/videobuf2-dma-contig.h>
  34. #include <uapi/linux/aspeed-video.h>
  35. #define ASPEED_VIDEO_V4L2_MIN_BUF_REQ 3
  36. #define DEVICE_NAME "aspeed-video"
  37. #define ASPEED_VIDEO_JPEG_NUM_QUALITIES 12
  38. #define ASPEED_VIDEO_JPEG_HEADER_SIZE 10
  39. #define ASPEED_VIDEO_JPEG_QUANT_SIZE 116
  40. #define ASPEED_VIDEO_JPEG_DCT_SIZE 34
  41. #define MAX_FRAME_RATE 60
  42. #define MAX_HEIGHT 1200
  43. #define MAX_WIDTH 1920
  44. #define MIN_HEIGHT 480
  45. #define MIN_WIDTH 640
  46. #define NUM_POLARITY_CHECKS 10
  47. #define INVALID_RESOLUTION_RETRIES 2
  48. #define INVALID_RESOLUTION_DELAY msecs_to_jiffies(250)
  49. #define RESOLUTION_CHANGE_DELAY msecs_to_jiffies(500)
  50. #define MODE_DETECT_TIMEOUT msecs_to_jiffies(500)
  51. #define STOP_TIMEOUT msecs_to_jiffies(1000)
  52. #define DIRECT_FETCH_THRESHOLD 0x0c0000 /* 1024 * 768 */
  53. #define VE_MAX_SRC_BUFFER_SIZE 0x8ca000 /* 1920 * 1200, 32bpp */
  54. #define VE_JPEG_HEADER_SIZE 0x006000 /* 512 * 12 * 4 */
  55. #define VE_BCD_BUFF_SIZE 0x9000 /* (1920/8) * (1200/8) */
  56. #define VE_PROTECTION_KEY 0x000
  57. #define VE_PROTECTION_KEY_UNLOCK 0x1a038aa8
  58. #define VE_SEQ_CTRL 0x004
  59. #define VE_SEQ_CTRL_TRIG_MODE_DET BIT(0)
  60. #define VE_SEQ_CTRL_TRIG_CAPTURE BIT(1)
  61. #define VE_SEQ_CTRL_FORCE_IDLE BIT(2)
  62. #define VE_SEQ_CTRL_MULT_FRAME BIT(3)
  63. #define VE_SEQ_CTRL_TRIG_COMP BIT(4)
  64. #define VE_SEQ_CTRL_AUTO_COMP BIT(5)
  65. #define VE_SEQ_CTRL_EN_WATCHDOG BIT(7)
  66. #define VE_SEQ_CTRL_YUV420 BIT(10)
  67. #define VE_SEQ_CTRL_COMP_FMT GENMASK(11, 10)
  68. #define VE_SEQ_CTRL_HALT BIT(12)
  69. #define VE_SEQ_CTRL_EN_WATCHDOG_COMP BIT(14)
  70. #define VE_SEQ_CTRL_TRIG_JPG BIT(15)
  71. #define VE_SEQ_CTRL_CAP_BUSY BIT(16)
  72. #define VE_SEQ_CTRL_COMP_BUSY BIT(18)
  73. #define AST2500_VE_SEQ_CTRL_JPEG_MODE BIT(13)
  74. #define AST2400_VE_SEQ_CTRL_JPEG_MODE BIT(8)
  75. #define VE_CTRL 0x008
  76. #define VE_CTRL_HSYNC_POL BIT(0)
  77. #define VE_CTRL_VSYNC_POL BIT(1)
  78. #define VE_CTRL_SOURCE BIT(2)
  79. #define VE_CTRL_INT_DE BIT(4)
  80. #define VE_CTRL_DIRECT_FETCH BIT(5)
  81. #define VE_CTRL_CAPTURE_FMT GENMASK(7, 6)
  82. #define VE_CTRL_AUTO_OR_CURSOR BIT(8)
  83. #define VE_CTRL_CLK_INVERSE BIT(11)
  84. #define VE_CTRL_CLK_DELAY GENMASK(11, 9)
  85. #define VE_CTRL_INTERLACE BIT(14)
  86. #define VE_CTRL_HSYNC_POL_CTRL BIT(15)
  87. #define VE_CTRL_FRC GENMASK(23, 16)
  88. #define VE_TGS_0 0x00c
  89. #define VE_TGS_1 0x010
  90. #define VE_TGS_FIRST GENMASK(28, 16)
  91. #define VE_TGS_LAST GENMASK(12, 0)
  92. #define VE_SCALING_FACTOR 0x014
  93. #define VE_SCALING_FILTER0 0x018
  94. #define VE_SCALING_FILTER1 0x01c
  95. #define VE_SCALING_FILTER2 0x020
  96. #define VE_SCALING_FILTER3 0x024
  97. #define VE_BCD_CTRL 0x02C
  98. #define VE_BCD_CTRL_EN_BCD BIT(0)
  99. #define VE_BCD_CTRL_EN_ABCD BIT(1)
  100. #define VE_BCD_CTRL_EN_CB BIT(2)
  101. #define VE_BCD_CTRL_THR GENMASK(23, 16)
  102. #define VE_BCD_CTRL_ABCD_THR GENMASK(31, 24)
  103. #define VE_CAP_WINDOW 0x030
  104. #define VE_COMP_WINDOW 0x034
  105. #define VE_COMP_PROC_OFFSET 0x038
  106. #define VE_COMP_OFFSET 0x03c
  107. #define VE_JPEG_ADDR 0x040
  108. #define VE_SRC0_ADDR 0x044
  109. #define VE_SRC_SCANLINE_OFFSET 0x048
  110. #define VE_SRC1_ADDR 0x04c
  111. #define VE_BCD_ADDR 0x050
  112. #define VE_COMP_ADDR 0x054
  113. #define VE_STREAM_BUF_SIZE 0x058
  114. #define VE_STREAM_BUF_SIZE_N_PACKETS GENMASK(5, 3)
  115. #define VE_STREAM_BUF_SIZE_P_SIZE GENMASK(2, 0)
  116. #define VE_COMP_CTRL 0x060
  117. #define VE_COMP_CTRL_VQ_DCT_ONLY BIT(0)
  118. #define VE_COMP_CTRL_VQ_4COLOR BIT(1)
  119. #define VE_COMP_CTRL_QUANTIZE BIT(2)
  120. #define VE_COMP_CTRL_EN_BQ BIT(4)
  121. #define VE_COMP_CTRL_EN_CRYPTO BIT(5)
  122. #define VE_COMP_CTRL_DCT_CHR GENMASK(10, 6)
  123. #define VE_COMP_CTRL_DCT_LUM GENMASK(15, 11)
  124. #define VE_COMP_CTRL_EN_HQ BIT(16)
  125. #define VE_COMP_CTRL_RSVD BIT(19)
  126. #define VE_COMP_CTRL_ENCODE GENMASK(21, 20)
  127. #define VE_COMP_CTRL_HQ_DCT_CHR GENMASK(26, 22)
  128. #define VE_COMP_CTRL_HQ_DCT_LUM GENMASK(31, 27)
  129. #define VE_CB_ADDR 0x06C
  130. #define AST2400_VE_COMP_SIZE_READ_BACK 0x078
  131. #define AST2600_VE_COMP_SIZE_READ_BACK 0x084
  132. #define VE_SRC_LR_EDGE_DET 0x090
  133. #define VE_SRC_LR_EDGE_DET_LEFT GENMASK(11, 0)
  134. #define VE_SRC_LR_EDGE_DET_NO_V BIT(12)
  135. #define VE_SRC_LR_EDGE_DET_NO_H BIT(13)
  136. #define VE_SRC_LR_EDGE_DET_NO_DISP BIT(14)
  137. #define VE_SRC_LR_EDGE_DET_NO_CLK BIT(15)
  138. #define VE_SRC_LR_EDGE_DET_RT GENMASK(27, 16)
  139. #define VE_SRC_LR_EDGE_DET_INTERLACE BIT(31)
  140. #define VE_SRC_TB_EDGE_DET 0x094
  141. #define VE_SRC_TB_EDGE_DET_TOP GENMASK(12, 0)
  142. #define VE_SRC_TB_EDGE_DET_BOT GENMASK(28, 16)
  143. #define VE_MODE_DETECT_STATUS 0x098
  144. #define VE_MODE_DETECT_H_PERIOD GENMASK(11, 0)
  145. #define VE_MODE_DETECT_EXTSRC_ADC BIT(12)
  146. #define VE_MODE_DETECT_H_STABLE BIT(13)
  147. #define VE_MODE_DETECT_V_STABLE BIT(14)
  148. #define VE_MODE_DETECT_V_LINES GENMASK(27, 16)
  149. #define VE_MODE_DETECT_STATUS_VSYNC BIT(28)
  150. #define VE_MODE_DETECT_STATUS_HSYNC BIT(29)
  151. #define VE_MODE_DETECT_VSYNC_RDY BIT(30)
  152. #define VE_MODE_DETECT_HSYNC_RDY BIT(31)
  153. #define VE_SYNC_STATUS 0x09c
  154. #define VE_SYNC_STATUS_HSYNC GENMASK(11, 0)
  155. #define VE_SYNC_STATUS_VSYNC GENMASK(27, 16)
  156. #define VE_H_TOTAL_PIXELS 0x0A0
  157. #define VE_INTERRUPT_CTRL 0x304
  158. #define VE_INTERRUPT_STATUS 0x308
  159. #define VE_INTERRUPT_MODE_DETECT_WD BIT(0)
  160. #define VE_INTERRUPT_CAPTURE_COMPLETE BIT(1)
  161. #define VE_INTERRUPT_COMP_READY BIT(2)
  162. #define VE_INTERRUPT_COMP_COMPLETE BIT(3)
  163. #define VE_INTERRUPT_MODE_DETECT BIT(4)
  164. #define VE_INTERRUPT_FRAME_COMPLETE BIT(5)
  165. #define VE_INTERRUPT_DECODE_ERR BIT(6)
  166. #define VE_INTERRUPT_HALT_READY BIT(8)
  167. #define VE_INTERRUPT_HANG_WD BIT(9)
  168. #define VE_INTERRUPT_STREAM_DESC BIT(10)
  169. #define VE_INTERRUPT_VSYNC_DESC BIT(11)
  170. #define VE_MODE_DETECT 0x30c
  171. #define VE_MODE_DT_HOR_TOLER GENMASK(31, 28)
  172. #define VE_MODE_DT_VER_TOLER GENMASK(27, 24)
  173. #define VE_MODE_DT_HOR_STABLE GENMASK(23, 20)
  174. #define VE_MODE_DT_VER_STABLE GENMASK(19, 16)
  175. #define VE_MODE_DT_EDG_THROD GENMASK(15, 8)
  176. #define VE_MEM_RESTRICT_START 0x310
  177. #define VE_MEM_RESTRICT_END 0x314
  178. /*
  179. * VIDEO_MODE_DETECT_DONE: a flag raised if signal lock
  180. * VIDEO_RES_CHANGE: a flag raised if res_change work on-going
  181. * VIDEO_RES_DETECT: a flag raised if res. detection on-going
  182. * VIDEO_STREAMING: a flag raised if user requires stream-on
  183. * VIDEO_FRAME_INPRG: a flag raised if hw working on a frame
  184. * VIDEO_STOPPED: a flag raised if device release
  185. * VIDEO_CLOCKS_ON: a flag raised if clk is on
  186. */
  187. enum {
  188. VIDEO_MODE_DETECT_DONE,
  189. VIDEO_RES_CHANGE,
  190. VIDEO_RES_DETECT,
  191. VIDEO_STREAMING,
  192. VIDEO_FRAME_INPRG,
  193. VIDEO_STOPPED,
  194. VIDEO_CLOCKS_ON,
  195. };
  196. enum aspeed_video_format {
  197. VIDEO_FMT_STANDARD = 0,
  198. VIDEO_FMT_ASPEED,
  199. VIDEO_FMT_MAX = VIDEO_FMT_ASPEED
  200. };
  201. // for VE_CTRL_CAPTURE_FMT
  202. enum aspeed_video_capture_format {
  203. VIDEO_CAP_FMT_YUV_STUDIO_SWING = 0,
  204. VIDEO_CAP_FMT_YUV_FULL_SWING,
  205. VIDEO_CAP_FMT_RGB,
  206. VIDEO_CAP_FMT_GRAY,
  207. VIDEO_CAP_FMT_MAX
  208. };
  209. struct aspeed_video_addr {
  210. unsigned int size;
  211. dma_addr_t dma;
  212. void *virt;
  213. };
  214. struct aspeed_video_buffer {
  215. struct vb2_v4l2_buffer vb;
  216. struct list_head link;
  217. };
  218. struct aspeed_video_perf {
  219. ktime_t last_sample;
  220. u32 totaltime;
  221. u32 duration;
  222. u32 duration_min;
  223. u32 duration_max;
  224. };
  225. #define to_aspeed_video_buffer(x) \
  226. container_of((x), struct aspeed_video_buffer, vb)
  227. /*
  228. * struct aspeed_video - driver data
  229. *
  230. * res_work: holds the delayed_work for res-detection if unlock
  231. * buffers: holds the list of buffer queued from user
  232. * flags: holds the state of video
  233. * sequence: holds the last number of frame completed
  234. * max_compressed_size: holds max compressed stream's size
  235. * srcs: holds the buffer information for srcs
  236. * jpeg: holds the buffer information for jpeg header
  237. * bcd: holds the buffer information for bcd work
  238. * yuv420: a flag raised if JPEG subsampling is 420
  239. * format: holds the video format
  240. * hq_mode: a flag raised if HQ is enabled. Only for VIDEO_FMT_ASPEED
  241. * frame_rate: holds the frame_rate
  242. * jpeg_quality: holds jpeq's quality (0~11)
  243. * jpeg_hq_quality: holds hq's quality (1~12) only if hq_mode enabled
  244. * frame_bottom: end position of video data in vertical direction
  245. * frame_left: start position of video data in horizontal direction
  246. * frame_right: end position of video data in horizontal direction
  247. * frame_top: start position of video data in vertical direction
  248. * perf: holds the statistics primary for debugfs
  249. */
  250. struct aspeed_video {
  251. void __iomem *base;
  252. struct clk *eclk;
  253. struct clk *vclk;
  254. struct device *dev;
  255. struct v4l2_ctrl_handler ctrl_handler;
  256. struct v4l2_device v4l2_dev;
  257. struct v4l2_pix_format pix_fmt;
  258. struct v4l2_bt_timings active_timings;
  259. struct v4l2_bt_timings detected_timings;
  260. u32 v4l2_input_status;
  261. struct vb2_queue queue;
  262. struct video_device vdev;
  263. struct mutex video_lock; /* v4l2 and videobuf2 lock */
  264. u32 jpeg_mode;
  265. u32 comp_size_read;
  266. wait_queue_head_t wait;
  267. spinlock_t lock; /* buffer list lock */
  268. struct delayed_work res_work;
  269. struct list_head buffers;
  270. unsigned long flags;
  271. unsigned int sequence;
  272. unsigned int max_compressed_size;
  273. struct aspeed_video_addr srcs[2];
  274. struct aspeed_video_addr jpeg;
  275. struct aspeed_video_addr bcd;
  276. bool yuv420;
  277. enum aspeed_video_format format;
  278. bool hq_mode;
  279. unsigned int frame_rate;
  280. unsigned int jpeg_quality;
  281. unsigned int jpeg_hq_quality;
  282. unsigned int frame_bottom;
  283. unsigned int frame_left;
  284. unsigned int frame_right;
  285. unsigned int frame_top;
  286. struct aspeed_video_perf perf;
  287. };
  288. #define to_aspeed_video(x) container_of((x), struct aspeed_video, v4l2_dev)
  289. struct aspeed_video_config {
  290. u32 jpeg_mode;
  291. u32 comp_size_read;
  292. };
  293. static const struct aspeed_video_config ast2400_config = {
  294. .jpeg_mode = AST2400_VE_SEQ_CTRL_JPEG_MODE,
  295. .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK,
  296. };
  297. static const struct aspeed_video_config ast2500_config = {
  298. .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE,
  299. .comp_size_read = AST2400_VE_COMP_SIZE_READ_BACK,
  300. };
  301. static const struct aspeed_video_config ast2600_config = {
  302. .jpeg_mode = AST2500_VE_SEQ_CTRL_JPEG_MODE,
  303. .comp_size_read = AST2600_VE_COMP_SIZE_READ_BACK,
  304. };
  305. static const u32 aspeed_video_jpeg_header[ASPEED_VIDEO_JPEG_HEADER_SIZE] = {
  306. 0xe0ffd8ff, 0x464a1000, 0x01004649, 0x60000101, 0x00006000, 0x0f00feff,
  307. 0x00002d05, 0x00000000, 0x00000000, 0x00dbff00
  308. };
  309. static const u32 aspeed_video_jpeg_quant[ASPEED_VIDEO_JPEG_QUANT_SIZE] = {
  310. 0x081100c0, 0x00000000, 0x00110103, 0x03011102, 0xc4ff0111, 0x00001f00,
  311. 0x01010501, 0x01010101, 0x00000000, 0x00000000, 0x04030201, 0x08070605,
  312. 0xff0b0a09, 0x10b500c4, 0x03010200, 0x03040203, 0x04040505, 0x7d010000,
  313. 0x00030201, 0x12051104, 0x06413121, 0x07615113, 0x32147122, 0x08a19181,
  314. 0xc1b14223, 0xf0d15215, 0x72623324, 0x160a0982, 0x1a191817, 0x28272625,
  315. 0x35342a29, 0x39383736, 0x4544433a, 0x49484746, 0x5554534a, 0x59585756,
  316. 0x6564635a, 0x69686766, 0x7574736a, 0x79787776, 0x8584837a, 0x89888786,
  317. 0x9493928a, 0x98979695, 0xa3a29a99, 0xa7a6a5a4, 0xb2aaa9a8, 0xb6b5b4b3,
  318. 0xbab9b8b7, 0xc5c4c3c2, 0xc9c8c7c6, 0xd4d3d2ca, 0xd8d7d6d5, 0xe2e1dad9,
  319. 0xe6e5e4e3, 0xeae9e8e7, 0xf4f3f2f1, 0xf8f7f6f5, 0xc4fffaf9, 0x00011f00,
  320. 0x01010103, 0x01010101, 0x00000101, 0x00000000, 0x04030201, 0x08070605,
  321. 0xff0b0a09, 0x11b500c4, 0x02010200, 0x04030404, 0x04040507, 0x77020100,
  322. 0x03020100, 0x21050411, 0x41120631, 0x71610751, 0x81322213, 0x91421408,
  323. 0x09c1b1a1, 0xf0523323, 0xd1726215, 0x3424160a, 0x17f125e1, 0x261a1918,
  324. 0x2a292827, 0x38373635, 0x44433a39, 0x48474645, 0x54534a49, 0x58575655,
  325. 0x64635a59, 0x68676665, 0x74736a69, 0x78777675, 0x83827a79, 0x87868584,
  326. 0x928a8988, 0x96959493, 0x9a999897, 0xa5a4a3a2, 0xa9a8a7a6, 0xb4b3b2aa,
  327. 0xb8b7b6b5, 0xc3c2bab9, 0xc7c6c5c4, 0xd2cac9c8, 0xd6d5d4d3, 0xdad9d8d7,
  328. 0xe5e4e3e2, 0xe9e8e7e6, 0xf4f3f2ea, 0xf8f7f6f5, 0xdafffaf9, 0x01030c00,
  329. 0x03110200, 0x003f0011
  330. };
  331. static const u32 aspeed_video_jpeg_dct[ASPEED_VIDEO_JPEG_NUM_QUALITIES]
  332. [ASPEED_VIDEO_JPEG_DCT_SIZE] = {
  333. { 0x0d140043, 0x0c0f110f, 0x11101114, 0x17141516, 0x1e20321e,
  334. 0x3d1e1b1b, 0x32242e2b, 0x4b4c3f48, 0x44463f47, 0x61735a50,
  335. 0x566c5550, 0x88644644, 0x7a766c65, 0x4d808280, 0x8c978d60,
  336. 0x7e73967d, 0xdbff7b80, 0x1f014300, 0x272d2121, 0x3030582d,
  337. 0x697bb958, 0xb8b9b97b, 0xb9b8a6a6, 0xb9b9b9b9, 0xb9b9b9b9,
  338. 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9,
  339. 0xb9b9b9b9, 0xb9b9b9b9, 0xb9b9b9b9, 0xffb9b9b9 },
  340. { 0x0c110043, 0x0a0d0f0d, 0x0f0e0f11, 0x14111213, 0x1a1c2b1a,
  341. 0x351a1818, 0x2b1f2826, 0x4142373f, 0x3c3d373e, 0x55644e46,
  342. 0x4b5f4a46, 0x77573d3c, 0x6b675f58, 0x43707170, 0x7a847b54,
  343. 0x6e64836d, 0xdbff6c70, 0x1b014300, 0x22271d1d, 0x2a2a4c27,
  344. 0x5b6ba04c, 0xa0a0a06b, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0,
  345. 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0,
  346. 0xa0a0a0a0, 0xa0a0a0a0, 0xa0a0a0a0, 0xffa0a0a0 },
  347. { 0x090e0043, 0x090a0c0a, 0x0c0b0c0e, 0x110e0f10, 0x15172415,
  348. 0x2c151313, 0x241a211f, 0x36372e34, 0x31322e33, 0x4653413a,
  349. 0x3e4e3d3a, 0x62483231, 0x58564e49, 0x385d5e5d, 0x656d6645,
  350. 0x5b536c5a, 0xdbff595d, 0x16014300, 0x1c201818, 0x22223f20,
  351. 0x4b58853f, 0x85858558, 0x85858585, 0x85858585, 0x85858585,
  352. 0x85858585, 0x85858585, 0x85858585, 0x85858585, 0x85858585,
  353. 0x85858585, 0x85858585, 0x85858585, 0xff858585 },
  354. { 0x070b0043, 0x07080a08, 0x0a090a0b, 0x0d0b0c0c, 0x11121c11,
  355. 0x23110f0f, 0x1c141a19, 0x2b2b2429, 0x27282428, 0x3842332e,
  356. 0x313e302e, 0x4e392827, 0x46443e3a, 0x2c4a4a4a, 0x50565137,
  357. 0x48425647, 0xdbff474a, 0x12014300, 0x161a1313, 0x1c1c331a,
  358. 0x3d486c33, 0x6c6c6c48, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c,
  359. 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c,
  360. 0x6c6c6c6c, 0x6c6c6c6c, 0x6c6c6c6c, 0xff6c6c6c },
  361. { 0x06090043, 0x05060706, 0x07070709, 0x0a09090a, 0x0d0e160d,
  362. 0x1b0d0c0c, 0x16101413, 0x21221c20, 0x1e1f1c20, 0x2b332824,
  363. 0x26302624, 0x3d2d1f1e, 0x3735302d, 0x22393a39, 0x3f443f2b,
  364. 0x38334338, 0xdbff3739, 0x0d014300, 0x11130e0e, 0x15152613,
  365. 0x2d355026, 0x50505035, 0x50505050, 0x50505050, 0x50505050,
  366. 0x50505050, 0x50505050, 0x50505050, 0x50505050, 0x50505050,
  367. 0x50505050, 0x50505050, 0x50505050, 0xff505050 },
  368. { 0x04060043, 0x03040504, 0x05040506, 0x07060606, 0x09090f09,
  369. 0x12090808, 0x0f0a0d0d, 0x16161315, 0x14151315, 0x1d221b18,
  370. 0x19201918, 0x281e1514, 0x2423201e, 0x17262726, 0x2a2d2a1c,
  371. 0x25222d25, 0xdbff2526, 0x09014300, 0x0b0d0a0a, 0x0e0e1a0d,
  372. 0x1f25371a, 0x37373725, 0x37373737, 0x37373737, 0x37373737,
  373. 0x37373737, 0x37373737, 0x37373737, 0x37373737, 0x37373737,
  374. 0x37373737, 0x37373737, 0x37373737, 0xff373737 },
  375. { 0x02030043, 0x01020202, 0x02020203, 0x03030303, 0x04040704,
  376. 0x09040404, 0x07050606, 0x0b0b090a, 0x0a0a090a, 0x0e110d0c,
  377. 0x0c100c0c, 0x140f0a0a, 0x1211100f, 0x0b131313, 0x1516150e,
  378. 0x12111612, 0xdbff1213, 0x04014300, 0x05060505, 0x07070d06,
  379. 0x0f121b0d, 0x1b1b1b12, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b,
  380. 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b,
  381. 0x1b1b1b1b, 0x1b1b1b1b, 0x1b1b1b1b, 0xff1b1b1b },
  382. { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503,
  383. 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908,
  384. 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09,
  385. 0x0c0b0f0c, 0xdbff0c0c, 0x03014300, 0x03040303, 0x04040804,
  386. 0x0a0c1208, 0x1212120c, 0x12121212, 0x12121212, 0x12121212,
  387. 0x12121212, 0x12121212, 0x12121212, 0x12121212, 0x12121212,
  388. 0x12121212, 0x12121212, 0x12121212, 0xff121212 },
  389. { 0x01020043, 0x01010101, 0x01010102, 0x02020202, 0x03030503,
  390. 0x06030202, 0x05030404, 0x07070607, 0x06070607, 0x090b0908,
  391. 0x080a0808, 0x0d0a0706, 0x0c0b0a0a, 0x070c0d0c, 0x0e0f0e09,
  392. 0x0c0b0f0c, 0xdbff0c0c, 0x02014300, 0x03030202, 0x04040703,
  393. 0x080a0f07, 0x0f0f0f0a, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f,
  394. 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f,
  395. 0x0f0f0f0f, 0x0f0f0f0f, 0x0f0f0f0f, 0xff0f0f0f },
  396. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x02020302,
  397. 0x04020202, 0x03020303, 0x05050405, 0x05050405, 0x07080606,
  398. 0x06080606, 0x0a070505, 0x09080807, 0x05090909, 0x0a0b0a07,
  399. 0x09080b09, 0xdbff0909, 0x02014300, 0x02030202, 0x03030503,
  400. 0x07080c05, 0x0c0c0c08, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c,
  401. 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c,
  402. 0x0c0c0c0c, 0x0c0c0c0c, 0x0c0c0c0c, 0xff0c0c0c },
  403. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010201,
  404. 0x03010101, 0x02010202, 0x03030303, 0x03030303, 0x04050404,
  405. 0x04050404, 0x06050303, 0x06050505, 0x03060606, 0x07070704,
  406. 0x06050706, 0xdbff0606, 0x01014300, 0x01020101, 0x02020402,
  407. 0x05060904, 0x09090906, 0x09090909, 0x09090909, 0x09090909,
  408. 0x09090909, 0x09090909, 0x09090909, 0x09090909, 0x09090909,
  409. 0x09090909, 0x09090909, 0x09090909, 0xff090909 },
  410. { 0x01010043, 0x01010101, 0x01010101, 0x01010101, 0x01010101,
  411. 0x01010101, 0x01010101, 0x01010101, 0x01010101, 0x02020202,
  412. 0x02020202, 0x03020101, 0x03020202, 0x01030303, 0x03030302,
  413. 0x03020303, 0xdbff0403, 0x01014300, 0x01010101, 0x01010201,
  414. 0x03040602, 0x06060604, 0x06060606, 0x06060606, 0x06060606,
  415. 0x06060606, 0x06060606, 0x06060606, 0x06060606, 0x06060606,
  416. 0x06060606, 0x06060606, 0x06060606, 0xff060606 }
  417. };
  418. static const struct v4l2_dv_timings_cap aspeed_video_timings_cap = {
  419. .type = V4L2_DV_BT_656_1120,
  420. .bt = {
  421. .min_width = MIN_WIDTH,
  422. .max_width = MAX_WIDTH,
  423. .min_height = MIN_HEIGHT,
  424. .max_height = MAX_HEIGHT,
  425. .min_pixelclock = 6574080, /* 640 x 480 x 24Hz */
  426. .max_pixelclock = 138240000, /* 1920 x 1200 x 60Hz */
  427. .standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
  428. V4L2_DV_BT_STD_CVT | V4L2_DV_BT_STD_GTF,
  429. .capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
  430. V4L2_DV_BT_CAP_REDUCED_BLANKING |
  431. V4L2_DV_BT_CAP_CUSTOM,
  432. },
  433. };
  434. static const char * const format_str[] = {"Standard JPEG",
  435. "Aspeed JPEG"};
  436. static unsigned int debug;
  437. static bool aspeed_video_alloc_buf(struct aspeed_video *video,
  438. struct aspeed_video_addr *addr,
  439. unsigned int size);
  440. static void aspeed_video_free_buf(struct aspeed_video *video,
  441. struct aspeed_video_addr *addr);
  442. static void aspeed_video_init_jpeg_table(u32 *table, bool yuv420)
  443. {
  444. int i;
  445. unsigned int base;
  446. for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) {
  447. base = 256 * i; /* AST HW requires this header spacing */
  448. memcpy(&table[base], aspeed_video_jpeg_header,
  449. sizeof(aspeed_video_jpeg_header));
  450. base += ASPEED_VIDEO_JPEG_HEADER_SIZE;
  451. memcpy(&table[base], aspeed_video_jpeg_dct[i],
  452. sizeof(aspeed_video_jpeg_dct[i]));
  453. base += ASPEED_VIDEO_JPEG_DCT_SIZE;
  454. memcpy(&table[base], aspeed_video_jpeg_quant,
  455. sizeof(aspeed_video_jpeg_quant));
  456. if (yuv420)
  457. table[base + 2] = 0x00220103;
  458. }
  459. }
  460. // just update jpeg dct table per 420/444
  461. static void aspeed_video_update_jpeg_table(u32 *table, bool yuv420)
  462. {
  463. int i;
  464. unsigned int base;
  465. for (i = 0; i < ASPEED_VIDEO_JPEG_NUM_QUALITIES; i++) {
  466. base = 256 * i; /* AST HW requires this header spacing */
  467. base += ASPEED_VIDEO_JPEG_HEADER_SIZE +
  468. ASPEED_VIDEO_JPEG_DCT_SIZE;
  469. table[base + 2] = (yuv420) ? 0x00220103 : 0x00110103;
  470. }
  471. }
  472. static void aspeed_video_update(struct aspeed_video *video, u32 reg, u32 clear,
  473. u32 bits)
  474. {
  475. u32 t = readl(video->base + reg);
  476. u32 before = t;
  477. t &= ~clear;
  478. t |= bits;
  479. writel(t, video->base + reg);
  480. v4l2_dbg(3, debug, &video->v4l2_dev, "update %03x[%08x -> %08x]\n",
  481. reg, before, readl(video->base + reg));
  482. }
  483. static u32 aspeed_video_read(struct aspeed_video *video, u32 reg)
  484. {
  485. u32 t = readl(video->base + reg);
  486. v4l2_dbg(3, debug, &video->v4l2_dev, "read %03x[%08x]\n", reg, t);
  487. return t;
  488. }
  489. static void aspeed_video_write(struct aspeed_video *video, u32 reg, u32 val)
  490. {
  491. writel(val, video->base + reg);
  492. v4l2_dbg(3, debug, &video->v4l2_dev, "write %03x[%08x]\n", reg,
  493. readl(video->base + reg));
  494. }
  495. static void update_perf(struct aspeed_video_perf *p)
  496. {
  497. struct aspeed_video *v = container_of(p, struct aspeed_video,
  498. perf);
  499. p->duration =
  500. ktime_to_ms(ktime_sub(ktime_get(), p->last_sample));
  501. p->totaltime += p->duration;
  502. p->duration_max = max(p->duration, p->duration_max);
  503. p->duration_min = min(p->duration, p->duration_min);
  504. v4l2_dbg(2, debug, &v->v4l2_dev, "time consumed: %d ms\n",
  505. p->duration);
  506. }
  507. static int aspeed_video_start_frame(struct aspeed_video *video)
  508. {
  509. dma_addr_t addr;
  510. unsigned long flags;
  511. struct aspeed_video_buffer *buf;
  512. u32 seq_ctrl = aspeed_video_read(video, VE_SEQ_CTRL);
  513. bool bcd_buf_need = (video->format != VIDEO_FMT_STANDARD);
  514. if (video->v4l2_input_status) {
  515. v4l2_dbg(1, debug, &video->v4l2_dev, "No signal; don't start frame\n");
  516. return 0;
  517. }
  518. if (!(seq_ctrl & VE_SEQ_CTRL_COMP_BUSY) ||
  519. !(seq_ctrl & VE_SEQ_CTRL_CAP_BUSY)) {
  520. v4l2_dbg(1, debug, &video->v4l2_dev, "Engine busy; don't start frame\n");
  521. return -EBUSY;
  522. }
  523. if (bcd_buf_need && !video->bcd.size) {
  524. if (!aspeed_video_alloc_buf(video, &video->bcd,
  525. VE_BCD_BUFF_SIZE)) {
  526. dev_err(video->dev, "Failed to allocate BCD buffer\n");
  527. dev_err(video->dev, "don't start frame\n");
  528. return -ENOMEM;
  529. }
  530. aspeed_video_write(video, VE_BCD_ADDR, video->bcd.dma);
  531. v4l2_dbg(1, debug, &video->v4l2_dev, "bcd addr(%pad) size(%d)\n",
  532. &video->bcd.dma, video->bcd.size);
  533. } else if (!bcd_buf_need && video->bcd.size) {
  534. aspeed_video_free_buf(video, &video->bcd);
  535. }
  536. spin_lock_irqsave(&video->lock, flags);
  537. buf = list_first_entry_or_null(&video->buffers,
  538. struct aspeed_video_buffer, link);
  539. if (!buf) {
  540. spin_unlock_irqrestore(&video->lock, flags);
  541. v4l2_dbg(1, debug, &video->v4l2_dev, "No buffers; don't start frame\n");
  542. return -EPROTO;
  543. }
  544. set_bit(VIDEO_FRAME_INPRG, &video->flags);
  545. addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
  546. spin_unlock_irqrestore(&video->lock, flags);
  547. aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0);
  548. aspeed_video_write(video, VE_COMP_OFFSET, 0);
  549. aspeed_video_write(video, VE_COMP_ADDR, addr);
  550. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  551. VE_INTERRUPT_COMP_COMPLETE);
  552. video->perf.last_sample = ktime_get();
  553. aspeed_video_update(video, VE_SEQ_CTRL, 0,
  554. VE_SEQ_CTRL_TRIG_CAPTURE | VE_SEQ_CTRL_TRIG_COMP);
  555. return 0;
  556. }
  557. static void aspeed_video_enable_mode_detect(struct aspeed_video *video)
  558. {
  559. /* Enable mode detect interrupts */
  560. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  561. VE_INTERRUPT_MODE_DETECT);
  562. /* Disable mode detect in order to re-trigger */
  563. aspeed_video_update(video, VE_SEQ_CTRL,
  564. VE_SEQ_CTRL_TRIG_MODE_DET, 0);
  565. /* Trigger mode detect */
  566. aspeed_video_update(video, VE_SEQ_CTRL, 0, VE_SEQ_CTRL_TRIG_MODE_DET);
  567. }
  568. static void aspeed_video_off(struct aspeed_video *video)
  569. {
  570. if (!test_bit(VIDEO_CLOCKS_ON, &video->flags))
  571. return;
  572. /* Disable interrupts */
  573. aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
  574. aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
  575. /* Turn off the relevant clocks */
  576. clk_disable(video->eclk);
  577. clk_disable(video->vclk);
  578. clear_bit(VIDEO_CLOCKS_ON, &video->flags);
  579. }
  580. static void aspeed_video_on(struct aspeed_video *video)
  581. {
  582. if (test_bit(VIDEO_CLOCKS_ON, &video->flags))
  583. return;
  584. /* Turn on the relevant clocks */
  585. clk_enable(video->vclk);
  586. clk_enable(video->eclk);
  587. set_bit(VIDEO_CLOCKS_ON, &video->flags);
  588. }
  589. static void aspeed_video_bufs_done(struct aspeed_video *video,
  590. enum vb2_buffer_state state)
  591. {
  592. unsigned long flags;
  593. struct aspeed_video_buffer *buf;
  594. spin_lock_irqsave(&video->lock, flags);
  595. list_for_each_entry(buf, &video->buffers, link)
  596. vb2_buffer_done(&buf->vb.vb2_buf, state);
  597. INIT_LIST_HEAD(&video->buffers);
  598. spin_unlock_irqrestore(&video->lock, flags);
  599. }
  600. static void aspeed_video_irq_res_change(struct aspeed_video *video, ulong delay)
  601. {
  602. v4l2_dbg(1, debug, &video->v4l2_dev, "Resolution changed; resetting\n");
  603. set_bit(VIDEO_RES_CHANGE, &video->flags);
  604. clear_bit(VIDEO_FRAME_INPRG, &video->flags);
  605. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  606. aspeed_video_off(video);
  607. aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR);
  608. schedule_delayed_work(&video->res_work, delay);
  609. }
  610. static void aspeed_video_swap_src_buf(struct aspeed_video *v)
  611. {
  612. if (v->format == VIDEO_FMT_STANDARD)
  613. return;
  614. /* Reset bcd buffer to have a full frame update every 8 frames. */
  615. if (IS_ALIGNED(v->sequence, 8))
  616. memset((u8 *)v->bcd.virt, 0x00, VE_BCD_BUFF_SIZE);
  617. if (v->sequence & 0x01) {
  618. aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[1].dma);
  619. aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[0].dma);
  620. } else {
  621. aspeed_video_write(v, VE_SRC0_ADDR, v->srcs[0].dma);
  622. aspeed_video_write(v, VE_SRC1_ADDR, v->srcs[1].dma);
  623. }
  624. }
  625. static irqreturn_t aspeed_video_irq(int irq, void *arg)
  626. {
  627. struct aspeed_video *video = arg;
  628. u32 sts = aspeed_video_read(video, VE_INTERRUPT_STATUS);
  629. /*
  630. * Hardware sometimes asserts interrupts that we haven't actually
  631. * enabled; ignore them if so.
  632. */
  633. sts &= aspeed_video_read(video, VE_INTERRUPT_CTRL);
  634. v4l2_dbg(2, debug, &video->v4l2_dev, "irq sts=%#x %s%s%s%s\n", sts,
  635. sts & VE_INTERRUPT_MODE_DETECT_WD ? ", unlock" : "",
  636. sts & VE_INTERRUPT_MODE_DETECT ? ", lock" : "",
  637. sts & VE_INTERRUPT_CAPTURE_COMPLETE ? ", capture-done" : "",
  638. sts & VE_INTERRUPT_COMP_COMPLETE ? ", comp-done" : "");
  639. /*
  640. * Resolution changed or signal was lost; reset the engine and
  641. * re-initialize
  642. */
  643. if (sts & VE_INTERRUPT_MODE_DETECT_WD) {
  644. aspeed_video_irq_res_change(video, 0);
  645. return IRQ_HANDLED;
  646. }
  647. if (sts & VE_INTERRUPT_MODE_DETECT) {
  648. if (test_bit(VIDEO_RES_DETECT, &video->flags)) {
  649. aspeed_video_update(video, VE_INTERRUPT_CTRL,
  650. VE_INTERRUPT_MODE_DETECT, 0);
  651. aspeed_video_write(video, VE_INTERRUPT_STATUS,
  652. VE_INTERRUPT_MODE_DETECT);
  653. sts &= ~VE_INTERRUPT_MODE_DETECT;
  654. set_bit(VIDEO_MODE_DETECT_DONE, &video->flags);
  655. wake_up_interruptible_all(&video->wait);
  656. } else {
  657. /*
  658. * Signal acquired while NOT doing resolution
  659. * detection; reset the engine and re-initialize
  660. */
  661. aspeed_video_irq_res_change(video,
  662. RESOLUTION_CHANGE_DELAY);
  663. return IRQ_HANDLED;
  664. }
  665. }
  666. if (sts & VE_INTERRUPT_COMP_COMPLETE) {
  667. struct aspeed_video_buffer *buf;
  668. bool empty = true;
  669. u32 frame_size = aspeed_video_read(video,
  670. video->comp_size_read);
  671. update_perf(&video->perf);
  672. spin_lock(&video->lock);
  673. clear_bit(VIDEO_FRAME_INPRG, &video->flags);
  674. buf = list_first_entry_or_null(&video->buffers,
  675. struct aspeed_video_buffer,
  676. link);
  677. if (buf) {
  678. vb2_set_plane_payload(&buf->vb.vb2_buf, 0, frame_size);
  679. /*
  680. * aspeed_jpeg requires continuous update.
  681. * On the contrary, standard jpeg can keep last buffer
  682. * to always have the latest result.
  683. */
  684. if (video->format == VIDEO_FMT_STANDARD &&
  685. list_is_last(&buf->link, &video->buffers)) {
  686. empty = false;
  687. v4l2_dbg(1, debug, &video->v4l2_dev, "skip to keep last frame updated\n");
  688. } else {
  689. buf->vb.vb2_buf.timestamp = ktime_get_ns();
  690. buf->vb.sequence = video->sequence++;
  691. buf->vb.field = V4L2_FIELD_NONE;
  692. vb2_buffer_done(&buf->vb.vb2_buf,
  693. VB2_BUF_STATE_DONE);
  694. list_del(&buf->link);
  695. empty = list_empty(&video->buffers);
  696. }
  697. }
  698. spin_unlock(&video->lock);
  699. aspeed_video_update(video, VE_SEQ_CTRL,
  700. VE_SEQ_CTRL_TRIG_CAPTURE |
  701. VE_SEQ_CTRL_FORCE_IDLE |
  702. VE_SEQ_CTRL_TRIG_COMP, 0);
  703. aspeed_video_update(video, VE_INTERRUPT_CTRL,
  704. VE_INTERRUPT_COMP_COMPLETE, 0);
  705. aspeed_video_write(video, VE_INTERRUPT_STATUS,
  706. VE_INTERRUPT_COMP_COMPLETE);
  707. sts &= ~VE_INTERRUPT_COMP_COMPLETE;
  708. aspeed_video_swap_src_buf(video);
  709. if (test_bit(VIDEO_STREAMING, &video->flags) && !empty)
  710. aspeed_video_start_frame(video);
  711. }
  712. return sts ? IRQ_NONE : IRQ_HANDLED;
  713. }
  714. static void aspeed_video_check_and_set_polarity(struct aspeed_video *video)
  715. {
  716. int i;
  717. int hsync_counter = 0;
  718. int vsync_counter = 0;
  719. u32 sts, ctrl;
  720. for (i = 0; i < NUM_POLARITY_CHECKS; ++i) {
  721. sts = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
  722. if (sts & VE_MODE_DETECT_STATUS_VSYNC)
  723. vsync_counter--;
  724. else
  725. vsync_counter++;
  726. if (sts & VE_MODE_DETECT_STATUS_HSYNC)
  727. hsync_counter--;
  728. else
  729. hsync_counter++;
  730. }
  731. ctrl = aspeed_video_read(video, VE_CTRL);
  732. if (hsync_counter < 0) {
  733. ctrl |= VE_CTRL_HSYNC_POL;
  734. video->detected_timings.polarities &=
  735. ~V4L2_DV_HSYNC_POS_POL;
  736. } else {
  737. ctrl &= ~VE_CTRL_HSYNC_POL;
  738. video->detected_timings.polarities |=
  739. V4L2_DV_HSYNC_POS_POL;
  740. }
  741. if (vsync_counter < 0) {
  742. ctrl |= VE_CTRL_VSYNC_POL;
  743. video->detected_timings.polarities &=
  744. ~V4L2_DV_VSYNC_POS_POL;
  745. } else {
  746. ctrl &= ~VE_CTRL_VSYNC_POL;
  747. video->detected_timings.polarities |=
  748. V4L2_DV_VSYNC_POS_POL;
  749. }
  750. aspeed_video_write(video, VE_CTRL, ctrl);
  751. }
  752. static bool aspeed_video_alloc_buf(struct aspeed_video *video,
  753. struct aspeed_video_addr *addr,
  754. unsigned int size)
  755. {
  756. addr->virt = dma_alloc_coherent(video->dev, size, &addr->dma,
  757. GFP_KERNEL);
  758. if (!addr->virt)
  759. return false;
  760. addr->size = size;
  761. return true;
  762. }
  763. static void aspeed_video_free_buf(struct aspeed_video *video,
  764. struct aspeed_video_addr *addr)
  765. {
  766. dma_free_coherent(video->dev, addr->size, addr->virt, addr->dma);
  767. addr->size = 0;
  768. addr->dma = 0ULL;
  769. addr->virt = NULL;
  770. }
  771. /*
  772. * Get the minimum HW-supported compression buffer size for the frame size.
  773. * Assume worst-case JPEG compression size is 1/8 raw size. This should be
  774. * plenty even for maximum quality; any worse and the engine will simply return
  775. * incomplete JPEGs.
  776. */
  777. static void aspeed_video_calc_compressed_size(struct aspeed_video *video,
  778. unsigned int frame_size)
  779. {
  780. int i, j;
  781. u32 compression_buffer_size_reg = 0;
  782. unsigned int size;
  783. const unsigned int num_compression_packets = 4;
  784. const unsigned int compression_packet_size = 1024;
  785. const unsigned int max_compressed_size = frame_size / 2; /* 4bpp / 8 */
  786. video->max_compressed_size = UINT_MAX;
  787. for (i = 0; i < 6; ++i) {
  788. for (j = 0; j < 8; ++j) {
  789. size = (num_compression_packets << i) *
  790. (compression_packet_size << j);
  791. if (size < max_compressed_size)
  792. continue;
  793. if (size < video->max_compressed_size) {
  794. compression_buffer_size_reg = (i << 3) | j;
  795. video->max_compressed_size = size;
  796. }
  797. }
  798. }
  799. aspeed_video_write(video, VE_STREAM_BUF_SIZE,
  800. compression_buffer_size_reg);
  801. v4l2_dbg(1, debug, &video->v4l2_dev, "Max compressed size: %#x\n",
  802. video->max_compressed_size);
  803. }
  804. /*
  805. * Update v4l2_bt_timings per current status.
  806. * frame_top/frame_bottom/frame_left/frame_right need to be ready.
  807. *
  808. * The following registers start counting from sync's rising edge:
  809. * 1. VR090: frame edge's left and right
  810. * 2. VR094: frame edge's top and bottom
  811. * 3. VR09C: counting from sync's rising edge to falling edge
  812. *
  813. * [Vertical timing]
  814. * +--+ +-------------------+ +--+
  815. * | | | v i d e o | | |
  816. * +--+ +-----+ +-----+ +---+
  817. * vsync+--+
  818. * frame_top+--------+
  819. * frame_bottom+----------------------------+
  820. *
  821. * +-------------------+
  822. * | v i d e o |
  823. * +--+ +-----+ +-----+ +---+
  824. * | | | |
  825. * +--+ +--+
  826. * vsync+-------------------------------+
  827. * frame_top+-----+
  828. * frame_bottom+-------------------------+
  829. *
  830. * [Horizontal timing]
  831. * +--+ +-------------------+ +--+
  832. * | | | v i d e o | | |
  833. * +--+ +-----+ +-----+ +---+
  834. * hsync+--+
  835. * frame_left+--------+
  836. * frame_right+----------------------------+
  837. *
  838. * +-------------------+
  839. * | v i d e o |
  840. * +--+ +-----+ +-----+ +---+
  841. * | | | |
  842. * +--+ +--+
  843. * hsync+-------------------------------+
  844. * frame_left+-----+
  845. * frame_right+-------------------------+
  846. *
  847. * @v: the struct of aspeed_video
  848. * @det: v4l2_bt_timings to be updated.
  849. */
  850. static void aspeed_video_get_timings(struct aspeed_video *v,
  851. struct v4l2_bt_timings *det)
  852. {
  853. u32 mds, sync, htotal, vtotal, vsync, hsync;
  854. mds = aspeed_video_read(v, VE_MODE_DETECT_STATUS);
  855. sync = aspeed_video_read(v, VE_SYNC_STATUS);
  856. htotal = aspeed_video_read(v, VE_H_TOTAL_PIXELS);
  857. vtotal = FIELD_GET(VE_MODE_DETECT_V_LINES, mds);
  858. vsync = FIELD_GET(VE_SYNC_STATUS_VSYNC, sync);
  859. hsync = FIELD_GET(VE_SYNC_STATUS_HSYNC, sync);
  860. /*
  861. * This is a workaround for polarity detection.
  862. * Because ast-soc counts sync from sync's rising edge, the reg value
  863. * of sync would be larger than video's active area if negative.
  864. */
  865. if (vsync > det->height)
  866. det->polarities &= ~V4L2_DV_VSYNC_POS_POL;
  867. else
  868. det->polarities |= V4L2_DV_VSYNC_POS_POL;
  869. if (hsync > det->width)
  870. det->polarities &= ~V4L2_DV_HSYNC_POS_POL;
  871. else
  872. det->polarities |= V4L2_DV_HSYNC_POS_POL;
  873. if (det->polarities & V4L2_DV_VSYNC_POS_POL) {
  874. det->vbackporch = v->frame_top - vsync;
  875. det->vfrontporch = vtotal - v->frame_bottom;
  876. det->vsync = vsync;
  877. } else {
  878. det->vbackporch = v->frame_top;
  879. det->vfrontporch = vsync - v->frame_bottom;
  880. det->vsync = vtotal - vsync;
  881. }
  882. if (det->polarities & V4L2_DV_HSYNC_POS_POL) {
  883. det->hbackporch = v->frame_left - hsync;
  884. det->hfrontporch = htotal - v->frame_right;
  885. det->hsync = hsync;
  886. } else {
  887. det->hbackporch = v->frame_left;
  888. det->hfrontporch = hsync - v->frame_right;
  889. det->hsync = htotal - hsync;
  890. }
  891. }
  892. #define res_check(v) test_and_clear_bit(VIDEO_MODE_DETECT_DONE, &(v)->flags)
  893. static void aspeed_video_get_resolution(struct aspeed_video *video)
  894. {
  895. bool invalid_resolution = true;
  896. int rc;
  897. int tries = 0;
  898. u32 mds;
  899. u32 src_lr_edge;
  900. u32 src_tb_edge;
  901. struct v4l2_bt_timings *det = &video->detected_timings;
  902. det->width = MIN_WIDTH;
  903. det->height = MIN_HEIGHT;
  904. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  905. memset(&video->perf, 0, sizeof(video->perf));
  906. do {
  907. if (tries) {
  908. set_current_state(TASK_INTERRUPTIBLE);
  909. if (schedule_timeout(INVALID_RESOLUTION_DELAY))
  910. return;
  911. }
  912. set_bit(VIDEO_RES_DETECT, &video->flags);
  913. aspeed_video_update(video, VE_CTRL,
  914. VE_CTRL_VSYNC_POL | VE_CTRL_HSYNC_POL, 0);
  915. aspeed_video_enable_mode_detect(video);
  916. rc = wait_event_interruptible_timeout(video->wait,
  917. res_check(video),
  918. MODE_DETECT_TIMEOUT);
  919. if (!rc) {
  920. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; first mode detect\n");
  921. clear_bit(VIDEO_RES_DETECT, &video->flags);
  922. return;
  923. }
  924. mds = aspeed_video_read(video, VE_MODE_DETECT_STATUS);
  925. // try detection again if current signal isn't stable
  926. if (!(mds & VE_MODE_DETECT_H_STABLE) ||
  927. !(mds & VE_MODE_DETECT_V_STABLE) ||
  928. (mds & VE_MODE_DETECT_EXTSRC_ADC))
  929. continue;
  930. aspeed_video_check_and_set_polarity(video);
  931. aspeed_video_enable_mode_detect(video);
  932. rc = wait_event_interruptible_timeout(video->wait,
  933. res_check(video),
  934. MODE_DETECT_TIMEOUT);
  935. clear_bit(VIDEO_RES_DETECT, &video->flags);
  936. if (!rc) {
  937. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out; second mode detect\n");
  938. return;
  939. }
  940. src_lr_edge = aspeed_video_read(video, VE_SRC_LR_EDGE_DET);
  941. src_tb_edge = aspeed_video_read(video, VE_SRC_TB_EDGE_DET);
  942. video->frame_bottom = FIELD_GET(VE_SRC_TB_EDGE_DET_BOT, src_tb_edge);
  943. video->frame_top = FIELD_GET(VE_SRC_TB_EDGE_DET_TOP, src_tb_edge);
  944. if (video->frame_top > video->frame_bottom)
  945. continue;
  946. video->frame_right = FIELD_GET(VE_SRC_LR_EDGE_DET_RT, src_lr_edge);
  947. video->frame_left = FIELD_GET(VE_SRC_LR_EDGE_DET_LEFT, src_lr_edge);
  948. if (video->frame_left > video->frame_right)
  949. continue;
  950. invalid_resolution = false;
  951. } while (invalid_resolution && (tries++ < INVALID_RESOLUTION_RETRIES));
  952. if (invalid_resolution) {
  953. v4l2_dbg(1, debug, &video->v4l2_dev, "Invalid resolution detected\n");
  954. return;
  955. }
  956. det->height = (video->frame_bottom - video->frame_top) + 1;
  957. det->width = (video->frame_right - video->frame_left) + 1;
  958. video->v4l2_input_status = 0;
  959. aspeed_video_get_timings(video, det);
  960. /*
  961. * Enable mode-detect watchdog, resolution-change watchdog and
  962. * automatic compression after frame capture.
  963. */
  964. aspeed_video_update(video, VE_INTERRUPT_CTRL, 0,
  965. VE_INTERRUPT_MODE_DETECT_WD);
  966. aspeed_video_update(video, VE_SEQ_CTRL, 0,
  967. VE_SEQ_CTRL_AUTO_COMP | VE_SEQ_CTRL_EN_WATCHDOG);
  968. v4l2_dbg(1, debug, &video->v4l2_dev, "Got resolution: %dx%d\n",
  969. det->width, det->height);
  970. }
  971. static void aspeed_video_set_resolution(struct aspeed_video *video)
  972. {
  973. struct v4l2_bt_timings *act = &video->active_timings;
  974. unsigned int size = act->width * ALIGN(act->height, 8);
  975. /* Set capture/compression frame sizes */
  976. aspeed_video_calc_compressed_size(video, size);
  977. if (!IS_ALIGNED(act->width, 64)) {
  978. /*
  979. * This is a workaround to fix a AST2500 silicon bug on A1 and
  980. * A2 revisions. Since it doesn't break capturing operation of
  981. * other revisions, use it for all revisions without checking
  982. * the revision ID. It picked new width which is a very next
  983. * 64-pixels aligned value to minimize memory bandwidth
  984. * and to get better access speed from video engine.
  985. */
  986. u32 width = ALIGN(act->width, 64);
  987. aspeed_video_write(video, VE_CAP_WINDOW, width << 16 | act->height);
  988. size = width * ALIGN(act->height, 8);
  989. } else {
  990. aspeed_video_write(video, VE_CAP_WINDOW,
  991. act->width << 16 | act->height);
  992. }
  993. aspeed_video_write(video, VE_COMP_WINDOW,
  994. act->width << 16 | act->height);
  995. aspeed_video_write(video, VE_SRC_SCANLINE_OFFSET, act->width * 4);
  996. /* Don't use direct mode below 1024 x 768 (irqs don't fire) */
  997. if (size < DIRECT_FETCH_THRESHOLD) {
  998. v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Sync Mode\n");
  999. aspeed_video_write(video, VE_TGS_0,
  1000. FIELD_PREP(VE_TGS_FIRST,
  1001. video->frame_left - 1) |
  1002. FIELD_PREP(VE_TGS_LAST,
  1003. video->frame_right));
  1004. aspeed_video_write(video, VE_TGS_1,
  1005. FIELD_PREP(VE_TGS_FIRST, video->frame_top) |
  1006. FIELD_PREP(VE_TGS_LAST,
  1007. video->frame_bottom + 1));
  1008. aspeed_video_update(video, VE_CTRL,
  1009. VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH,
  1010. VE_CTRL_INT_DE);
  1011. } else {
  1012. v4l2_dbg(1, debug, &video->v4l2_dev, "Capture: Direct Mode\n");
  1013. aspeed_video_update(video, VE_CTRL,
  1014. VE_CTRL_INT_DE | VE_CTRL_DIRECT_FETCH,
  1015. VE_CTRL_DIRECT_FETCH);
  1016. }
  1017. size *= 4;
  1018. if (size != video->srcs[0].size) {
  1019. if (video->srcs[0].size)
  1020. aspeed_video_free_buf(video, &video->srcs[0]);
  1021. if (video->srcs[1].size)
  1022. aspeed_video_free_buf(video, &video->srcs[1]);
  1023. if (!aspeed_video_alloc_buf(video, &video->srcs[0], size))
  1024. goto err_mem;
  1025. if (!aspeed_video_alloc_buf(video, &video->srcs[1], size))
  1026. goto err_mem;
  1027. v4l2_dbg(1, debug, &video->v4l2_dev, "src buf0 addr(%pad) size(%d)\n",
  1028. &video->srcs[0].dma, video->srcs[0].size);
  1029. v4l2_dbg(1, debug, &video->v4l2_dev, "src buf1 addr(%pad) size(%d)\n",
  1030. &video->srcs[1].dma, video->srcs[1].size);
  1031. aspeed_video_write(video, VE_SRC0_ADDR, video->srcs[0].dma);
  1032. aspeed_video_write(video, VE_SRC1_ADDR, video->srcs[1].dma);
  1033. }
  1034. return;
  1035. err_mem:
  1036. dev_err(video->dev, "Failed to allocate source buffers\n");
  1037. if (video->srcs[0].size)
  1038. aspeed_video_free_buf(video, &video->srcs[0]);
  1039. }
  1040. static void aspeed_video_update_regs(struct aspeed_video *video)
  1041. {
  1042. u8 jpeg_hq_quality = clamp((int)video->jpeg_hq_quality - 1, 0,
  1043. ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1);
  1044. u32 comp_ctrl = FIELD_PREP(VE_COMP_CTRL_DCT_LUM, video->jpeg_quality) |
  1045. FIELD_PREP(VE_COMP_CTRL_DCT_CHR, video->jpeg_quality | 0x10) |
  1046. FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode) |
  1047. FIELD_PREP(VE_COMP_CTRL_HQ_DCT_LUM, jpeg_hq_quality) |
  1048. FIELD_PREP(VE_COMP_CTRL_HQ_DCT_CHR, jpeg_hq_quality | 0x10);
  1049. u32 ctrl = 0;
  1050. u32 seq_ctrl = 0;
  1051. v4l2_dbg(1, debug, &video->v4l2_dev, "framerate(%d)\n",
  1052. video->frame_rate);
  1053. v4l2_dbg(1, debug, &video->v4l2_dev, "jpeg format(%s) subsample(%s)\n",
  1054. format_str[video->format],
  1055. video->yuv420 ? "420" : "444");
  1056. v4l2_dbg(1, debug, &video->v4l2_dev, "compression quality(%d)\n",
  1057. video->jpeg_quality);
  1058. v4l2_dbg(1, debug, &video->v4l2_dev, "hq_mode(%s) hq_quality(%d)\n",
  1059. video->hq_mode ? "on" : "off", video->jpeg_hq_quality);
  1060. if (video->format == VIDEO_FMT_ASPEED)
  1061. aspeed_video_update(video, VE_BCD_CTRL, 0, VE_BCD_CTRL_EN_BCD);
  1062. else
  1063. aspeed_video_update(video, VE_BCD_CTRL, VE_BCD_CTRL_EN_BCD, 0);
  1064. if (video->frame_rate)
  1065. ctrl |= FIELD_PREP(VE_CTRL_FRC, video->frame_rate);
  1066. if (video->format == VIDEO_FMT_STANDARD) {
  1067. comp_ctrl &= ~FIELD_PREP(VE_COMP_CTRL_EN_HQ, video->hq_mode);
  1068. seq_ctrl |= video->jpeg_mode;
  1069. }
  1070. if (video->yuv420)
  1071. seq_ctrl |= VE_SEQ_CTRL_YUV420;
  1072. if (video->jpeg.virt)
  1073. aspeed_video_update_jpeg_table(video->jpeg.virt, video->yuv420);
  1074. /* Set control registers */
  1075. aspeed_video_update(video, VE_SEQ_CTRL,
  1076. video->jpeg_mode | VE_SEQ_CTRL_YUV420,
  1077. seq_ctrl);
  1078. aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC, ctrl);
  1079. aspeed_video_update(video, VE_COMP_CTRL,
  1080. VE_COMP_CTRL_DCT_LUM | VE_COMP_CTRL_DCT_CHR |
  1081. VE_COMP_CTRL_EN_HQ | VE_COMP_CTRL_HQ_DCT_LUM |
  1082. VE_COMP_CTRL_HQ_DCT_CHR | VE_COMP_CTRL_VQ_4COLOR |
  1083. VE_COMP_CTRL_VQ_DCT_ONLY,
  1084. comp_ctrl);
  1085. }
  1086. static void aspeed_video_init_regs(struct aspeed_video *video)
  1087. {
  1088. u32 ctrl = VE_CTRL_AUTO_OR_CURSOR |
  1089. FIELD_PREP(VE_CTRL_CAPTURE_FMT, VIDEO_CAP_FMT_YUV_FULL_SWING);
  1090. /* Unlock VE registers */
  1091. aspeed_video_write(video, VE_PROTECTION_KEY, VE_PROTECTION_KEY_UNLOCK);
  1092. /* Disable interrupts */
  1093. aspeed_video_write(video, VE_INTERRUPT_CTRL, 0);
  1094. aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
  1095. /* Clear the offset */
  1096. aspeed_video_write(video, VE_COMP_PROC_OFFSET, 0);
  1097. aspeed_video_write(video, VE_COMP_OFFSET, 0);
  1098. aspeed_video_write(video, VE_JPEG_ADDR, video->jpeg.dma);
  1099. /* Set control registers */
  1100. aspeed_video_write(video, VE_CTRL, ctrl);
  1101. aspeed_video_write(video, VE_COMP_CTRL, VE_COMP_CTRL_RSVD);
  1102. /* Don't downscale */
  1103. aspeed_video_write(video, VE_SCALING_FACTOR, 0x10001000);
  1104. aspeed_video_write(video, VE_SCALING_FILTER0, 0x00200000);
  1105. aspeed_video_write(video, VE_SCALING_FILTER1, 0x00200000);
  1106. aspeed_video_write(video, VE_SCALING_FILTER2, 0x00200000);
  1107. aspeed_video_write(video, VE_SCALING_FILTER3, 0x00200000);
  1108. /* Set mode detection defaults */
  1109. aspeed_video_write(video, VE_MODE_DETECT,
  1110. FIELD_PREP(VE_MODE_DT_HOR_TOLER, 2) |
  1111. FIELD_PREP(VE_MODE_DT_VER_TOLER, 2) |
  1112. FIELD_PREP(VE_MODE_DT_HOR_STABLE, 6) |
  1113. FIELD_PREP(VE_MODE_DT_VER_STABLE, 6) |
  1114. FIELD_PREP(VE_MODE_DT_EDG_THROD, 0x65));
  1115. aspeed_video_write(video, VE_BCD_CTRL, 0);
  1116. }
  1117. static void aspeed_video_start(struct aspeed_video *video)
  1118. {
  1119. aspeed_video_on(video);
  1120. aspeed_video_init_regs(video);
  1121. /* Resolution set to 640x480 if no signal found */
  1122. aspeed_video_get_resolution(video);
  1123. /* Set timings since the device is being opened for the first time */
  1124. video->active_timings = video->detected_timings;
  1125. aspeed_video_set_resolution(video);
  1126. video->pix_fmt.width = video->active_timings.width;
  1127. video->pix_fmt.height = video->active_timings.height;
  1128. video->pix_fmt.sizeimage = video->max_compressed_size;
  1129. }
  1130. static void aspeed_video_stop(struct aspeed_video *video)
  1131. {
  1132. set_bit(VIDEO_STOPPED, &video->flags);
  1133. cancel_delayed_work_sync(&video->res_work);
  1134. aspeed_video_off(video);
  1135. if (video->srcs[0].size)
  1136. aspeed_video_free_buf(video, &video->srcs[0]);
  1137. if (video->srcs[1].size)
  1138. aspeed_video_free_buf(video, &video->srcs[1]);
  1139. if (video->bcd.size)
  1140. aspeed_video_free_buf(video, &video->bcd);
  1141. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  1142. video->flags = 0;
  1143. }
  1144. static int aspeed_video_querycap(struct file *file, void *fh,
  1145. struct v4l2_capability *cap)
  1146. {
  1147. strscpy(cap->driver, DEVICE_NAME, sizeof(cap->driver));
  1148. strscpy(cap->card, "Aspeed Video Engine", sizeof(cap->card));
  1149. snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
  1150. DEVICE_NAME);
  1151. return 0;
  1152. }
  1153. static int aspeed_video_enum_format(struct file *file, void *fh,
  1154. struct v4l2_fmtdesc *f)
  1155. {
  1156. struct aspeed_video *video = video_drvdata(file);
  1157. if (f->index)
  1158. return -EINVAL;
  1159. f->pixelformat = video->pix_fmt.pixelformat;
  1160. return 0;
  1161. }
  1162. static int aspeed_video_get_format(struct file *file, void *fh,
  1163. struct v4l2_format *f)
  1164. {
  1165. struct aspeed_video *video = video_drvdata(file);
  1166. f->fmt.pix = video->pix_fmt;
  1167. return 0;
  1168. }
  1169. static int aspeed_video_set_format(struct file *file, void *fh,
  1170. struct v4l2_format *f)
  1171. {
  1172. struct aspeed_video *video = video_drvdata(file);
  1173. if (vb2_is_busy(&video->queue))
  1174. return -EBUSY;
  1175. switch (f->fmt.pix.pixelformat) {
  1176. case V4L2_PIX_FMT_JPEG:
  1177. video->format = VIDEO_FMT_STANDARD;
  1178. break;
  1179. case V4L2_PIX_FMT_AJPG:
  1180. video->format = VIDEO_FMT_ASPEED;
  1181. break;
  1182. default:
  1183. return -EINVAL;
  1184. }
  1185. video->pix_fmt.pixelformat = f->fmt.pix.pixelformat;
  1186. return 0;
  1187. }
  1188. static int aspeed_video_enum_input(struct file *file, void *fh,
  1189. struct v4l2_input *inp)
  1190. {
  1191. struct aspeed_video *video = video_drvdata(file);
  1192. if (inp->index)
  1193. return -EINVAL;
  1194. strscpy(inp->name, "Host VGA capture", sizeof(inp->name));
  1195. inp->type = V4L2_INPUT_TYPE_CAMERA;
  1196. inp->capabilities = V4L2_IN_CAP_DV_TIMINGS;
  1197. inp->status = video->v4l2_input_status;
  1198. return 0;
  1199. }
  1200. static int aspeed_video_get_input(struct file *file, void *fh, unsigned int *i)
  1201. {
  1202. *i = 0;
  1203. return 0;
  1204. }
  1205. static int aspeed_video_set_input(struct file *file, void *fh, unsigned int i)
  1206. {
  1207. if (i)
  1208. return -EINVAL;
  1209. return 0;
  1210. }
  1211. static int aspeed_video_get_parm(struct file *file, void *fh,
  1212. struct v4l2_streamparm *a)
  1213. {
  1214. struct aspeed_video *video = video_drvdata(file);
  1215. a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  1216. a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1217. a->parm.capture.timeperframe.numerator = 1;
  1218. if (!video->frame_rate)
  1219. a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
  1220. else
  1221. a->parm.capture.timeperframe.denominator = video->frame_rate;
  1222. return 0;
  1223. }
  1224. static int aspeed_video_set_parm(struct file *file, void *fh,
  1225. struct v4l2_streamparm *a)
  1226. {
  1227. unsigned int frame_rate = 0;
  1228. struct aspeed_video *video = video_drvdata(file);
  1229. a->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
  1230. a->parm.capture.readbuffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1231. if (a->parm.capture.timeperframe.numerator)
  1232. frame_rate = a->parm.capture.timeperframe.denominator /
  1233. a->parm.capture.timeperframe.numerator;
  1234. if (!frame_rate || frame_rate > MAX_FRAME_RATE) {
  1235. frame_rate = 0;
  1236. a->parm.capture.timeperframe.denominator = MAX_FRAME_RATE;
  1237. a->parm.capture.timeperframe.numerator = 1;
  1238. }
  1239. if (video->frame_rate != frame_rate) {
  1240. video->frame_rate = frame_rate;
  1241. aspeed_video_update(video, VE_CTRL, VE_CTRL_FRC,
  1242. FIELD_PREP(VE_CTRL_FRC, frame_rate));
  1243. }
  1244. return 0;
  1245. }
  1246. static int aspeed_video_enum_framesizes(struct file *file, void *fh,
  1247. struct v4l2_frmsizeenum *fsize)
  1248. {
  1249. struct aspeed_video *video = video_drvdata(file);
  1250. if (fsize->index)
  1251. return -EINVAL;
  1252. if (fsize->pixel_format != V4L2_PIX_FMT_JPEG)
  1253. return -EINVAL;
  1254. fsize->discrete.width = video->pix_fmt.width;
  1255. fsize->discrete.height = video->pix_fmt.height;
  1256. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  1257. return 0;
  1258. }
  1259. static int aspeed_video_enum_frameintervals(struct file *file, void *fh,
  1260. struct v4l2_frmivalenum *fival)
  1261. {
  1262. struct aspeed_video *video = video_drvdata(file);
  1263. if (fival->index)
  1264. return -EINVAL;
  1265. if (fival->width != video->detected_timings.width ||
  1266. fival->height != video->detected_timings.height)
  1267. return -EINVAL;
  1268. if (fival->pixel_format != V4L2_PIX_FMT_JPEG)
  1269. return -EINVAL;
  1270. fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
  1271. fival->stepwise.min.denominator = MAX_FRAME_RATE;
  1272. fival->stepwise.min.numerator = 1;
  1273. fival->stepwise.max.denominator = 1;
  1274. fival->stepwise.max.numerator = 1;
  1275. fival->stepwise.step = fival->stepwise.max;
  1276. return 0;
  1277. }
  1278. static int aspeed_video_set_dv_timings(struct file *file, void *fh,
  1279. struct v4l2_dv_timings *timings)
  1280. {
  1281. struct aspeed_video *video = video_drvdata(file);
  1282. if (timings->bt.width == video->active_timings.width &&
  1283. timings->bt.height == video->active_timings.height)
  1284. return 0;
  1285. if (vb2_is_busy(&video->queue))
  1286. return -EBUSY;
  1287. video->active_timings = timings->bt;
  1288. aspeed_video_set_resolution(video);
  1289. video->pix_fmt.width = timings->bt.width;
  1290. video->pix_fmt.height = timings->bt.height;
  1291. video->pix_fmt.sizeimage = video->max_compressed_size;
  1292. timings->type = V4L2_DV_BT_656_1120;
  1293. v4l2_dbg(1, debug, &video->v4l2_dev, "set new timings(%dx%d)\n",
  1294. timings->bt.width, timings->bt.height);
  1295. return 0;
  1296. }
  1297. static int aspeed_video_get_dv_timings(struct file *file, void *fh,
  1298. struct v4l2_dv_timings *timings)
  1299. {
  1300. struct aspeed_video *video = video_drvdata(file);
  1301. timings->type = V4L2_DV_BT_656_1120;
  1302. timings->bt = video->active_timings;
  1303. return 0;
  1304. }
  1305. static int aspeed_video_query_dv_timings(struct file *file, void *fh,
  1306. struct v4l2_dv_timings *timings)
  1307. {
  1308. int rc;
  1309. struct aspeed_video *video = video_drvdata(file);
  1310. /*
  1311. * This blocks only if the driver is currently in the process of
  1312. * detecting a new resolution; in the event of no signal or timeout
  1313. * this function is woken up.
  1314. */
  1315. if (file->f_flags & O_NONBLOCK) {
  1316. if (test_bit(VIDEO_RES_CHANGE, &video->flags))
  1317. return -EAGAIN;
  1318. } else {
  1319. rc = wait_event_interruptible(video->wait,
  1320. !test_bit(VIDEO_RES_CHANGE,
  1321. &video->flags));
  1322. if (rc)
  1323. return -EINTR;
  1324. }
  1325. timings->type = V4L2_DV_BT_656_1120;
  1326. timings->bt = video->detected_timings;
  1327. return video->v4l2_input_status ? -ENOLINK : 0;
  1328. }
  1329. static int aspeed_video_enum_dv_timings(struct file *file, void *fh,
  1330. struct v4l2_enum_dv_timings *timings)
  1331. {
  1332. return v4l2_enum_dv_timings_cap(timings, &aspeed_video_timings_cap,
  1333. NULL, NULL);
  1334. }
  1335. static int aspeed_video_dv_timings_cap(struct file *file, void *fh,
  1336. struct v4l2_dv_timings_cap *cap)
  1337. {
  1338. *cap = aspeed_video_timings_cap;
  1339. return 0;
  1340. }
  1341. static int aspeed_video_sub_event(struct v4l2_fh *fh,
  1342. const struct v4l2_event_subscription *sub)
  1343. {
  1344. switch (sub->type) {
  1345. case V4L2_EVENT_SOURCE_CHANGE:
  1346. return v4l2_src_change_event_subscribe(fh, sub);
  1347. }
  1348. return v4l2_ctrl_subscribe_event(fh, sub);
  1349. }
  1350. static const struct v4l2_ioctl_ops aspeed_video_ioctl_ops = {
  1351. .vidioc_querycap = aspeed_video_querycap,
  1352. .vidioc_enum_fmt_vid_cap = aspeed_video_enum_format,
  1353. .vidioc_g_fmt_vid_cap = aspeed_video_get_format,
  1354. .vidioc_s_fmt_vid_cap = aspeed_video_set_format,
  1355. .vidioc_try_fmt_vid_cap = aspeed_video_get_format,
  1356. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  1357. .vidioc_querybuf = vb2_ioctl_querybuf,
  1358. .vidioc_qbuf = vb2_ioctl_qbuf,
  1359. .vidioc_expbuf = vb2_ioctl_expbuf,
  1360. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  1361. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  1362. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  1363. .vidioc_streamon = vb2_ioctl_streamon,
  1364. .vidioc_streamoff = vb2_ioctl_streamoff,
  1365. .vidioc_enum_input = aspeed_video_enum_input,
  1366. .vidioc_g_input = aspeed_video_get_input,
  1367. .vidioc_s_input = aspeed_video_set_input,
  1368. .vidioc_g_parm = aspeed_video_get_parm,
  1369. .vidioc_s_parm = aspeed_video_set_parm,
  1370. .vidioc_enum_framesizes = aspeed_video_enum_framesizes,
  1371. .vidioc_enum_frameintervals = aspeed_video_enum_frameintervals,
  1372. .vidioc_s_dv_timings = aspeed_video_set_dv_timings,
  1373. .vidioc_g_dv_timings = aspeed_video_get_dv_timings,
  1374. .vidioc_query_dv_timings = aspeed_video_query_dv_timings,
  1375. .vidioc_enum_dv_timings = aspeed_video_enum_dv_timings,
  1376. .vidioc_dv_timings_cap = aspeed_video_dv_timings_cap,
  1377. .vidioc_subscribe_event = aspeed_video_sub_event,
  1378. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  1379. };
  1380. static int aspeed_video_set_ctrl(struct v4l2_ctrl *ctrl)
  1381. {
  1382. struct aspeed_video *video = container_of(ctrl->handler,
  1383. struct aspeed_video,
  1384. ctrl_handler);
  1385. switch (ctrl->id) {
  1386. case V4L2_CID_JPEG_COMPRESSION_QUALITY:
  1387. video->jpeg_quality = ctrl->val;
  1388. if (test_bit(VIDEO_STREAMING, &video->flags))
  1389. aspeed_video_update_regs(video);
  1390. break;
  1391. case V4L2_CID_JPEG_CHROMA_SUBSAMPLING:
  1392. video->yuv420 = (ctrl->val == V4L2_JPEG_CHROMA_SUBSAMPLING_420);
  1393. if (test_bit(VIDEO_STREAMING, &video->flags))
  1394. aspeed_video_update_regs(video);
  1395. break;
  1396. case V4L2_CID_ASPEED_HQ_MODE:
  1397. video->hq_mode = ctrl->val;
  1398. if (test_bit(VIDEO_STREAMING, &video->flags))
  1399. aspeed_video_update_regs(video);
  1400. break;
  1401. case V4L2_CID_ASPEED_HQ_JPEG_QUALITY:
  1402. video->jpeg_hq_quality = ctrl->val;
  1403. if (test_bit(VIDEO_STREAMING, &video->flags))
  1404. aspeed_video_update_regs(video);
  1405. break;
  1406. default:
  1407. return -EINVAL;
  1408. }
  1409. return 0;
  1410. }
  1411. static const struct v4l2_ctrl_ops aspeed_video_ctrl_ops = {
  1412. .s_ctrl = aspeed_video_set_ctrl,
  1413. };
  1414. static const struct v4l2_ctrl_config aspeed_ctrl_HQ_mode = {
  1415. .ops = &aspeed_video_ctrl_ops,
  1416. .id = V4L2_CID_ASPEED_HQ_MODE,
  1417. .name = "Aspeed HQ Mode",
  1418. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1419. .min = false,
  1420. .max = true,
  1421. .step = 1,
  1422. .def = false,
  1423. };
  1424. static const struct v4l2_ctrl_config aspeed_ctrl_HQ_jpeg_quality = {
  1425. .ops = &aspeed_video_ctrl_ops,
  1426. .id = V4L2_CID_ASPEED_HQ_JPEG_QUALITY,
  1427. .name = "Aspeed HQ Quality",
  1428. .type = V4L2_CTRL_TYPE_INTEGER,
  1429. .min = 1,
  1430. .max = ASPEED_VIDEO_JPEG_NUM_QUALITIES,
  1431. .step = 1,
  1432. .def = 1,
  1433. };
  1434. static void aspeed_video_resolution_work(struct work_struct *work)
  1435. {
  1436. struct delayed_work *dwork = to_delayed_work(work);
  1437. struct aspeed_video *video = container_of(dwork, struct aspeed_video,
  1438. res_work);
  1439. aspeed_video_on(video);
  1440. /* Exit early in case no clients remain */
  1441. if (test_bit(VIDEO_STOPPED, &video->flags))
  1442. goto done;
  1443. aspeed_video_init_regs(video);
  1444. aspeed_video_update_regs(video);
  1445. aspeed_video_get_resolution(video);
  1446. if (video->detected_timings.width != video->active_timings.width ||
  1447. video->detected_timings.height != video->active_timings.height) {
  1448. static const struct v4l2_event ev = {
  1449. .type = V4L2_EVENT_SOURCE_CHANGE,
  1450. .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
  1451. };
  1452. v4l2_dbg(1, debug, &video->v4l2_dev, "fire source change event\n");
  1453. v4l2_event_queue(&video->vdev, &ev);
  1454. } else if (test_bit(VIDEO_STREAMING, &video->flags)) {
  1455. /* No resolution change so just restart streaming */
  1456. aspeed_video_start_frame(video);
  1457. }
  1458. done:
  1459. clear_bit(VIDEO_RES_CHANGE, &video->flags);
  1460. wake_up_interruptible_all(&video->wait);
  1461. }
  1462. static int aspeed_video_open(struct file *file)
  1463. {
  1464. int rc;
  1465. struct aspeed_video *video = video_drvdata(file);
  1466. mutex_lock(&video->video_lock);
  1467. rc = v4l2_fh_open(file);
  1468. if (rc) {
  1469. mutex_unlock(&video->video_lock);
  1470. return rc;
  1471. }
  1472. if (v4l2_fh_is_singular_file(file))
  1473. aspeed_video_start(video);
  1474. mutex_unlock(&video->video_lock);
  1475. return 0;
  1476. }
  1477. static int aspeed_video_release(struct file *file)
  1478. {
  1479. int rc;
  1480. struct aspeed_video *video = video_drvdata(file);
  1481. mutex_lock(&video->video_lock);
  1482. if (v4l2_fh_is_singular_file(file))
  1483. aspeed_video_stop(video);
  1484. rc = _vb2_fop_release(file, NULL);
  1485. mutex_unlock(&video->video_lock);
  1486. return rc;
  1487. }
  1488. static const struct v4l2_file_operations aspeed_video_v4l2_fops = {
  1489. .owner = THIS_MODULE,
  1490. .read = vb2_fop_read,
  1491. .poll = vb2_fop_poll,
  1492. .unlocked_ioctl = video_ioctl2,
  1493. .mmap = vb2_fop_mmap,
  1494. .open = aspeed_video_open,
  1495. .release = aspeed_video_release,
  1496. };
  1497. static int aspeed_video_queue_setup(struct vb2_queue *q,
  1498. unsigned int *num_buffers,
  1499. unsigned int *num_planes,
  1500. unsigned int sizes[],
  1501. struct device *alloc_devs[])
  1502. {
  1503. struct aspeed_video *video = vb2_get_drv_priv(q);
  1504. if (*num_planes) {
  1505. if (sizes[0] < video->max_compressed_size)
  1506. return -EINVAL;
  1507. return 0;
  1508. }
  1509. *num_planes = 1;
  1510. sizes[0] = video->max_compressed_size;
  1511. return 0;
  1512. }
  1513. static int aspeed_video_buf_prepare(struct vb2_buffer *vb)
  1514. {
  1515. struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue);
  1516. if (vb2_plane_size(vb, 0) < video->max_compressed_size)
  1517. return -EINVAL;
  1518. return 0;
  1519. }
  1520. static int aspeed_video_start_streaming(struct vb2_queue *q,
  1521. unsigned int count)
  1522. {
  1523. int rc;
  1524. struct aspeed_video *video = vb2_get_drv_priv(q);
  1525. video->sequence = 0;
  1526. video->perf.duration_max = 0;
  1527. video->perf.duration_min = 0xffffffff;
  1528. aspeed_video_update_regs(video);
  1529. rc = aspeed_video_start_frame(video);
  1530. if (rc) {
  1531. aspeed_video_bufs_done(video, VB2_BUF_STATE_QUEUED);
  1532. return rc;
  1533. }
  1534. set_bit(VIDEO_STREAMING, &video->flags);
  1535. return 0;
  1536. }
  1537. static void aspeed_video_stop_streaming(struct vb2_queue *q)
  1538. {
  1539. int rc;
  1540. struct aspeed_video *video = vb2_get_drv_priv(q);
  1541. clear_bit(VIDEO_STREAMING, &video->flags);
  1542. rc = wait_event_timeout(video->wait,
  1543. !test_bit(VIDEO_FRAME_INPRG, &video->flags),
  1544. STOP_TIMEOUT);
  1545. if (!rc) {
  1546. v4l2_dbg(1, debug, &video->v4l2_dev, "Timed out when stopping streaming\n");
  1547. /*
  1548. * Need to force stop any DMA and try and get HW into a good
  1549. * state for future calls to start streaming again.
  1550. */
  1551. aspeed_video_off(video);
  1552. aspeed_video_on(video);
  1553. aspeed_video_init_regs(video);
  1554. aspeed_video_get_resolution(video);
  1555. }
  1556. aspeed_video_bufs_done(video, VB2_BUF_STATE_ERROR);
  1557. }
  1558. static void aspeed_video_buf_queue(struct vb2_buffer *vb)
  1559. {
  1560. bool empty;
  1561. struct aspeed_video *video = vb2_get_drv_priv(vb->vb2_queue);
  1562. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  1563. struct aspeed_video_buffer *avb = to_aspeed_video_buffer(vbuf);
  1564. unsigned long flags;
  1565. spin_lock_irqsave(&video->lock, flags);
  1566. empty = list_empty(&video->buffers);
  1567. list_add_tail(&avb->link, &video->buffers);
  1568. spin_unlock_irqrestore(&video->lock, flags);
  1569. if (test_bit(VIDEO_STREAMING, &video->flags) &&
  1570. !test_bit(VIDEO_FRAME_INPRG, &video->flags) && empty)
  1571. aspeed_video_start_frame(video);
  1572. }
  1573. static const struct vb2_ops aspeed_video_vb2_ops = {
  1574. .queue_setup = aspeed_video_queue_setup,
  1575. .wait_prepare = vb2_ops_wait_prepare,
  1576. .wait_finish = vb2_ops_wait_finish,
  1577. .buf_prepare = aspeed_video_buf_prepare,
  1578. .start_streaming = aspeed_video_start_streaming,
  1579. .stop_streaming = aspeed_video_stop_streaming,
  1580. .buf_queue = aspeed_video_buf_queue,
  1581. };
  1582. #ifdef CONFIG_DEBUG_FS
  1583. static int aspeed_video_debugfs_show(struct seq_file *s, void *data)
  1584. {
  1585. struct aspeed_video *v = s->private;
  1586. u32 val08;
  1587. seq_puts(s, "\n");
  1588. seq_puts(s, "Capture:\n");
  1589. val08 = aspeed_video_read(v, VE_CTRL);
  1590. if (FIELD_GET(VE_CTRL_DIRECT_FETCH, val08)) {
  1591. seq_printf(s, " %-20s:\tDirect fetch\n", "Mode");
  1592. seq_printf(s, " %-20s:\t%s\n", "VGA bpp mode",
  1593. FIELD_GET(VE_CTRL_INT_DE, val08) ? "16" : "32");
  1594. } else {
  1595. seq_printf(s, " %-20s:\tSync\n", "Mode");
  1596. seq_printf(s, " %-20s:\t%s\n", "Video source",
  1597. FIELD_GET(VE_CTRL_SOURCE, val08) ?
  1598. "external" : "internal");
  1599. seq_printf(s, " %-20s:\t%s\n", "DE source",
  1600. FIELD_GET(VE_CTRL_INT_DE, val08) ?
  1601. "internal" : "external");
  1602. seq_printf(s, " %-20s:\t%s\n", "Cursor overlay",
  1603. FIELD_GET(VE_CTRL_AUTO_OR_CURSOR, val08) ?
  1604. "Without" : "With");
  1605. }
  1606. seq_printf(s, " %-20s:\t%s\n", "Signal",
  1607. v->v4l2_input_status ? "Unlock" : "Lock");
  1608. seq_printf(s, " %-20s:\t%d\n", "Width", v->pix_fmt.width);
  1609. seq_printf(s, " %-20s:\t%d\n", "Height", v->pix_fmt.height);
  1610. seq_printf(s, " %-20s:\t%d\n", "FRC", v->frame_rate);
  1611. seq_puts(s, "\n");
  1612. seq_puts(s, "Compression:\n");
  1613. seq_printf(s, " %-20s:\t%s\n", "Format", format_str[v->format]);
  1614. seq_printf(s, " %-20s:\t%s\n", "Subsampling",
  1615. v->yuv420 ? "420" : "444");
  1616. seq_printf(s, " %-20s:\t%d\n", "Quality", v->jpeg_quality);
  1617. if (v->format == VIDEO_FMT_ASPEED) {
  1618. seq_printf(s, " %-20s:\t%s\n", "HQ Mode",
  1619. v->hq_mode ? "on" : "off");
  1620. seq_printf(s, " %-20s:\t%d\n", "HQ Quality",
  1621. v->hq_mode ? v->jpeg_hq_quality : 0);
  1622. }
  1623. seq_puts(s, "\n");
  1624. seq_puts(s, "Performance:\n");
  1625. seq_printf(s, " %-20s:\t%d\n", "Frame#", v->sequence);
  1626. seq_printf(s, " %-20s:\n", "Frame Duration(ms)");
  1627. seq_printf(s, " %-18s:\t%d\n", "Now", v->perf.duration);
  1628. seq_printf(s, " %-18s:\t%d\n", "Min", v->perf.duration_min);
  1629. seq_printf(s, " %-18s:\t%d\n", "Max", v->perf.duration_max);
  1630. seq_printf(s, " %-20s:\t%d\n", "FPS",
  1631. (v->perf.totaltime && v->sequence) ?
  1632. 1000 / (v->perf.totaltime / v->sequence) : 0);
  1633. return 0;
  1634. }
  1635. DEFINE_SHOW_ATTRIBUTE(aspeed_video_debugfs);
  1636. static struct dentry *debugfs_entry;
  1637. static void aspeed_video_debugfs_remove(struct aspeed_video *video)
  1638. {
  1639. debugfs_remove_recursive(debugfs_entry);
  1640. debugfs_entry = NULL;
  1641. }
  1642. static void aspeed_video_debugfs_create(struct aspeed_video *video)
  1643. {
  1644. debugfs_entry = debugfs_create_file(DEVICE_NAME, 0444, NULL,
  1645. video,
  1646. &aspeed_video_debugfs_fops);
  1647. }
  1648. #else
  1649. static void aspeed_video_debugfs_remove(struct aspeed_video *video) { }
  1650. static void aspeed_video_debugfs_create(struct aspeed_video *video) { }
  1651. #endif /* CONFIG_DEBUG_FS */
  1652. static int aspeed_video_setup_video(struct aspeed_video *video)
  1653. {
  1654. const u64 mask = ~(BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_444) |
  1655. BIT(V4L2_JPEG_CHROMA_SUBSAMPLING_420));
  1656. struct v4l2_device *v4l2_dev = &video->v4l2_dev;
  1657. struct vb2_queue *vbq = &video->queue;
  1658. struct video_device *vdev = &video->vdev;
  1659. struct v4l2_ctrl_handler *hdl = &video->ctrl_handler;
  1660. int rc;
  1661. video->pix_fmt.pixelformat = V4L2_PIX_FMT_JPEG;
  1662. video->pix_fmt.field = V4L2_FIELD_NONE;
  1663. video->pix_fmt.colorspace = V4L2_COLORSPACE_SRGB;
  1664. video->pix_fmt.quantization = V4L2_QUANTIZATION_FULL_RANGE;
  1665. video->v4l2_input_status = V4L2_IN_ST_NO_SIGNAL;
  1666. rc = v4l2_device_register(video->dev, v4l2_dev);
  1667. if (rc) {
  1668. dev_err(video->dev, "Failed to register v4l2 device\n");
  1669. return rc;
  1670. }
  1671. v4l2_ctrl_handler_init(hdl, 4);
  1672. v4l2_ctrl_new_std(hdl, &aspeed_video_ctrl_ops,
  1673. V4L2_CID_JPEG_COMPRESSION_QUALITY, 0,
  1674. ASPEED_VIDEO_JPEG_NUM_QUALITIES - 1, 1, 0);
  1675. v4l2_ctrl_new_std_menu(hdl, &aspeed_video_ctrl_ops,
  1676. V4L2_CID_JPEG_CHROMA_SUBSAMPLING,
  1677. V4L2_JPEG_CHROMA_SUBSAMPLING_420, mask,
  1678. V4L2_JPEG_CHROMA_SUBSAMPLING_444);
  1679. v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_mode, NULL);
  1680. v4l2_ctrl_new_custom(hdl, &aspeed_ctrl_HQ_jpeg_quality, NULL);
  1681. rc = hdl->error;
  1682. if (rc) {
  1683. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1684. v4l2_device_unregister(v4l2_dev);
  1685. dev_err(video->dev, "Failed to init controls: %d\n", rc);
  1686. return rc;
  1687. }
  1688. v4l2_dev->ctrl_handler = hdl;
  1689. vbq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1690. vbq->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
  1691. vbq->dev = v4l2_dev->dev;
  1692. vbq->lock = &video->video_lock;
  1693. vbq->ops = &aspeed_video_vb2_ops;
  1694. vbq->mem_ops = &vb2_dma_contig_memops;
  1695. vbq->drv_priv = video;
  1696. vbq->buf_struct_size = sizeof(struct aspeed_video_buffer);
  1697. vbq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1698. vbq->min_queued_buffers = ASPEED_VIDEO_V4L2_MIN_BUF_REQ;
  1699. rc = vb2_queue_init(vbq);
  1700. if (rc) {
  1701. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1702. v4l2_device_unregister(v4l2_dev);
  1703. dev_err(video->dev, "Failed to init vb2 queue\n");
  1704. return rc;
  1705. }
  1706. vdev->queue = vbq;
  1707. vdev->fops = &aspeed_video_v4l2_fops;
  1708. vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
  1709. V4L2_CAP_STREAMING;
  1710. vdev->v4l2_dev = v4l2_dev;
  1711. strscpy(vdev->name, DEVICE_NAME, sizeof(vdev->name));
  1712. vdev->vfl_type = VFL_TYPE_VIDEO;
  1713. vdev->vfl_dir = VFL_DIR_RX;
  1714. vdev->release = video_device_release_empty;
  1715. vdev->ioctl_ops = &aspeed_video_ioctl_ops;
  1716. vdev->lock = &video->video_lock;
  1717. video_set_drvdata(vdev, video);
  1718. rc = video_register_device(vdev, VFL_TYPE_VIDEO, 0);
  1719. if (rc) {
  1720. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1721. v4l2_device_unregister(v4l2_dev);
  1722. dev_err(video->dev, "Failed to register video device\n");
  1723. return rc;
  1724. }
  1725. return 0;
  1726. }
  1727. static int aspeed_video_init(struct aspeed_video *video)
  1728. {
  1729. int irq;
  1730. int rc;
  1731. struct device *dev = video->dev;
  1732. irq = irq_of_parse_and_map(dev->of_node, 0);
  1733. if (!irq) {
  1734. dev_err(dev, "Unable to find IRQ\n");
  1735. return -ENODEV;
  1736. }
  1737. rc = devm_request_threaded_irq(dev, irq, NULL, aspeed_video_irq,
  1738. IRQF_ONESHOT, DEVICE_NAME, video);
  1739. if (rc < 0) {
  1740. dev_err(dev, "Unable to request IRQ %d\n", irq);
  1741. return rc;
  1742. }
  1743. dev_info(video->dev, "irq %d\n", irq);
  1744. video->eclk = devm_clk_get(dev, "eclk");
  1745. if (IS_ERR(video->eclk)) {
  1746. dev_err(dev, "Unable to get ECLK\n");
  1747. return PTR_ERR(video->eclk);
  1748. }
  1749. rc = clk_prepare(video->eclk);
  1750. if (rc)
  1751. return rc;
  1752. video->vclk = devm_clk_get(dev, "vclk");
  1753. if (IS_ERR(video->vclk)) {
  1754. dev_err(dev, "Unable to get VCLK\n");
  1755. rc = PTR_ERR(video->vclk);
  1756. goto err_unprepare_eclk;
  1757. }
  1758. rc = clk_prepare(video->vclk);
  1759. if (rc)
  1760. goto err_unprepare_eclk;
  1761. of_reserved_mem_device_init(dev);
  1762. rc = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  1763. if (rc) {
  1764. dev_err(dev, "Failed to set DMA mask\n");
  1765. goto err_release_reserved_mem;
  1766. }
  1767. if (!aspeed_video_alloc_buf(video, &video->jpeg,
  1768. VE_JPEG_HEADER_SIZE)) {
  1769. dev_err(dev, "Failed to allocate DMA for JPEG header\n");
  1770. rc = -ENOMEM;
  1771. goto err_release_reserved_mem;
  1772. }
  1773. dev_info(video->dev, "alloc mem size(%d) at %pad for jpeg header\n",
  1774. VE_JPEG_HEADER_SIZE, &video->jpeg.dma);
  1775. aspeed_video_init_jpeg_table(video->jpeg.virt, video->yuv420);
  1776. return 0;
  1777. err_release_reserved_mem:
  1778. of_reserved_mem_device_release(dev);
  1779. clk_unprepare(video->vclk);
  1780. err_unprepare_eclk:
  1781. clk_unprepare(video->eclk);
  1782. return rc;
  1783. }
  1784. static const struct of_device_id aspeed_video_of_match[] = {
  1785. { .compatible = "aspeed,ast2400-video-engine", .data = &ast2400_config },
  1786. { .compatible = "aspeed,ast2500-video-engine", .data = &ast2500_config },
  1787. { .compatible = "aspeed,ast2600-video-engine", .data = &ast2600_config },
  1788. {}
  1789. };
  1790. MODULE_DEVICE_TABLE(of, aspeed_video_of_match);
  1791. static int aspeed_video_probe(struct platform_device *pdev)
  1792. {
  1793. const struct aspeed_video_config *config;
  1794. struct aspeed_video *video;
  1795. int rc;
  1796. video = devm_kzalloc(&pdev->dev, sizeof(*video), GFP_KERNEL);
  1797. if (!video)
  1798. return -ENOMEM;
  1799. video->base = devm_platform_ioremap_resource(pdev, 0);
  1800. if (IS_ERR(video->base))
  1801. return PTR_ERR(video->base);
  1802. config = of_device_get_match_data(&pdev->dev);
  1803. if (!config)
  1804. return -ENODEV;
  1805. video->jpeg_mode = config->jpeg_mode;
  1806. video->comp_size_read = config->comp_size_read;
  1807. video->frame_rate = 30;
  1808. video->jpeg_hq_quality = 1;
  1809. video->dev = &pdev->dev;
  1810. spin_lock_init(&video->lock);
  1811. mutex_init(&video->video_lock);
  1812. init_waitqueue_head(&video->wait);
  1813. INIT_DELAYED_WORK(&video->res_work, aspeed_video_resolution_work);
  1814. INIT_LIST_HEAD(&video->buffers);
  1815. rc = aspeed_video_init(video);
  1816. if (rc)
  1817. return rc;
  1818. rc = aspeed_video_setup_video(video);
  1819. if (rc) {
  1820. aspeed_video_free_buf(video, &video->jpeg);
  1821. clk_unprepare(video->vclk);
  1822. clk_unprepare(video->eclk);
  1823. return rc;
  1824. }
  1825. aspeed_video_debugfs_create(video);
  1826. return 0;
  1827. }
  1828. static void aspeed_video_remove(struct platform_device *pdev)
  1829. {
  1830. struct device *dev = &pdev->dev;
  1831. struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
  1832. struct aspeed_video *video = to_aspeed_video(v4l2_dev);
  1833. aspeed_video_off(video);
  1834. aspeed_video_debugfs_remove(video);
  1835. clk_unprepare(video->vclk);
  1836. clk_unprepare(video->eclk);
  1837. vb2_video_unregister_device(&video->vdev);
  1838. v4l2_ctrl_handler_free(&video->ctrl_handler);
  1839. v4l2_device_unregister(v4l2_dev);
  1840. aspeed_video_free_buf(video, &video->jpeg);
  1841. of_reserved_mem_device_release(dev);
  1842. }
  1843. static struct platform_driver aspeed_video_driver = {
  1844. .driver = {
  1845. .name = DEVICE_NAME,
  1846. .of_match_table = aspeed_video_of_match,
  1847. },
  1848. .probe = aspeed_video_probe,
  1849. .remove_new = aspeed_video_remove,
  1850. };
  1851. module_platform_driver(aspeed_video_driver);
  1852. module_param(debug, int, 0644);
  1853. MODULE_PARM_DESC(debug, "Debug level (0=off,1=info,2=debug,3=reg ops)");
  1854. MODULE_DESCRIPTION("ASPEED Video Engine Driver");
  1855. MODULE_AUTHOR("Eddie James");
  1856. MODULE_LICENSE("GPL v2");